Fig. 4.3 illustrates the ID-VG transfer characteristic of 5 μm gate length for GaAs MOSFET with Ge-S/D, and the ratio Ion (VD = 2 V)/Ioff (VD = 2 V) is about 2.59×101, It is because Ge have found that the Fermi level at metal-Ge Schottky barriers is pinned near the valence band of Ge for a variety of metals. So Ge Source/Drain has the poorer sheet resistance.
Therefore, we must research methods to reduce conduction band offset. The technique by inserting ultrathin dielectrics result in low ΦBN. Fig. 4.4 illustrates the ID-VG transfer characteristic of 10 μm gate length for GaAs MOSFET with Ge-S/D by inserting TiO2
interfacial layer, and the ratio Ion (VD = 1 V)/Ioff (VD = 1 V) ratio is about 2.5×102.
According to Fig. 4.3 and Fig. 4.4, the contact resistivity was significantly reduced by
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inserting TiO2 interfacial layer, so on-state current is more large than without TiO2 interfacial layer.
4.5 Summary
GaAs have low density of states (DOS), tending to reduce the inversion charge (Qinv) and hence reduce drive current. In addition, Ge have more high solid solubility and lattice match to GaAs. Thus, we propose that Ge selective epitaxial growth be used as source/drain of III-V MOSFETs.
The Fermi level at metal-Ge Schottky barriers is pinned near the valence band of Ge for a variety of metals. We use TiO2 interfacial layer on GaAs for MIS source/drain structure to reduce electron schottky barrier height (ΦBN). Finally, the GaAs MOSFET with embedded Ge source/drain successfully was improvement.
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Reference
[1] Guang-Li Luo, Zong-You Han, et al. “Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs” Journal of The Electrochemical Society, vol.157, 2010.
[2] G. K. Dalapati, M. K. Kumar, et al “Interfacial and Electrical Characterization of Atomic-Layer-Deposited HfO2 Gate Dielectric on High Mobility Epitaxial GaAs/Ge Channel Substrates” Journal of The Electrochemical Society, vol.157, 2010.
[3] M.V. Fischetti, L. Wang, et al “Simulation of Electron Transport in High-Mobility MOSFETs: Density of States Bottleneck and Source Starvation” IEEE, 2007.
[4] N.Sugiyama, Y. Moriyama et al. “Kinetics of epitaxial growth of Si and SiGe film on(110) Si substrates” Applied Surface Science, 2004.
[5] J.M. Hartmann, M. Burdin, et al “Growth kinetics of Si and SiGe onSi(100), Si(110), and Si(111) surfaces” Journal of Crystal Growth, 2006.
[6] D. Connelly, C. Faulkner, et al “Self-Aligned Low-Schottky Barrier Deposited Metal S/D MOSFETs with Si3N4 M/Si Passivation” Appl. Phys. Lett. vol.88, p.012105, 2006.
[7] M.Kobayashi, A. Kinoshita, et al “Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application” J.
Appl. Phys. vol.105, p.023702, 2009.
[8] R.R. Lieten, S. Degrrote, et al. “Ohmic contact formation on n-type Ge” Appl. Phys. Lett.
vol.92, p.022106, 2008.
[9] T.Nishimura, K. Kita, et al. “Control of high-k/germanium interface properties through selection of high-k materials and suppression of GeO volatilization” Appl. Phys. Express, p.051406, 2008.
[10] J.Y. Jason Lin, Arunanshu M. Roy, et al “Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height”
Applied physics letters, vol.98, 2011.
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Fig. 4.1 The scheme and process flow of GaAs MOSFET.
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-1.0 -0.5 0.0 0.5 1.0
1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
Current (A)
Voltage (V)
TiO2 0cyc TiO2 30cyc TiO2 60cyc TiO2 90cyc
Fig. 4.2 the I-V characteristics of the Al/TiO2/Ge structures
Fig. 4.3 Transfer characteristic for E-mode GaAs n-MOSFET with Ge-S/D.
0 1 2 3 4 5
1E-6 1E-5 1E-4 1E-3
0.01ALD-Al2O3/SI(111)A GaAs n-MOSFET with Ge S/D
Drain Current(A/m)
Gate Voltage(V)
VD=2V VD=3V W/L=100um/5um
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Fig. 4.4 Transfer characteristic for E-mode GaAs n-MOSFET with Ge-S/D by inserting TiO2
interfacial layer
0.0 0.5 1.0 1.5 2.0 2.5 3.0
1E-6 1E-5 1E-4 1E-3 0.01
W/L=100um/10um
ALD-TiO2/Al2O3/SI(111)A GaAs n-MOSFET with Ge S/D
VG (V) I D (uA/um)
VD=2V VD=3V S.S.=270mV/dec
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Chapter 5
Conclusions and Future work
5.1 Conclusions
In this thesis, firstly, we have studied the electrical characteristic of GaAs capacitors with Al2O3 dielectric. Unlike SiO2 on Si, III-V materials such as GaAs don’t have such a native oxide that have high quality, thermodynamically stable properties that can be stable on the device criteria as SiO2 on Si. Poor dielectric quality results in frequency dispersion, hysteresis, flab band shift, and unfavorable low dielectric constant. According to the result of C-V and conductance measurement, we believed that the surface treatment of silane passivation and PDA can efficiently diminish the formation of GaAs(100) native oxide, thus improve the effect of Fermi-level pinning appearance. Next, we analyzed reliability for silane passivation. A clear understanding of reliability of this different interfaces, via charge trapping/detrapping studies under different stressing condition, we observed the SiH4 passivation can improve the reliability of GaAs(100). But GaAs(111)A had the best surface band bending and lower value of Dit in the middle of bandgap, we assumed that the improvement resulted from the different structure of surface on orientation. The Fermi level pinning is not an intrinsic property of GaAs.
After we improved interface of III-V, we explored S/D resistance and junction.
According to electrical characteristics, we discovered that the sheet resistivity at 30keV&80keV is lower than 50keV implant energy. However, the contact resistivity is just contrary. In addition, from the point of temperature, we found that the sheet resistivity at 850℃ is lower than 950℃, and the contact resistivity is just contrary. But, the junction of
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forward current didn’t suppress significantly at alloy metal 400oC 30s. We optimize conditions of sheet resistivity, contact resistivity, and Ohmic RTA time.
Finally, we used these conditions to fabricate metal-oxide-semiconductor field effect transistors with the different surface orientation successfully and measured electrical characteristics. In addition, we also fabricated GaAs MOSFET with embedded Ge source/drain and studied electrical characteristics. But the resistances were lager for all MOSFET that we fabricated.
5.2 Future work
Although III-V compound semiconductors have high electron mobility and high velocity satuation. But one of the most critical challenge is the lower values of solid solubility and the density of states ( DOS ). For example, the maximum solid solubility and the DOS are 1 × 1019 and 4.7 × 1017 cm-3, respectively, on GaAs substrate, which are lower, compared to Si [18]. Therefore, these material properties contribute the more source/drain ( S/D ) resistance and hence suppress the maximum operate current. Therefore, we proposed a new structure of the III-V channel MOSFET to solve these problems and hence enhance the current drive. In present, in order to overcome the solid solubility limit, the metal S/D structure is one of the most promising ways to reduce the resistance of S/D.
In addition, the Ge-S/D structure of GaAs MOSFET can solve the most critical challenge. And III-Vs cannot make good p-channels, which are also needed for CMOS, because their hole mobilities are relatively low. Using the epitaxial technology to form the Ultimate CMOS structure composed of the combination of III-V semiconductors n-MOSFETs and Ge p-MOSFETs on insulators.
Except for improving the performance of the GaAs nMOSFET, the reliability characteristics of MOSFET with ALD-Al2O3 films is also worth investigating. Accelerated
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life-test of MOS devices is conventionally performed by applying a constant gate voltage ( CVS ) or injecting a constant gate current ( CCS ) over a period of time to monitor the oxide degradation. In addition, time to dielectric breakdown ( TDDB ) under constant-voltage stressing is considered a very important parameter in determining the gate oxide reliability and integrity.
Non-planar, multi-gate architectures have been investigated for improved electrostatics in Si MOSFETs. In recently, III-V MOSFETs start to be reported. The structure can efficiently increase gate control ability and move the Fermi-level effectively.
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