Admittance Behavior of GaAs MOS capacitor

2.5

GaAs MOS capacitor

2.5.1 Conductance Method to Extract Dit

The conductance method is one of the most sensitive methods to determine Dit, so it is the means of choice to extensively study the interface passivation. Through understanding of the conductance method allow proper extraction of the interface trap across the bandgap. First of all, we have to understand that conductance is extracted since the substrate conductance

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only is contributed from interface density and the band diagram of MOS capacitor is showed in Fig. 2.9. Where is a gate voltage V_G applied between the metal and the semiconductor, which fixes the value of the surface Fermi level. The C-V measurements consist in applying on top of the static gate bias voltage a small sinusoidal voltage with frequency f and amplitude of 25 mV. This small periodic gate voltage causes the bands and the surface potential in the semiconductor to periodically move up and down, causing the interface traps lying around the value of the surface potential to fill and empty. Only if the traps around the surface potential have a characteristic response time that is of the order of the measurement frequency f can they interact with the measurement ac signal and affect the total impedance of the MOS capacitor. The conductance uses a simplified equivalent circuit of the capacitance and the parallel conductance, as seen in equivalent circuit model of Fig. 2.10. It consists of the oxide capacitance C_ox, the semiconductor capacitance C_s, and the interface state capacitance Cit. The capture-emission of carriers by Dit is a losing process, represented by the resistance R_it. It is convenient to replace the circuit of Fig. 2.10(a) by Fig. 2.10(b), where Cp and Gp are given by

where Cit = q²Dit , ω=2πf, f is measurement frequency, and = RitCit, the characteristic emission frequencies of trapped charge carriers, given by .

Equation (2.5) and Equation (2.6) is valid for an interface trap with single energy level in the bandgap. In reality, interface traps are continuously distributed across the bandgap. If the time constant dispersion and trap energy level distribution across bandgap are taken into account, eq. (2.6) is modified:

(2.7)

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When Gp/ is plotted as a function of f, the maximum appears at f , and at that maximum

(2.8) Gp/ plots are repeated at different gate voltages to scan trap energies to obtain an interface state density distribution across the bandgap. By utilizing eq. (2.9), can be determined from the measurement ( ) by eliminating the oxide capacitance.

(2.9)

The flows of conductance method to extract D_it in Fig. 2.11.

2.5.2 Conductance method application of GaAs MOS capacitor

It is worthy to note that according to the emission time constant ( ), the behavior of interface trap time constant as a function of temperature determines the part of interface traps in the bandgap observable in the MOS admittance characteristic. That is, traps located nearer to midgap become observable for higher temperatures while traps more located toward the band edges become observable for lower temperature. We assumed the capture cross section σ = 1×10^-15 cm² and plotted the characteristic emission frequencies of trapped charge carriers in GaAs at the different temperature as a function of the position of the trap in

the energy bandgap.For high band gap GaAs, midgap traps are not able to be observed at room temperature; if increasing the temperature, the observable energy windows shift toward

the midgap as shown in Fig 2.12, where the effective density of states of the conduction (N_c) and the valence (Nv) bands, electron and hole thermal velocity, change in GaAs bandgap with

temperature are all taken into account. Fig 2.13 and Fig. 2.14 illustrates the Gp/ versus f plots of MOS capacitor for different orientation and measurement is performed at room temperature. Gp/ curves are shown at the gate voltages Fermi level is only portions of the

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bandgap where interface states are able to capture and emission with the small signal AC bias.

The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. Then, the equation combined with

the value of maximum value of Gp/ transforms the Dit (VG) into Dit (E) plot.

2.5.3 High Temperature Measurement of GaAs MOS capacitor

In order to obtain the full distribution of D_it in the bandgap, conductance method is applied at high temperatures. The multi frequency CV characteristics measured at 423K are shown in Fig. 2.15 and Fig.2.16 for different orientation. Fig. 2.17 and Fig.2.18 Gp/ curves are shown at the gate voltages Fermi level is near the midgap where interface states are able to capture and emission with the small signal AC bias. The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. We interpret the largest G_p/ω value to represent Dit at the specific position in bandgap.

the Dit profile of each sample for GaAs(100) is demonstrated in Fig 2.19 compared to GaAs(111)A.

According to these figures, we saw that Dit was not high for middle of the bandgap obviously for n-type GaAs(111)A and p-type GaAs(111)A compared to the GaAs orientation of (100). Once again, the electrical characteristics proved that the Fermi level pinning is not an intrinsic property of GaAs.