3.6 Reliability characteristics of GaAs(100) with silane passivation
3.7.3 Result and conclusions
Fig. 3.21 displayed the ID-VG characteristics with a drain bias of 0.1V and 2V. The gate length of the device is 10μm and the gate width is 100μm the value of Vth was 1.25 V which is extracted by linear extrapolation.
The ID versus VD output characteristics of the device are presented in Fig. 3.22 with Vg
from 0V to 3V and a step of 1 V. The drive current at Vg =3V is ~3.5nA/μm measured at VD = 3V.
3.8 Summary
Unlike SiO2 on Si, III-V materials such as GaAs don’t have such a native oxide that have high quality, thermodynamically stable properties that can be stable on the device criteria as SiO2 on Si. Poor dielectric quality results in frequency dispersion, hysteresis, flab band shift, and unfavorable low dielectric constant. In the section 3.3 and 3.4, we can obviously see these phenomenon for GaAs(100) without passivation. We investigated the surface treatment effects on the electrical characteristics of GaAs(100) capacitors with silane passivation and PDA. The pretreatment diminished the formation of GaAs native oxide, thus improve the effect of Fermi-level pinning appearance. According to these electrical characteristics, the passivation sample displayed not only small frequency dispersion, but also small hysteresis. In order to confirm the electrical characteristics, we used the conductance method to extract distributions of Dit for different interface passivation. At the first, we measured the multi-frequency of Cm-f and Gm-f which are measured at the different temperature conditions. Next, we calculated the Gp/ωand extracted Dit by conductance method, we can accurately determined Dit distribution across the bandgap. And then, we measured the reliability of P-GaAs(100) without and with silane passivation. A clear understanding of reliability of this different interfaces, via charge trapping/detrapping studies under different
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stressing condition, we observed the silane passivation can improve the reliability of GaAs(100). Finally, utilizing the electrical characteristic of the GaAs MOS capacitor to decide the experimental condition is suitable in manufacture procedure of enhance-mode GaAs(100) MOSFET.
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Fig. 3.1 The structure and process flow of MOS capacitor.
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Fig. 3.2 Multi-frequency C-V curve (a) N-type GaAs(100) (b) P-type GaAs(100)
-2 -1 0 1 2 3 4
Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle Al/Al2O3/GaAs P(100)/NiGeAu Cap TMA20cycle
75
76
Fig. 3.4 Hysteresis C-V curve (a) N-type GaAs(100) (b) P-type GaAs(100)
-1 0 1 2 3 4
Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle
Al/Al2O3/GaAs P(100)/NiGeAu Cap TMA20cycle
Al2O3150cycle f=100kHz
C(F/cm2 )
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Fig. 3.5 Multi-frequency C-V curve (a) N-type GaAs(100)with SiH4 passivation (b) P-type GaAs(100) with SiH4 passivation
-2 -1 0 1 2 3 4 5
Al/Al2O3/GaAs N(100)/NiGeAu Cap Si passivation 90s
Al/Al2O3/GaAs P(100)/TiPtAu Cap Si passivation 90s
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Fig. 3.5 Hysteresis C-V curve (c) N-type GaAs(100) with SiH4 passivation (d) P-type GaAs(100) with SiH4 passivation
-2 -1 0 1 2 3 4
Al/Al2O3/Si/GaAs N(100)/NiGeAu Cap Si passivation 90s Si passivation 90s As
Hysteresis
~300mV
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Fig. 3.6 Multi-frequency C-V curve (a) N-type GaAs(100)PDA (b) P-type GaAs(100)PDA
-2 -1 0 1 2 3 4
Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle Al/Al2O3/GaAs P(100)/NiGeAu Cap TMA20cycle
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Fig. 3.6 Hysteresis C-V curve (c) N-type GaAs(100)PDA (d) P-type GaAs(100)PDA
-1 0 1 2 3 4 Al/Al2O3/GaAs N(100)/NiGeAu Cap
TMA20cycle Al/Al2O3/GaAs P(100)/NiGeAu Cap TMA20cycle
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Fig. 3.7 Multi-frequency C-V curve (a) N-type GaAs(100)with SiH4 passivation and PDA (b) P-type GaAs(100) with SiH4 passivation and PDA
-2 -1 0 1 2 3 4 5
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Fig. 3.7 Hysteresis C-V curve (c) N-type GaAs(100) with SiH4 passivation and PDA (d) P-type GaAs(100) with SiH4 passivation and PDA
-2 -1 0 1 2 3 4
Al/Al2O3/Si/GaAs N(100)/NiGeAu Cap Si passivation 90s
Al/Al2O3/GaAs P(100)/TiPtAu Cap Si passivation 90s
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Fig. 3.8 Multi-frequency C-V curve 300K (a) N-type GaAs(100)PDA (b) P-type GaAs(100)PDA
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Fig. 3.9 Multi-frequency C-V curve 300K (a) N-type GaAs(100)with SiH4 and PDA (b) P-type GaAs(100) with SiH4 and PDA
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Fig. 3.10 Gp/ as a function of frequency at 25℃ (a) N-type GaAs(100)PDA (b) P-type GaAs(100)PDA
100 1000 10000 100000 1000000
0.0
100 1000 10000 100000 1000000
0.0
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Fig. 3.11 Gp/ as a function of frequency at 25℃ (a) N-type GaAs(100)PDA (b) P-type GaAs(100)PDA
100 1000 10000 100000 1000000
0.0
100 1000 10000 100000 1000000
0.00
Al/Al2O3/GaAsP(100)/TiPtAu Si Passivation 90s PDA
300K
Gp/ (F /cm2 )
Frequency(Hz)
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Fig. 3.12 the Dit profile of GaAs(100) with SiH4 passivation at 300K
-3 -2 -1 0 1 2 3
0.1 0.2 0.3 0.4
Al/Al2O3/GaAsP(100)/TiPtAu Si Passivation 90s
100 1000 10000 100000 1000000
0.00
100 1000 10000 100000 1000000
0.00 0.05
0.10 Al/Al2O3/GaAsP(100)/TiPtAu
Si Passivation 90s
Trap energy within bandgap (eV) Dit (1012 /eVcm2 )
P300K N300K
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Fig. 3.13 Multi-frequency C-V curve 425K (a) N-type GaAs(100) (b) P-type GaAs(100)
-1 0 1 2 3
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Fig. 3.14 Multi-frequency C-V curve 425K (a) N-type GaAs(100)with SiH4 passivation (b) P-type GaAs(100) with SiH4 passivation
(a)N-type
Al/Al2O3/GaAsP(100)/TiPtAu Si Passivation 90s
90
Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle
100 1000 10000 100000 1000000
0.0
Al/Al2O3/GaAsP(100)/TiPtAu TMA20cycle
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Fig. 3.16 Gp/ as a function of frequency at 150℃ (a) N-type GaAs(100)with SiH4 and PDA (b) P-type GaAs(100) with SiH4 and PDA
100 1000 10000 100000 1000000
0.0 0.5 1.0 1.5 2.0 2.5
Al / Al2O3 /GaAsN(100)/ NiGeAu Si passivation 90s
PDA 600oC 15s 425K
Gp/ (F /cm2 )
Frequency(Hz)
(a)N-type
(b)P-type GaAs(100)
100 1000 10000 100000 1000000
0.0 0.5 1.0
Al/Al2O3/GaAsP(100)/TiPtAu Si Passivation 90s PDA
425K
Gp/ (F /cm2 )
Frequency(Hz)
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Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle
Al/Al2O3/GaAsP(100)/TiPtAu TMA20cycle
Al/Al2O3/GaAs N(100)/NiGeAu Cap TMA20cycle
Al/Al2O3/GaAsP(100)/TiPtAu PDA
Trap energy within bandgap (eV) Dit (1012 /eVcm2 )
P(100)423K N(100)400K
93
Trap energy within bandgap (eV) Dit (1012 /eVcm2 ) Al/Al2O3/GaAsP(100)/TiPtAu Si Passivation 90s PDA
425K
100 1000 10000 100000 1000000
0.00
100 1000 10000 100000 1000000
0.00 0.05
0.10 Al/Al2O3/GaAsP(100)/TiPtAu
Si Passivation 90s PDA
425K
Gm/ (F /cm2 )
Frequency(Hz)
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Fig. 3.19 High frequency capacitance–voltage (C–V) characteristics of MOS capacitors employing (a) Al2O3/P-GaAs and (b) Al2O3/Si/P-GaAs structures.
(a) P-type GaAs(100)PDA
(b) P-type GaAs(100)with SiH4
passivation and PDA
-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.2
0.3 0.4
Capacitance(m/cm2 )
Gate Voltage(V)
Flash CVS:-3V CVS:-4V CVS:-5V
Al / Al2O3 / GaAs(100)
-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.2
0.3 0.4
Al / Al2O3 / Si /GaAs(100)
Capacitance (m/cm2 )
Gate Voltage(V)
Flash CVS:-3V CVS:-4V CVS:-5V
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Fig. 3.20 The scheme and process flow of GaAs MOSFET.
96
Fig. 3.21 Id-Vg of enhancement mode GaAs n-MOSFET
Fig. 3.22 Id-Vd characteristics of enhancement mode GaAs n-MOSFET
-1 0 1 2 3 4
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Chapter 4
GaAs NMOSFET with Embedded-Ge Source/Drain
4.1 Introduction
III-V materials have significantly smaller effective mass and higher electron mobility compared to Si and Ge. Although their small transport mass leads to high injection velocity (vinj), III-V materials have low density of states (DOS), tending to reduce the inversion charge (Qinv) and hence reduce drive current. It result high source/drain resistance and source starvation. The source starvation is that the inability of the source region to sustain a large flow of carriers in 'longitudinal' velocity states in the channel, unless the momentum relaxation rate and/or the doping density in the source are sufficiently large.
Therefore, we propose that Ge selective epitaxial growth be used as source/drain of III-V MOSFETs. Ge have more high solid solubility than III-V materials. In addition, III-V materials such as GaAs are lattice matched to Ge. The NMOSFETs possess higher solid solubility and higher channel mobility. However, In the case of Ge we have found that the Fermi level at metal-Ge Schottky barriers is pinned near the valence band of Ge for a variety of metals. It will bring large parasitic resistance in the S/D regions that can be significantly worse in III-V NMOSFET [1-5]
Recently, researchers used a ultrathin dielectrics inserted between metal and substrate such as Ge3N4, Al2O3, GeO2 and Si3O4 [6-9]. In this chapter, we use TiO2 [10] as the insulating layer for n+ source/drain regions for application in n-channel GaAs MOSFETs.
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4.2 Experimental process
In Ge-S/D MOSFET fabrication, the first step is the S/D region etching by the solution with H3PO4:H2O2:H2O = 1:1:160 (the etching rate ~0.5 nm/s). After surface cleaning, the growth of Ge was carried out by using a UHV/CVD system with a base pressure of less than 5
× 10-8 Torr. After GaAs wafers were loaded into the growth chamber, they were first in situ prebaked at 550°C for 10 min. Then, the Ge layer was grown at the same temperature with a constant GeH4 flow rate. Throughout the entire growth process, the gas pressure in the growth chamber was kept at 30 mTorr.
Next, the S/D regions were implanted with phosphorus at doses of 5 × 1014 cm-2 and 1 × 1015 cm-2 at 50keV and 30keV, respectively. Subsequently, a Al2O3 layer was deposited by atomic layer deposited (ALD), and then, the sample was annealed in a N2 ambient at 600 °C for 30 s by rapid thermal annealing (RTA).
After etching the S/D contact holes, Thermal coatered Al about 4000 Å were patterned as gate electrodes and Source/Drain pattern through the lithography. The fully process flow of Ge-S/D MESFET was shown in Fig. 4.1.