2.6.1 Introduction
In general, the condition of suitable gate dielectric on MOSFET will require: (a) the oxides do not react with the substrates. (b) The band offset of the oxide on the semiconductor is required to have over 1eV to inhibit leakage.
The high mobility materials are applied in MOSFET to obtain higher device
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performance than Silicon. In particular, Ge and III-V based are promising material to use in place of conventional Si MOSFETs. Recently, high-k/Ge p-MOSFET characteristics have been reported have high performance characteristic recently [9-10]. However, Ge n-MOSFETs remains have challenging because of the resulting from low electron mobility and the asymmetrical distribution of interface states that result in the Fermi level (EF) pinning.
In addition, III-V materials have higher electron mobility than Ge, we showed some III-V materials’ advantages in Fig. 2.20. In present, the several promising MESFET and n-MOSFET device characteristics based on III-V channels have been continually demonstrated [11-16], and their performances even exceeded the strained-Si transistors at the nano-scale devices [17]. In order to obtain the superior III-V device performance, it is essential to achieve the unpinned oxide/substrate interface.
In this chapter, we fabricated the circular transmission line method (CTLM) for analyzing contact and sheet resistivity. And then, we fabricated the junction of different conditions. After optimizing the conditions of CTLM and junction, we also succeeded to fabricate the enhancement-mode (E-mode) GaAs n-MOSFET with ALD- Al2O3 gate dielectrics on the GaAs substrate.
2.6.2 Source/Drain Ohmic Contact on GaAs 1. Introduction
The resistance is an importance factor for metal-oxide-semiconductor field effect transistors (MOSFET) device performance. The contact resistance is the most importance among series resistances.
How to decide it is a good contact? The ohmic contact is a right method to determine.
Ohmic contacts have a linear current-voltage characteristic. The contacts have to be able to supply the necessary device current, and the voltage drop across the contact should be small compared to the voltage drops across the active regions. We fabricated the circular transmission line method (CTLM) for analyzing contact and sheet resistivity. The problem of
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W≠L of TLM can be avoided with circular test structure [18], including of a conducting circular inner region of radius r, a gap of width d, and a conducting circular outer region R in Fig. 2.21. The total resistance between the internal and the external contacts is
, LT=
where I and K are the Bessel functions of the first order. Due to L 4LT, the Bessel function ratios I0/I1 and K0/K1 tend to unity and RT simplifies to
In the circular transmission line test structure, due to r d, the equation becomes
, where C=
For d / r 1, the above equation simplifies to
, LT=
According to above equation, we firstly measured the relationship of RT and d, and find line to fit it. The ρs and can be extracted. Finally, the value of ρc utilizes LT to obtain in Fig. 2.22.
2. Experimental Procedures
The samples, firstly, were implanted the Silicon doses 1 × 1014 cm-2 at 50 keV After deposit SiO2 capping layer, activation was using RTA at 750℃,850℃ and 950℃ for 15 s in N2 ambient. Then, we used Acetone to remove metal-organic residues and the metal of Ni/Ge/Au ( 30 nm/70 nm/180 nm ) was deposited by using E-gun system and lift-off process, the CTLM structure in Fig. showed. Alloy metal was formed by RTA at 400 ℃ for 30s.
3. Results and Discussions
First, due to activation was using RTA at 750℃showed current characteristics couldn’t
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limiting, so we remove the condition of 750℃. We designed the conditions of different activity temperature and implant energy on SI-(111)A substrate in shown Fig. 2.23 (a), (b), (c), (d) and Table 1.
In these result, from the point of implant energy, we discovered that the sheet resistivity at 30keV&80keV is lower than 50keV implant energy. However, the contact resistivity is just contrary. In addition, from the point of temperature, we found that the sheet resistivity at 850℃ is lower than 950℃, and the contact resistivity is just contrary. We can conclude the optimized condition for GaAs ohmic contact that was implanted at 50keV and the activity temperature at 850℃. Fig. 2.24 show the optimized condition on SI-(100) GaAs substrate.
Next, we only designed the conditions of different implant energy for 850℃in shown Fig.2.25, Fig. 2.26 and Table2. It is because that some of condition for 950℃showed current characteristics couldn’t limiting( sheet resistivity is large ). Similarly, the optimized condition for GaAs ohmic contact was implanted at 50keV and the activity temperature at 850℃.
2.6.3 Source/Drain Junction on GaAs 1. Introduction
One of the most important properties is that their conductivity can be controlled by adding dopants. The conduction mechanisms for a metal on n-type semiconductor are described. For the low-doped semiconductor, the current mechanism is thermionic emission (TE). For the high-doped N+, the width was sufficiently narrow for tunneling directly, known as field emission (FE). In the intermediate-doped range, thermionic-field emission (TFE) dominates. Although many exciting results on GaAs MOS capacitors and enhance mode GaAs MOSFETs without source/drain implantation have been reported [19-21], and also the cost is higher and the throughput is lower. GaAs material have a challenge in fabricating is dopant’s low activation efficiency. It is because common source such as Si or Ge can replace either Ga atom or As atom to be donor or acceptor, respectively [22]. Hence, the net donor
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concentration would be the number of Si atoms occupying the Ga minus the number of Si atoms occupying the As. In order to increase the number of Si atoms occupying the Ga and increase the activation efficiency, we design the conditions of different activity temperature including 750℃, 850℃ and 950℃.
2. Experimental Procedures
In GaAs Junction fabrication, we used PECVD to deposit SiO2 420 nm as isolation layer, and then, we defined the Si implantation regions by photolithography, which were implanted the doses 1 × 1014 cm-2 at 50keV . After deposit SiO2 encapsulation layer, S/D activation was using RTA at different temperatures in N2 ambient. the metal of Ni/Ge/Au ( 30 nm/70 nm/180 nm ) was deposited at the S/D region by using E-gun system and lift-off process. Alloy metal was formed by RTA at 400 ℃ for 30s and 60s.
3. Results and Discussions
The GaAs P(111) N+/P junction current-voltage characteristic with Si implantation are shown in Table 3 and Fig. 2.27 measured by 4200. The alloy metal annealing time by RTA is 30s and 60s was also examined. From the experiments, we can conclude the optimized condition for GaAs Ohmic contact that was annealed at 400°C for 30s. In addition, we found thatthe ratio of forward to reverse current at this N+ /P junction is achieved to be as high as I forward / I reverse=107, indicating an activation temperature of 950 °C is enough to activate Si in GaAs and a high quality N+ /P junction. The reason is because that the defect was repaired, the junction reverse current could be reduced.
2.6.4 MOSFET on GaAs with atomic-layer-deposited Al2O3 as gate dielectrics
GaAs is one of materials for high performance due to its high electron mobility, high saturation velocity, and wide bandgap. GaAs MOSFET can be applied on a sensitive test. In this section, we fabricate GaAs MOSFETs for different orientation include (111)A and (100).
In GaAs MOSFET fabrication, we used ALD and PECVD to deposit Al2O3 10 nm and SiO2 420 nm as isolation layer, respectively, and then, defined the Si and P implantation
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regions, which were implanted the doses 1 × 1014 cm-2 at 50 keV and 1 × 1015 cm-2 at 60 keV, respectively. S/D activation was using RTA at 850℃ for 10 s in N2 ambient. And then the sample was cleaned by diluted HCl, diluted NH4OH, (NH4)2S solution. After surface cleaning, the sample was loading into the ALD chamber, followed by surface pretreatment with TMA pulse 20 cycles. Next, the Al2O3 gate dielectric was deposited by ALD at 250 ℃, followed by PDA at 600 °C for 15 s in an N2 ambient. Thermal coatered Al about 4000 Å were patterned as T-gate electrodes through the lithography. After excavating the S/D contact holes, the tri-layer of Ni/Ge/Au ( 30 nm/70 nm/180 nm ) was deposited at the S/D region by using E-beam system and lift-off process, followed by PDA at 400°C for 60 s in an N2 ambient to form Ohmic contact. The fully process flow of GaAs MOSFET was shown in Fig. 2.28.
Fig. 2.29 illustrates the ID-VG transfer characteristic of 4μm gate length for E-mode ALD-Al2O3/GaAs (111)A nMOSFET with TMA 20-cycles-pulse pretreatment and the ratio Ion (ID at VG = 3V, VD = 2V)/Ioff (ID at VG = 0V, VD = 2V) is 2.8×105. For device with the gate length/width of 4/100 μm, the value of Vth was 0.895 V which is extracted by linear extrapolation.
In Fig. 2.30, the well saturation and pinch-off characteristics were presented in ID-VD curves with the gate drive VG ranging from 0 to 3 V in steps of 0.5 V display and the maximum drain current was 46 μA/ μm measured at VG = 3 V, VD = 3 V.
The gate-to-channel capacitance and inversion charge density by Eq. (4.3)
and solving for the effective mobility μeff gives
where the drain conductance gd is defined as
Fig. 2.31 (a) depicts the effective mobility is obtained.
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The series resistance not only degrades the MOSFET current-voltage behavior, but also affects the mobility, since the effective mobility depends on drain conductance gd. ID depends on series resistance RSD, so also depends on RSD. The drain conductance becomes
Where gd0 is the drain conductance for RSD=0.
An early method is total resistance method that due to Terada and Muta, and Chern et al.
in 1980, with Rm =VDS/ID
(2.18) where Rch is the channel resistance, the intrinsic resistance of the MOSFET.
Equation (2.18) gives Rm=RSD for L= .Therefore, measuring a set of device with same channel width and different channel length (Fix VDS at 0.05V and VGS-Vth is set in the range from 0V to VDD), and then a plot of Rm versus L for devices with differing L and for varying gate voltages in Fig. . The intersection point represent RSD and .
Since S/D parasitic resistance can result in a significant reduction in the drain voltage falling across the channel and influence the drive current as well as the effective mobility extraction, the effective inversion mobility with RSD eliminated is depicted in Fig. 2.31 (b), utilizing eq. (4.1).
(2.19)