Overview

The main objective of this thesis is the development of small signal equivalent circuit models for RF MOSFETs and circuit simulation. This thesis is organized into six chapters as follows:

Chapter 2 provides the introduction to the non-quasi-statistic (NQS) effect for gate resistance in long channel devices and the NQS modeling in SPICE simulation.

Two-port and four-port S-parameters, as well as port reduction methods for four-port to two-port will be covered in this chapter.

In chapter 3 and Chapter 4, the equivalent circuit models will be developed

under different biasing conditions for two-port 3T and four-port 4T MOSFETs, respectively. The model parameters for both intrinsic and extrinsic components will be extracted under appropriate bias conditions. Then, an analysis will be performed on the extracted model parameters in the features under various biases and scalability over different geometries.

In chapter 5, the proposed equivalent circuit models will be verified through ADS simulation. It can be proven that the substrate network extracted from four-port 4T test structures can provide sufficient data base in terms of four-port S- and Y-parameters and facilitate the model accuracy for simulation under body biases.

Chapters 6 will make conclusions and address the future work for further study.

Chapter 2

Fundamental theory and RF MOSFET design

2.1 Non-quasi-statistic (NQS) effect

As the improvement of RF CMOS technology, the cut-off frequency is roughly inversely proportional to the gate length. In the longer channel devices, the channel charge relaxation time is finite, and then, the carries in the channel can not response to the signal immediately. NQS effect should be included for the equivalent circuit model to describe the device behavior accurately over a broad frequency.

2.1.1 Quasi-static (QS) model

In Quasi-static model, the channel charge is assumed to be a unique function of the instantaneous biases, the charges per unit area at any time are assumed to identical at any position. QS model assumption is described in Fig. 2.1, the gate capacitances are lumped into the intrinsic source and drain nodes, the signal form gate will couple to source and drain side directly, this model ignores that the charge built up in the center portion of the channel does not follow a change of gate biases as readily as at the source or drain edge of channel.

2.1.2 NQS model

It has been known that the carriers in the channel can not respond to the signal immediately nearly cut-off frequency, for long channel devices, the channel transit time is roughly inversely proportional to (Vgs-Vth) and proportional to square of channel length, NQS effect become pronounced in the application, considering the

input signal with rapid rise and fall times comparable to the channel transit time in Fig.

2.2, the channel charge is not a unique function of the instantaneous terminal voltage but a function of the history of the voltage, owing to the existence of the NQS effect, QS model will be not suit to the characteristic of devices with NQS effect at the operating frequency accurately.

The method to model NQS effect for RF application, one solution is to represent the channel as n transistors in series, this model wastes on the expense of simulation time but the behavior is accurately. One solution is the RC network approach, NQS model in BSIM3v3.2.2 was based on the circuit of Elmore model, the Elmore equivalent circuit can be viewed as a first step toward an NQS model, the channel charge buildup is modeled with reasonable accuracy because it retains the lowest frequency pole of the original RC network. Fig. 2.3 illustrates the QS and NQS equivalent circuit for SPICE simulation.

The Elmore resistance RElmore is calculated from the channel resistance in strong inversion as

gst ox eff eff

eff ch

eff eff Elomore

V C W Rch L

Q e R L

μ

μ ^~

2

∝

= (2.1)

Where e is the Elmore constant with a theoretical value close to 5 and Qch is the total charge in the channel, this formulation is only valid above threshold where the drift current dominates. The overall relaxation time τ is model as two components: τdrift

and τdiff. In strong inversion region, τdrift is dominates ; in subthreshold region, τdiff is dominates, the relaxation time τ can be written as follows:

drift diff

τ τ

τ

1 1

1 = +

(2.2)

where

gst eff

eff ox Elmore drift

V L L

W C

R μ

τ = ~

² (2.3)

KT qL_eff

diff

0 2

16μ

τ = (2.4)

2.2 Scattering parameters

At microwave frequency the Z, Y and H parameters are very difficult to measure, the reason is that short and open circuits to ac signals are difficult to implement at microwave frequencies, so that, the scattering matrix are used usually in the analysis of two port networks usually.

Considering the two-port network with incident wave a1 and reflected wave b1 at port1, and incident wave a2 and reflected wave b2 at port 2, the S parameters can be written in matrix form as:

⎥⎦

⎢ ⎤

⎣

⎥⎡

⎦

⎢ ⎤

⎣

=⎡

⎥⎦

⎢ ⎤

⎣

⎡

2 1 22 21

12 11 2

1

a a S S

S S b

b (2.5)

2.2.1 Two-port network parameters conversion

At a given frequency, a two-port network can be described in terms of several parameters. Therefore, there is a conversion relationship between the parameters, for example, the conversion relation between the S and Z parameters can be shown as:

[ ] [ ] [ ] [ ] [ ]

^{( ) (} 0 ⁾ 1

0 Z Z

Z Z

S = + ⁻ − (2.6)

[ ] [ ] [ ] [ ] [ ] [ ]

Z = Z0 (1 + S )(1 − S )⁻¹ (2.7) where is the characteristic impedance diagonal matrix, and

[

is the unit diagonal matrix. The other conversions among the Z, Y, H, and S parameters also be included in the ADS and ICCAP for using, they are useful to analyze the small signal

[

Z0

]

equivalent circuit.

]

1

2.2.2 Four-port

k is simple, the transmission lines

scattering parameters

or The extension of the formulation to four-port netw

are assumed to be lossless with characteristic impedance Z0, and then, we can write the scattering parameters of the four-port in matrix form

⎤ port common source configuration. For example, S11 can be arranged form the S matrix in (2.8) as

To measure S11, the matched resistive terminations of 50Ω are used at ports 2, 3, and

2.2.3 Port reduction method in S-parameters

of the extrinsic and intrin

(2.10) 4, and the ratio b1/a1 is obtained. In a two-port common source configuration, S11

is measured with reference resistance 50Ω at port 2 and source/body grounding.

Similarly, the parameters S12, S21, and S22 in four-port S matrix will be different form the parameters in two-port matrix.

Considering a 4-port networks system, the I-V relationship sic parameters can be written as a 4X4 Y matrix

According to equation (2.10), grounding a terminal is simply giving the corresponding zero supply volt d su

representing the resulting configuration of the MOSFET, therefore, the 4 x 4 matrix of the 4-port networks can be reduced

negligible, the reduced

⎦

⎣

⎦

⎣

⎦

⎣I Y Y V

matrix can be obtained by setting the corresponding supply voltage to zero.

2.3 RF MOSFET design

the measured S parameters are nditions and geometries, both two-port 3T and four-port 4T

Table 2.1 The device geometries of two-port 3T MOSFETs

age, and the remaine b-matrix will be the Y matrix

to 3-port or 2-port Y matrix.

For example, the common source(CS) configuration is source (port3) and body (port4) grounding, the CS 2-port Y matrix can be obtained by setting the Vs=Vb=0V in the 4-port measurement, in this case, the term of source and body in (2.10) is

Y matrix can be written as

⎥⎤

⎢⎡

⎥⎤

⎢⎡

⎥ =

⎢ ⎤

⎡

2 1 22 21

12 11 2

1 Y Y V

I

(2.11)

Similarly, the common gate and common drain Y

To understand the dependency of device parameters, and develop better scaling RF model at high frequency, the extraction from

presented under various bias co

RF MOSFETs are covered in this work. In this study, four-port S parameter measurement is supported by Radio Frequency Technology Center of National Nano Device Laboratory (NDL RFIC). The device geometries of two-port 3T and four-port 4T MOSFETs are listed in Table. 2.1 and Table 2.2, respectively.

0.13 4 6,18,36,72

L(um) W(um) NF

0.18 4 6,18,36,72

0.35 4 6,18,36,72

Dummy Pad

open short

0.5 4 6,18,36,72

Table 2.2 The device geometries of four-port MOSFETs

L W NF

0.13 4 6 open NF=6 short NF=6

0.13 4 18 open NF=18

Dummy Pad

short NF=3

0.13 4 36 open NF=36 6

Fig. 2.1 Quasi-static model assumption

Fig. 2.2 Input signals and the channel charge response

Fig. 2.3 Quasi-Static and Non-Quasi-Static models for SPICE analysis

Chapter 3

Two-port 3T RF MOSFET Model Parameter Extraction

3.1 De-embedding methods and verification

The test structures of the RF MOSFET includes the actual device under test (DUT) and parasitic components form the metal interconnections to the pad structures, in order to model the behavior of the DUT accurately and extracting MOSFET parameters from measured data, to build de-embedding method is necessary for the purpose, and the de-embedding method in the thesis will use “open” and “short”

de-embedding method.

3.1.1 Open de-embeddi

st structures is the full structure take off the layer under metal1(M1), and the open

a. Measure the S p

;

3

(3.2)

c. Subtract the Y parameter of the open pad from the Y parameters of DUT.

(3.3)

ng

The dummy open pad is designed to clear the parallel coupling capacitances, the te

de-embedding step can be describe as follows.

arameters of the DUT and transform it into Y parameters.

mea mea

S → Y

(3.1) b. Measure the S parameters of the dummy open pad and transform them into Y parameters.

open open

1 3 3

C C C

op

Y +Y −Y

⎡ ⎤

S →Y

3 2

en

C C C

Y = ⎢⎣ −Y Y +Y ⎥⎦

_

mea o mea open

Y →Y −Y

Fig. 3.1 and Fig. 3.2 represent the equivalent circuit of 3T device with pad and

dummy open pad respectively, the open pad equivalent circuit is composed of capacitance mainly, in Fig. 3.1, YC1 and YC2 are coupling parameters between pads

. ZRL1 ~ ZRL3 p

rameters of device, and the parameters can be used to calculate the s in equivalent circuit model.

T mbed

pa

ad structures uses the layout of open p and reference ground, YC3 is the coupling parameter between two signal pads

arameters a

a

value of the component

he open de-e rallel with the DUT

re related to the metal line layout in each terminal of device, and the parameters will be discussed later in section 3.1.2. So far, we can get the first de-embed Y p

3.1.2 Short de-embedding

ding method can de-embed the parasitic components in , but there are still the parasitic components in series with the DUT. Thus, the dummy short pad is designed to clear the series parasitical

parameters, the dummy short p ad and

connected all terminals together in metal3, the short de-embedding step can be describe as follows.

a. Measure the S parameters of the Short pad and to execute open de-embedding.

short

short Y

S → ; Y_short −Y_open =Y_{short_o} (3.4) b. Convert Ymea_o and Yshort_o parameters into Z parameters.

;

(3.5)

(3.7)

o mea o

mea_{_}

→ Z

_{_}

Y Y

_{short_o}

→ Z

_{short_o}

⎥⎤

= ⎢

Z^short_o ⎣ Z_RL3 Z_RL2 +Z_RL3⎦

c. Subtract the Z parameter of the Zshort_o from the Z parameters of Zmea_o.

o short o

mea

dut

Z Z

Z =

_{_}

−

_{_} (3.6)

dut dut

⎡Z_RL1+Z_RL3 Z_RL3

Y

Z →

Remember that all test structure have the parasitic capacitances between the g first in order to substrate the coupling param

arameters ZRL1~ZRL3

originate from metal interconnections between the terminal of DUT and the pad. The intrinsic Z parameters of the DUT can be obtained through conventional open and short de-embedding discussed above, the

parameters or S parameters for the need. Fig. 3.4 is a good illustration of showing

3.2 Parasitic re

g can be represented s Fig. 3.5. According to the layout, the metal line connects form metal3(M3) to

ance GSG pad and ground, so that, all test structure need to do the open de-embeddin

eters. The equivalent circuit of short pad is shown In Fig. 3.3, we support that there are only parasitic p

final Z matrix also can be converted to Y

de-embedding procedures discussed in preceding paragraphs.

sistance and inductance extraction and analysis

The two-port 3T RF MOSFET is implemented with common source configuration that source and body terminals are tied together in metal3 and grounding, and the terminals of DUT connect to GSG pad by metal line. In our experience, the parasitic resistance contributed from the metal line will affect the I-V characteristic of DUT. For the purpose, we will extract the parasitic RL parameters from short pad and extract RL parameters from device directly in this session.

3.2.1 Parasitic RL extraction from short pad

The equivalent circuit of short pad after open de-embeddin a

metal8(M8), we assume that it is composed of parasitic resistance and induct only form metal interconnections between the DUT and the pad, and the parameters with subscript “ext” to represent extrinsic RL parameters.

By analysis the Z parameters of the equivalent circuit of short pad after open

de-embedding, the Z parameters can be express as follow: addition, the parasitic resistance and inductance can be expressed by arrange the

The extracted R and R have the weak frequency dependence at low frequency, the behavior indicated that there are frequency term without considered at high frequency probably. Although it has the behavior, the p

ω

arasitic RL parameters are

Table 3.1 The extracted extrinsic resistance and inductance of short pad Extracted

extrinsic RL

Rg_ext extracted at low frequency.

AVG(2~5G) 0.355 0.589 0.228 57.05 57.72 15.11

3.2.2 Parasitic RL extraction from device

In chapter 3.2.1, we discuss the approximate parasitic resistance and inductance

When MOSFET operating in strong inversion region and Vds=0V, the equivalent

circuit the

from short pad, but this part of resistance and inductance come from metal connection between metal3 and metal8 only, in order to determine total terminal resistance come form metal1 to metal8, parasitic parameters are extracted from device after open de-embedding only directly.

of DUT after open de-embedding can be represented as Fig. 3.6. Refer to

pu our ory, p RL extraction method can be summarized as the following equation.

blishing in laborat arasitic

( )

ch

( )

^dut

3.2.3 Frequency and bias dependence of Parasitic RL

It has been known that gate resistance will influe

noise performance of RF MOSFET at high frequency, for the layout of multi-finger MOSFET, the gate/drain terminal is used p

resistance. The terminal parasitic RL represe inductanc nsists of both intrinsic and e

The effective lumped resistance and inductance can be considered to have a gate bias dependent and a bias independent component, remember that the terminal of DUT connect to the GSG pad by metal only, it means that the bias independent parasitic RL contributed from the extrinsic metal interconnection between M3 and M8, and the bias dependent RL will be contributed from the intrinsic MOSFET device.

nce the input impedance and

arallel structure to reduce the gate/drain nts the effective lumped resistance and

e that co xtrinsic part.

We have extract the parameters from devices with various channel length (L) and cy, and observe that R

-1

ance and the gate electrode resist

gate finger number (NF) at several bias conditions under the suitable frequen

D and RG are almost const in short channel device but sensitive to the gate bias at long channel device, the parasitic resistance decreases with gate bias increases. Thus, the optimizing RG andRD verse (Vgs -Vth) at different geometry is plotted in Fig. 3.7 and Fig. 3.8.

The effective gate resistance that consists of the distributed channel resist ance, the effective drain resistance that consists of the electrode resistance and the resistance contributed from the channel, the expression for gate/drain resistance model can be written as:

_ _

_

_

G g poly g ch

R

g bias g const

gs th

R R

R

= +

R V V

= +

−

(3.15)

_ _

_

D d poly d ch

d bias

^d_^const

gs th

R R R

R V V

= +

−

RG versus inverse of (Vgs -Vth) is plotted to obtain Rg_poly and Rg_ch, where Rg_poly

and Rg_ch represent the gate bias independent resistance and gate bias dependent resistance respectively, Rg_poly

= R +

(3.16)

can be determined from the linear regression of mea

uation in Fig. 3.8. It provides that electrode resistance is bias independent, but distributed channel resistance is bias independent again.

surement data intercept at (Vgs -Vth)^-1=0, in addition, Rg_bias is obtained from the slope of the liner regression equation in Fig. 3.7. Similarly, Rd_const can be determined from the linear regression of measurement data intercept at (Vgs -Vth)^-1=0, Rd_bias is obtained from the slope of the liner regression eq

3.2.4 Device geometry dependence

In this session, we will discuss the geometry d

further, the optimizing R t

1/L, and resistance of NQS effect is

The extracted R and R decrease with increasing finger number (NF) in

g_const, Rd_const, Rg_bias and Rd_bias

verse inverse of NF individually

G G

ependence of gate/drain resistance

G verse channel length at different Vgs is plotted in Fig. 3.9, i shows that RG decreases first as channel length increase while showing a weak bias dependence in the region, then to increase with channel length increase above 0.18um while showing a strong bias dependence. The channel length dependence of RG is strong on longer device and at lower Vgs.

The U-shape channel length dependence of RG in Fig. 3.9 can be explained with the consideration of the distributed effects in both distributed transmission line effect on the gate and NQS effect in the channel. It has been well known that the resistance of a poly-silicon resistor is proportional to

proportional to L.

g_const g_bias

the all devices, Fig. 3.10~3.13 show that extracted R

, the result support us that the linear regression of the resistances is a good reciprocal function of NF, and the behavior proved that the resistance originate from channel distributed effect obviously.

Using the method to separate the bias and geometry dependent and independent component from the R , the total parasitic resistance R can be written as below, where α, β almost is constant.

_ _

_ _

_

G g poly g ch

g poly g nqs

g bias

gs th

_

_

*

* * ( )

g const

g ext

R R R

R R

R R

V V R L

L NF NF V

_gs

V

_th

α β

= + +

−

= +

= +

= +

−

(3.17)

The calculated Rg_poly and Rg_ch verse channel length show in the Fig. 3.14 and Fig. 3.15. Rg_poly decrease with the channel length increasing, and Rg_ch increase with the channel length increasing. When channel is short enough, the contribution of Rg_ch

is smaller than Rg_poly,, Rg_poly is gate bias insensitively and dominate the total resis

-shape channel length dependence of the total gate terminal resistance.

3.3 Extraction of device parameters in linear region

In this section, we will discuss that parameters extraction of MOSFET operating in linear region. When gate voltage is smaller than the threshold voltage and at Vds=

ce extraction and analysis

Capacitances of RF MOSFET are extracted from the intrinsic Y parameters at low acitances extra

tance. As channel length increasing, the NQS effect is more significant, Rg_ch will dominate the RG, and RG has a strong gate bias dependence. So that, it provides that Rg_poly and Rg_ch cause the U

0V, the equivalent circuit of 3T device with parasitic RL parameters and substrate network components can be shown in Fig. 3.16. Cgs0 and Cgd0 represent the gate-to-source and gate-to-drain zero bias capacitances, respectively. Cgb is the total intrinsic and extrinsic gate-to-body capacitances. Cjs and Cjd are diffusion junction capacitances, Rsub represents the substrate resistance and Cdnw is junction capacitance between substrate and deep N-well.

3.3.1 Capacitan

frequency conventionally, short de-embedding is essential for accurate cap

ction in our experience. By performing Y parameter analysis on the circuit of intrinsic DUT in Fig. 3.17, the capacitance of equivalent circuit at low frequency can be express by

( ) ( )

gg

dut C

Y₁₁ =

ω

Im (3.18)

( )

gd

dut C

Y =ω

−Im ₁₂ (3.19)

( ) (

gd jd

)

dut C C

Y₂₂ =ω +

Im (3.20)

For Vgs>Vth,

C

_gg

= C

_gd

+ C

_{gs. For Vgs<Vth,}C_gg =C_gdo +C_gso +C_gb.

Note that the capacitances Cgs and Cgd are equal almost because the symmetry es includes both intrinsic and

pad in operating open de-embedding, and the capacitances decreases by a time constant decay with frequency

goodly dummy open/short pad. Thus, we still extract the capacitances of measured data at low frequency as the initial value of the circuit.

3.3 tance bias etry dependence

structure in this bias condition. The extracted gate capacitanc

extrinsic component of the MOSFET individually, it also can be separated the bias dependent or independent part by the gate voltage. The extracted capacitances appear non-smooth curve in the smaller finger number devices with the frequency, because that small device has the small capacitances compared to the capacitances of the open

increasing, the issue can be solved by the

.2 Capaci and geom

The gate-bias dependences of the optimizing capacitances are shown in Fig.

3.18, the intrinsic capacitance is normally bias dependent while the overlap capacitance is bias independent. when gate voltage small than the threshold voltage, To observe the transcapacitances conservation, the gate capacitances cab be rewrite as the equation Cgg=Cgd0+Cgs0+Cgb, As the gate voltage increases, the channel

3.18, the intrinsic capacitance is normally bias dependent while the overlap capacitance is bias independent. when gate voltage small than the threshold voltage, To observe the transcapacitances conservation, the gate capacitances cab be rewrite as the equation Cgg=Cgd0+Cgs0+Cgb, As the gate voltage increases, the channel

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