Extraction of device parameters in linear region

In this section, we will discuss that parameters extraction of MOSFET operating in linear region. When gate voltage is smaller than the threshold voltage and at Vds=

ce extraction and analysis

Capacitances of RF MOSFET are extracted from the intrinsic Y parameters at low acitances extra

tance. As channel length increasing, the NQS effect is more significant, Rg_ch will dominate the RG, and RG has a strong gate bias dependence. So that, it provides that Rg_poly and Rg_ch cause the U

0V, the equivalent circuit of 3T device with parasitic RL parameters and substrate network components can be shown in Fig. 3.16. Cgs0 and Cgd0 represent the gate-to-source and gate-to-drain zero bias capacitances, respectively. Cgb is the total intrinsic and extrinsic gate-to-body capacitances. Cjs and Cjd are diffusion junction capacitances, Rsub represents the substrate resistance and Cdnw is junction capacitance between substrate and deep N-well.

3.3.1 Capacitan

frequency conventionally, short de-embedding is essential for accurate cap

ction in our experience. By performing Y parameter analysis on the circuit of intrinsic DUT in Fig. 3.17, the capacitance of equivalent circuit at low frequency can be express by

( ) ( )

gg

dut C

Y₁₁ =

ω

Im (3.18)

( )

gd

dut C

Y =ω

−Im ₁₂ (3.19)

( ) (

gd jd

)

dut C C

Y₂₂ =ω +

Im (3.20)

For Vgs>Vth,

C

_gg

= C

_gd

+ C

_{gs. For Vgs<Vth,}C_gg =C_gdo +C_gso +C_gb.

Note that the capacitances Cgs and Cgd are equal almost because the symmetry es includes both intrinsic and

pad in operating open de-embedding, and the capacitances decreases by a time constant decay with frequency

goodly dummy open/short pad. Thus, we still extract the capacitances of measured data at low frequency as the initial value of the circuit.

3.3 tance bias etry dependence

structure in this bias condition. The extracted gate capacitanc

extrinsic component of the MOSFET individually, it also can be separated the bias dependent or independent part by the gate voltage. The extracted capacitances appear non-smooth curve in the smaller finger number devices with the frequency, because that small device has the small capacitances compared to the capacitances of the open

increasing, the issue can be solved by the

.2 Capaci and geom

The gate-bias dependences of the optimizing capacitances are shown in Fig.

3.18, the intrinsic capacitance is normally bias dependent while the overlap capacitance is bias independent. when gate voltage small than the threshold voltage, To observe the transcapacitances conservation, the gate capacitances cab be rewrite as the equation Cgg=Cgd0+Cgs0+Cgb, As the gate voltage increases, the channel charges build up to increase the intrinsic component of the extracted capacitances, when the channel charge can be supplied by source/drain to channel rather than body in the strong inversion region, the whole Cgb capacitance which through the active

channel area to source/drain region is very small and can be neglected, the gate capacitances can describe as Cgg=Cgd+Cgs.

In the simplified C-V model, the gate capacitance can be described as equation ce geometry dependenc

(3.21). under a given gate voltage, we will discuss the capacitan

e, Fig. 3.19 and Fig. 3.20 show that the gate capacitances are well proportioned to the NF and channel length, the intercept of Y-axis is much closed to zero, and it verifies that the proposed extraction method is accurate and reliable.

* (

^gs

)

g active active ox

Q = W L C V V

(3.21)

3.3.3 Channel resistance extraction and analysis

When MOSFET operates at strong inversion region and Vds=0V, the extracted channel resistance Rch discussed above in question (3.10), Rch is considered as a intrinsic parameter originate form the inversion layer channel charge, the bias, NF, and channel length dependent are plotted in Fig. 3.21~Fig. 3.23, individually.

As the Vgs increasing, the channel charge can be supplied by source/drain to channel is increasing, the depths

finger number but is propositional to channel length.

nsic resistance from the device only.

FET is of inversion layer is increasing similarly, the behavior will cause the Rch decrease as vgs increase, Rch also decrease as NF increase base on the multi-finger gate/drain structure, but the total Rch is sum of the distributed channel resistance at the source/drain direction, Rch will increase with the longer channel length. So that, channel resistance is inverse proportion to gate voltage and

Rch is well propositional to geometry provided that the channel resistance is dominated by the intri

3.3.4 Substrate resistance extraction and analysis

One of the most important features to be considered when the MOS

oper

T in Fig. 3.17, the parameters of equivalent circuit at low frequency can be express by:

ated at high frequencies is the impact of the substrate network on the output impedance. This substrate network consists of the junction capacitances and the substrate loss resistances, the drain junction capacitance and the bulk spreading resistance are represented by Cjd and Rsub, respectively.

As the operation frequency increases, the impedance of the junction capacitance reduces. The signal coupling through the substrate resistances from the drain to the source and from the drain/source to the substrate contact has to be carefully considered for the output admittance. By performing Y parameter analysis on the circuit of intrinsic DU

(

^{22 12}

)

Im

^{dut dut}

C

jd

= Y + Y ω

(3.22)

( )

^{22 2 2}

Re

^dut

sub jd

R = Y ω C

(3.23) We will extract the substrate parameters using (3.23) as the initial value, In order to achieve the best fit for the simulated and measured S-parameter data, optimization of all the RF component values must be done. The optimizing Cjd and Rbulk geometry dependence are plotted in Fig. 3.24 and Fig. 3.25.

在文檔中 射頻金氧半電晶體小訊號等效電路模型參數萃取方法建立以應用於各種偏壓與幾何結構 (頁 32-35)