Chapter 3 Two-port 3T RF MOSFET Model Parameter Extraction
3.4 Extraction of intrinsic parameters in saturation region
y channel structure and current gain. The parameters gm and gds represent the transconductance and the output conductance of the transistor respectively, and uniform channel resistance replace by Rch , Rds and Cds parameters to express the asymmetry inversion
When MOSFET operating in saturation region, the equivalent circuit of DUT after open de-embedding can be represented as Fig. 3.26, the difference between linear region and saturation region is the asymmetr
layer.
Refer to the thesis in our laboratory, and the extraction method of element can be
summarized as the following equation,
d m
gs
g I
V
= ∂
∂
;d ds ds
g I
V
= ∂
∂
(3.24)1
ch ds
g
ds= R + R
;R C
ch gs= R C
ds gd (3.25)1.2 0, 1.2
gs ds gs ds
jd V V V jd V V V
C C
= =
=
= = (3.26)3.4.1 Capacitance extraction and analysis
Extraction of capacitance at Vds=0V (3.18~3.20) to be suitable for use at this condition, the gate bias dependences of extracted capacitances are shown in Fig.
3.27 and Fig. 3.28, Cgs and Cgd are composed of the intrinsic and overlap components, the intrinsic capacitance is normally bias dependent while the overlap capa
acitances.
Cgs has strong gate bias dependence in Fig. 3.27, Cg
bias increases near subthreshold region, and is saturation gradually in the strong inversion saturation region. Cgd only increases slightly with g
under saturation conditions, intrinsic capacitances of Cgd are very small because that drain voltage will deplete the drain side capacitance, an
citance is bias independent. As Vgs increases, the channel charges build up and increase the intrinsic component of the extracted cap
s increases strong as gate
ate bias in Fig. 3.28,
d the total gate-to-drain capacitance is dominated by the overlap capacitance.
From Fig. 3.27, it is observed that as Vds increases, there is a small increase in Cgs., this is because the transistor is approaching the saturation region and the channel is pinched-off when Vds=Vgs-Vth. The channel charge in the source side increases and the intrinsic capacitance of Cgs also increases. For Cgd, when the channel is approaching the pinch-off condition, the charge in the intrinsic drain region decreases and this decreases the intrinsic capacitance of Cgd.
The capacitance geometry dependence are plotted in Fig.3.29 ~ Fig. 3.32, the gate capacitances are well proportioned to the NF and channel length as the description in section 3.3.2.
Fig. 3.1 The equivalent circuit of 3T device with pad
Fig. 3.2 The equivalent circuit of open pad
Fig. 3.3 The equivalent circuit of short pad
Fig. 3.4 The illustration of de-embedding procedure for 3T device
Rg,ext Lg,ext Ld,ext Rd,ext
Rs,ext
Ls,ext
Port1 Port2
Fig. 3.5 The equivalent circuit of short pad after open de-embedding
Fig. 3.6 The equivalent circuit of 3T device at Vgs>>Vth, Vds=0V (Open_de)
0 2 4 6 8 10 12 14
2 4 6 8 10 12 14
Y =1.98+0 X
Y =2.74222+0.00159 X Y =4.89+0 X
12.71+0 X L=0.13um, Vds=0 Y =
NF=6 NF=18 NF=36 NF=72
R G
1/Vg-Vth
0 2 4 6 8 10 12 14
2 4 6 8 10 12 14
Y =1.93561+0.00755 X Y =2.37548+0.0173 X Y =3.95065+0.07304 X Y =10.0322+0.23748 X
0 L=0.18um, Vds=
NF=6 NF=18 NF=36
NF=72 R G
1/Vg-Vth
0 2 4 6 8 10 12 14
5 10 15 20
Y =1.29187+0.08814 X Y =1.93053+0.1933 X Y =2.56023+0.39036 X Y =7.59692+0.91755 X
L=0.35um, Vds=0 NF=6 NF=18 NF=36 NF=72
R G
1/Vg-Vth
0 2 4 6 8 10 12 14
2 4 6 8 10 12 14 16 18 20 22 24 L=0.5um, Vds=0
Y =1.28039+0.17593 X Y =1.38584+0.34572 X Y =2.74468+0.71231 X Y =6.65665+1.18009 X
NF=6 NF=18 NF=36 NF=72
R G
1/Vg-Vth
Fig. 3.7 linear regression of optimized RG versus (Vgs -Vth)-1 at Vds=0V
0 2 4 6 8 10 12 14
Y =0.64563+0.00622 X Y =0.8002+0.00216 X Y =1.07174+0.00599 X
Y =1.942+5.62066E-4 X L=0.13um, Vds=0 NF=6
Y =0.4824+0.00754 X Y =0.63818+0.00846 X Y =0.9714+0.01107 X Y =2.10659+0.01477 X
L=0.18um, Vds=0 NF=6
Y =0.71329+0.03433 X Y =0.88487+0.06399 X Y =1.89061+0.04848 X Y =5.99764+0.94104 X
L=0.35um, Vds=0 NF=6
Y =0.32146+0.22044 X Y =0.7015+0.23557 X Y =2.04675+0.24657 X Y =6.53914+1.09505 X
L=0.5um, Vds=0 NF=6
Fig. 3.8 linear regression of optimized RD versus (Vgs -Vth)-1 at Vds=0V
0.1 0.2 0.3 0.4 0.5
NF=6, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V
L (um)
NF=18, Vds=0V Vg=0.4V
NF=36, Vds=0V Vg=0.4V
NF=72, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V
L (um)
Fig. 3.9 The gate resistance optimized RG versus channel length at Vds=0V
0.000 0.03 0.06 0.09 0.12 0.15 0.18
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0
2 4 6 8
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0 Y =0.90912+70.80926 X
L=0.13um, Vds=0V
Rg_poly
1/NF
Y =1.01627+53.91991 X L=0.18um, Vds=0V
Rg_poly
1/NF
Y =0.61219+41.42194 X L=0.35um, Vds=0V
Rg_poly
1/NF
Y =0.49853+37.16637 X L=0.5um, Vds=0V
Rg_poly
1/NF
Fig. 3.10 linear regression of Rg_poly versus reciprocal of NFat Vds=0V
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.6
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.5
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0 Y =0.56494+8.33579 X
L=0.13um, Vds=0V
Rd_poly
1/NF
Y =0.35191+10.57629 X L=0.18um, Vds=0V
Rd_poly
1/NF
Y =0.02319+35.59681 X L=0.35um, Vds=0V
Rd_poly
1/NF
Y =-0.31365+41.16676 X L=0.5um, Vds=0V
Rd_poly
1/NF
Fig. 3.11 linear regression of Rd_poly versus reciprocal of NFat Vds=0V
-0.03 0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.21
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.00
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.0 Y =6.75351E-4-0.00421 X
L=0.13um, Vds=0V
Rg_bias
1/NF 1/NF
Y =-0.01726+1.53253 X L=0.18um, Vds=0V
Rg_bias
Y =0.04801+5.29512 X L=0.35um, Vds=0V
Rg_bias
1/NF 1/NF
Y =0.19613+6.1751 X L=0.5um, Vds=0V
Rg_bias
Fig. 3.12 linear regression of Rg_bias versus reciprocal of NFat Vds=0V
0.00 0.03 0.06 0.09 0.12 0.15 0.18 -0.10
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.007
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.0
0.00 0.03 0.06 0.09 0.12 0.15 0.18 0.2 Y =6.75351E-4-0.00421 X
L=0.13um, Vds=0V
Rd_bias
1/NF
Y =-0.01726+1.53253 X L=0.18um, Vds=0V
Rd_bias
1/NF
Y =0.04801+5.29512 X L=0.35um, Vds=0V
Rd_bias
1/NF
Y =0.19613+6.1751 X L=0.5um, Vds=0V
Rd_bias
1/NF
Fig. 3.13 linear regression of Rd_bias versus reciprocal of NFat Vds=0V
2 3 4 5 6 7 8 NF=6, Vds=0V
Rg_poly
1/L
NF=18, Vds=0V
Rg_poly
1/L NF=36, Vds=0V
Rg_poly
1/L
NF=72, Vds=0V
Rg_poly
1/L
Fig. 3.14 channel length dependence of Rg_polyat Vds=0V
0.1 0.2 0.3 0.4 0.5 NF=36, Vds=0V
Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V NF=6, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V
NF=18, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V
NF=72, Vds=0V Vg=0.4V
Fig. 3.15 channel length dependence of Rg_chat Vds=0V
Fig. 3.16 The equivalent circuit of 3T device at Vgs=Vds=0V (Open_de)
Fig. 3.17 The equivalent circuit of 3T device at Vgs=Vds=0V (Open+Short_de)
0.4 0.6 0.8 1
220 L=0.13um, Vds=0
NF=6 L=0.18um, Vds=0 300
NF=6
L=0.35um, Vds=0 NF=6 L=0.5um, Vds=0
NF=6
Fig. 3.18 The bias dependence of optimized Cgd at Vds=0V
)gd (fF L=0.13um, Vds=0V
Vg=0.4V
L=0.18um, Vds=0V Vg=0.4V
L=0.35um, Vds=0V Vg=0.4V
L=0.5um, Vds=0V Vg=0.4V
Fig. 3.19 The NF dependence of optimized Cgd at Vds=0V
0.1 0.2 0.3 0.4 0.5
NF=6, Vds=0V
200
NF=18, Vds=0V Vg=0.4V
NF=36, Vds=0V
L
Cgd (fF)
NF=72, Vds=0V Vg=0.4V
Fig. 3.20 The channel length dependence of optimized Cgd at Vds=0V
0 2 4 6 8 10 12 14
NF=6, Vds=0 L=0.13um NF=18, Vds=0 140
L=0.13um
70 NF=36, Vds=0 L=0.13um NF=72, Vds=0
L=0.13um
Fig. 3.21 The bias dependence of optimized Rch at Vds=0V
0.000 0.03 0.06 0.09 0.12 0.15 0.18 L=0.13um, Vds=0V
Vg=0.4V
L=0.18um, Vds=0V Vg=0.4V L=0.35um, Vds=0V
Vg=0.4V
L=0.5um, Vds=0V Vg=0.4V
Fig. 3.22 The NF dependence of optimized Rch at Vds=0V
0.1 0.2 0.3 0.4 0.5
NF=6, Vds=0V Vg=0.4V
NF=18, Vds=0V Vg=0.4V
NF=36, Vds=0V Vg=0.4V
NF=72, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V
L (um)
Fig. 3.23 The L dependence of optimized Rch at Vds=0V
0 10 20 30 40 50 60 70 80 L=0.13um, Vds=0V
Vg=0.4V
L=0.18um, Vds=0V Vg=0.4V L=0.35um, Vds=0V
Vg=0.4V
L=0.5um, Vds=0V Vg=0.4V
Fig. 3.24 The NF dependence of optimized Cjd at Vds=0V
0.00 0.03 0.06 0.09 0.12 0.15 0.18 20
0.00 0.03 0.06 0.09 0.12 0.15 0.18 40 L=0.13um, Vds=0V
Vg=0.4V
L=0.18um, Vds=0V Vg=0.4V L=0.35um, Vds=0V
Vg=0.4V
L=0.5um, Vds=0V Vg=0.4V
Fig. 3.25The NF dependence of optimized Rbulk at Vds=0V
Fig. 3.26 The equivalent circuit of 3T device at Vgs=Vds=1V (Open_de)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 50
100 150 200 250
L=0.13um
NF= 6 Vds=0 Vds=1V NF=18 Vds=0 Vds=1V NF=36 Vds=0 Vds=1V NF=72 Vds=0 Vds=1V
Cgs (fF)
Vg (V)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 50 100 150 200 250 300 350
L=0.18um
Cgs (fF)
Vg (V)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 100
200 300 400 500 600 700 800
L=0.35um
Cgs (fF)
Vg (V)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 200 400 600 800 1000 1200 L=0.5um
Cgs (fF)
Vg (V)
Fig. 3.27 Bias dependence of optimized Cgs at Vds=1V
0.4 0.5 0.6 0.7 0.8 0.9 1.0
L=0.13um, Vds=1V NF=6 L=0.18um, Vds=1V
NF=6
L=0.35um, Vds=1V NF=6 L=0.5um, Vds=1V
NF=6
Fig. 3.28 Bias dependence of optimized Cgd at Vds=1V
0 10 20 30 40 50 60 70 80 L=0.13um, Vds=1V
Vg=0.4V
L=0.18um, Vds=1V Vg=0.4V L=0.35um, Vds=1V
Vg=0.4V
L=0.5um, Vds=1V Vg=0.4V
Fig. 3.29 NF dependence of optimized Cgs at Vds=1V
0 10 20 30 40 50 60 70 80 L=0.13um, Vds=1V
Vg=0.4V
L=0.18um, Vds=1V Vg=0.4V L=0.35um, Vds=1V
Vg=0.4V
L=0.5um, Vds=1V Vg=0.4V
Fig. 3.30 NF dependence of optimized Cgd at Vds=1V
0.1 0.2 0.3 0.4 0.5 Vg=0.8V, Vds=1V
NF=6 NF=18 NF=36 NF=72 Vg=0.4V, Vds=1V
NF=6 NF=18 NF=36 NF=72
Vg=0.6V, Vds=1V NF=6 NF=18 NF=36 NF=72
Vg=1.0V, Vds=1V NF=6
Fig. 3.31 L dependence of optimized Cgs at Vds=1V
0.1 0.2 0.3 0.4 0.5 20
40 60 80 100 120 140
Cgd (fF)
L (um)
Vg=0.8V, Vds=1V NF=6 NF=18 NF=36 NF=72
Vg=0.4V, Vds=1V NF=6 NF=18 NF=36 NF=72
Vg=1.0V, Vds=1V NF=6 NF=18 NF=36 NF=72
0.1 0.2 0.3 0.4 0.5
20 40 60 80 100 120 140 Vg=0.6V, Vds=1V
NF=6 NF=18 NF=36 NF=72
Cgd (fF)
L (um)
0.1 0.2 0.3 0.4 0.5
20 40 60 80 100 120 140 160
Cgd (fF)
L (um)
0.1 0.2 0.3 0.4 0.5
20 40 60 80 100 120 140 160 180 200
Cgd (fF)
L (um)
Fig. 3.32 L dependence of extracted Cgd at Vds=1V
Chapter 4
Four-port RF MOSFET Model Parameter Extraction
4.1 De-embedding methods
MOSFETs are designed as common source amplifiers in most RF circuit application, and are implemented by the traditional two-port 3T MOSFET CS configuration that source and body terminals are tied together in metal3 and grounding. In fact, source and body terminals are not always connected together in the application of RFIC design, there are some MOSFETs are designed to operate with the body bias, such as a conventional cascade LNA with source degeneration inductor, the body terminal is always connected to ground, but source terminal is not.
To implement the MOSFET with separate source and body terminals for
measurement, s the GSG pad,
therefore, four terminal of MOSFET can supply the voltage individually for the needs.
In this study, the deep N-well (DNW) also connect to ground as the clean-cut reference point to avoid the unanalyzable Z parameter in the four-port devices, and the supplied body bias should be small than the turn on voltage of the junction between the substrate and DNW. One thing is mentioned that test key layout design must conform to the rule of four-port network measurement mechanism, and then the area of the four-port devices will be larger than two-port conventional devices, the full test structure and cross section of four-port devices are plot in Fig. 4.1.
ource and body terminals will connect to signal pad of
4.1.1 Open
The two port conventional open and short de-embedding method are introduced in session 3.1, basing on the concept of two port de-embedding method, we suppose that the de-embedding method can be apply to the four-port devices, so that, the unique four-port dummy open and short pad will be developed for the purpose. For the open pad, the test structure is the full device structure take off the layer under metal1 (M1), and DNW connecting to ground, the simple 3D illustration is shown in the Fig.
4.2. For the short pad, all signal terminals are connected together in metal3 on the open pad structure, then through the M1 to the ground, remember that M1 grounding is a necessity for the short pad, or it will be as the through pad. However, the simple 3D illustration is shown in the Fig. 4.3.
In this study, the de-embedding method of two-port devices will extend to the four-port networks. According to the conventional de-embedding method of two-port devices, the step can be summar
(4.1)
and Short de-embedding method
ized as:
short short
open open
mea
mea
Y S Y S Y
S → , → , →
o short o
mea dut
o short o
short o
mea o
mea
open mea
o mea
Z
Z Y
Z Y
Y Y
Y
Y Y
Y
_ _
_ _
_ _
_
,
−
=
open short
o short _
→
→
−
=
Z
Z −
=
Following the above de-embedding step, the intrinsic device Z parameters can be obtained, final Z matrix also can be converted to Y parameters or S parameters for the needs, the parameters in equation (4.1) are all the 4x4 matrix, and the matrix conversion between of S, Y and Z parameters is discussed in session 2.
4.2 Parasitic RL extraction from short pad
The two-port parasitic RL parameters extraction method is discussed in session 3.2. For four-port devices, the equivalent circuit of short pad after open de-embedding can be represented as Fig. 4.4. Similarly, we support that there are only parasitic RL parameters originate from metal interconnections between the terminal of DUT and the pad, by analysis the Z parameters of the equivalent circuit of short pad after open de-embedding, the parameters extraction for four-port devices can be described as
( )
arameters extraction of four-port devices operating in linear region. For four-port devic
uation (4.2), the subscript value represents the port number for the measurement respectively. In this study, port1, 2, 3, and 4 represent that gate, source, drain, and body respectively. The result shows that the extracted parasitic RL is not the frequency independent parameters, it may be has a high frequency term without considered in the equivalent circuit, and common part of the resistance is smaller than the resistances come from metal connection between metal3 and metal8, the parasitic RL parameters are extracted at low frequency.
4.3 Extraction and analysis of parameters in linear region
In this section, we will discuss that p
es, when gate voltage is smaller than the threshold voltage and Vds=0V, the equivalent circuit of four-port devices with parasitic
RL parameters and substrate network components can be shown in Fig. 4.5. The differentiation between two-port and four-port devices is the substrate networks that connection of the body and DNW terminal is not tied together in four-port devices.
4.3.1 Extraction of parameters in linear region
The capacitances of the equivalent circuit are extracted from the intrinsic Y parameters at low frequency conventionally, the circuit is very simple, we assume that
extraction quation.
For the four-port MOSFET, Ward-Dutton description leads to a total of 16 ed as follows in a 4x4 matrix
(4.3)
terminal current does not contain any conductive current component. The elements in each column and low must sum to zero owing to the constraints imposed by charge conservation. As gate capacitances for example, the gate capacitances relationship cab be represented as
the components between gate and the other terminals can be considered as purely capacitances, the terminals resistance is finite in the frequency of our consideration, and it will be smaller than the impedance of the captaincies, according to the assumption, Rs and Rd can be neglected at low frequency to simplified the
e
transcapacitances. This set of 16 elements can be organiz .
⎥
⎥ ⎥
⎤
⎢
⎢ ⎢
⎡
=
bb bd
bs bg
db dd
ds dg
sb sd
ss sg
gb gd
gs
gg
C C C
C C
In this bias condition, there is not current flow through the devices, so that
⎥
⎥
⎢ ⎦
⎢
⎣ C C C C
C C
C C
C C
C C
gb gd
gs
gg
C C C
C = + +
(4.4) performing the Y parameter analysis of the equivalent circuit, the Y11 Bycomponent cab be derived as
bulk gb
R C j C
Following the Y parameter analysis, the components of Yxy(x=1~4, y=1~4) also can be derived, under the assumption
ω
2Rbulk2 Cgb2 <<1, the capacitances extraction equation can be simplified as bellow:( ) ( ) / ω Im ( ) / ω
The proposed de-embedding method is simpler than that of two-port 4T devices, and the capacitances can be extracted form the intrinsic Y matrix at low frequency directly, especially source junction capacitance, it is hardly to extract Cjs in a
ected together.
, the equivalent circuit is plotted in Fig. 4.6, extraction of capacitance at Vg=0V (4.6) to be suitable for use at this c
traditional two-port 3T CS MOSFET because source and body conn
The substrate resistance extraction tends to use the method discussed in the two-port CS configuration devices, the 2x2 matrix will be obtained by using the port reduction method that discussed in session 2.2.3, the remaining parameters Rs_diff, Rd_diff, and Cdnw also can be extraction by the reduced 2x2 Y matrix that bias at Vg=Vd=Vs=Vb=0V in other words.
Similarly, when MOSFETs operate at the strong inversion region and at Vd=Vs=Vb=0V
ondition, and the channel resistance will be extracted in the 2x2 matrix that reduce from the 4x4 matrix.
4.3.2 Analysis of parameters in linear region
The extracted capacitances are plotted as a function frequency in Fig.4.7 and Fig.
4.8, the extracted capacitances Cgg, Cgs and Cgs have weak frequency dependence at low frequency, and will be increase with the frequency increasing, there are some inductances without de-embedding completely to cause the behavior at high frequency
e of the existence of Rblk in equivalent circuit.
capacitances are well proportioned to the NF. As gate voltage increases, the channel charges build up to increase the intrinsic component of the extracted capacitances and Cgs is larger than the Cgd at Vgs=1.2V
there
.
rain to channel rather than body in the strong inversion region, the whole Cgb capacitance which through the active channel area to source/drain region is very small and can be neglected, the value of the Cgb is close to zero at Vg=1.2V. The extracted junction capacitances also show that the value of Cjs is larger than that of Cjd, becaus
junction than the drain and gate bias independent almost.
The geometry dependence of the optimizing resistances is shown in Fig. 4.11, it is known that R
. Conversely, the extracted capacitances Cgb, Cjs, and Cjd will be decease as the frequency increase, Cgb is extracted from the imaginary part of the intrinsic Y parameters in equation (4.6), and there is a frequency component in the denominator with the RC component, In other words, the capacitances Cgb, Cjs, and Cjd will be decrease as frequency increasing becaus
The geometry dependence of the optimizing capacitances are shown in Fig. 4.9 and Fig. 4.10, it shows that the
, because are one source junction than the drain, the extrinsic capacitances with gate bias dependency of source is more than drain
When the channel charge can be supplied by source/d
e there is one source
g_poly is gate bias insensitively and dominate the total resistance in
shorter devices, it also show that RG is well proportional to reciprocal function of NF.
4.4 Extraction and analysis of parameters in saturation region
h parasitic RL parameters and substrate network component
=0V is discussed chapter cuit, the capacitance extraction equation at
When MOSFET operates at saturation region and Vs=Vb=0V, the equivalent circuit can be extend to four-port devices base on ones of the two-port 3T devices, the equivalent circuit of four-port devices wit
s can be shown in Fig.4.12.
4.4.1 Extraction of parameters in saturation region
The capacitance extraction for four-port devices at Vds 4.3, by performing the Y parameter analysis of the equivalent cir
Vds=1.2V also can be written as:
( ) ( )
Note that the Yij is not equal to Yji in equation (4.7) because of the existent of current gain and asymmetry in channel.
V V
∂ ∂
4.4.2 Analysis of parameters in saturation region
The extracted capacitances are plotted as a function frequency in Fig.4.13 and
Fig. 4.14, the extracted capacitances Cgg, Cgs and Cgs is weak frequency dependet at low frequency, and will be increase with the frequency increasing. There are some inductances without de-embedding completely to cause the behavior at high frequency. Conversely, the extracted capacitances Cgb, Cjs, and Cjd will be decease as t
t nction capacitances in four-port devices, and the extracted result shows that the Cjd
junction with the reverse bias operation, and Cjs is a gate bias independent he frequency increase, and the extracted Cjs, and Cjd is almost gate bias independence.
The geometry dependence of the optimizing capacitances are shown in Fig. 4.15 and Fig. 4.16, it shows that the capacitances are well proportioned to the NF, and the gate capacitances relationship between of linear and saturation region is described in two-port devices.
For the junction capacitances, according to the equivalent circuit of two-port devices, Im(Y22) combine with Cjd, Cgd, Cds, and Cdnw, so it is hardly to extract the Cjd in two-port devices that operate at saturation region. Contrary, it is easy to extrac ju
capacitances at Vds=1.2V is smaller than one at Vds=0V, because that the drain-body
parameters.
Fig. 4.1 The cross section and structure of four-port MOSFETs
Fig. 4.2 Four-port dummy open structure (M1)
Fig. 4.3 Four-port dummy short structure (M3)
Fig. 4.4 The equivalent circuit of four-port short pad after open de-embedding
Open De-embedding Only RG
LG
RD_diff
LD
RS
LS
G
D
B S
Cgso
Cgdo
Cjd
Cjs
Rbulk Cdnw
RS_diff
RD
Cgb
RB
LB
Fig. 4.5 The equivalent circuit of four-port devices at Vgs=Vds=0V
Fig. 4.6 The equivalent circuit of 4-port device at Vgs=1.2V, Vds=0V (Open_de)
160
0 10G 20G 30G 40G
60 80 100 120
140 Vg=0V
Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=0V
Cgg(fF)
Frequency(Hz)
0 10G 20G 30G 40G
30 40 50 60 70 80 90
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=0V
Cgs(fF)
Frequency(Hz)
0 10G 20G 30G 40G
30 40 50 60 70
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=0V
Cgd(fF)
Frequency(Hz)
Fig. 4.7 The extracted Cgg, Cgs , Cgd capacitance verse frequency at Vds=0V
0 10G 20G 30G 40G 0
2 4 6 8 10 12
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=0V
Cgb(fF)
Frequency(Hz)
0 10G 20G 30G 40G
0 20 40 60
80 Vg=0V
Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V 100
L=0.13um, NF=18 Vds=0V
Cjs(fF)
Frequency(Hz)
0 10G 20G 30G 40G
0 10 20 30 40 50 60
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=0V
Cjd(fF)
Frequency(Hz)
Fig. 4.8 The extracted Cgb, Cjs, Cjd capacitance verse frequency at Vds=0V
5 10 15 20 25 30 35 40 0
40 60 80 100 120 140
Vds=0
Cgs@Vgs=0V Cgd@Vgs=0V Cgb@Vgs=0V Cgs@Vgs=1V Cgd@Vgs=1V
20
Cgb@Vgs=1V
G a te capacitan ces ( fF)
NF
Fig. 4.9 The NF dependence of optimized gate capacitances at Vds=0V
5 10 15 20 25 30 35 40
20 40 60 80 100
120
Vds=0Cjs@Vgs=0V Cjd@Vgs=0V Cjs@Vgs=1V Cjd@Vgs=1V
Junction capacitances (fF)
NF
Fig. 4.10 The NF dependence of optimized junction capacitances at Vds=0V
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0 2
4 6 8 10 12 14 16 18
Vds=0
RG@Vgs=0V RG@Vgs=1.2V Rch@Vgs=1.2V
Resistan ces ( fF)
1/NF
Fig. 4.11 The NF dependence of optimized RG and Rch at Vds=0V
Fig.
4.12 The equivalent circuit of 4-port device at Vgs=Vds=1.2V (Open_de)
0 10G 20G 30G 40G 60
80 100 120 140
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=1.2V
Cgg(fF)
Frequency(Hz)
0 10G 20G 30G 40G
30 40 50 60 70 80 90 100
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V L=0.13um, NF=18
Vds=1.2V
Cgs(fF)
Frequency(Hz)
Vg=1.0V Vg=1.2V
0 10G 20G 30G 40G
25 30 35 40 45
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V L=0.13um, NF=18
Vds=1.2V
Cgd(fF)
Frequency(Hz)
Fig. 4.13 The extracted Cgg, Cgs,Cgd capacitance verse frequency at Vds=1.2V
0 10G 20G 30G 40G -2
0 2 4 6 8 10 12
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V
Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V