RF MOSFET design

⎣

⎦

⎣

⎦

⎣I Y Y V

matrix can be obtained by setting the corresponding supply voltage to zero.

2.3 RF MOSFET design

the measured S parameters are nditions and geometries, both two-port 3T and four-port 4T

Table 2.1 The device geometries of two-port 3T MOSFETs

age, and the remaine b-matrix will be the Y matrix

to 3-port or 2-port Y matrix.

For example, the common source(CS) configuration is source (port3) and body (port4) grounding, the CS 2-port Y matrix can be obtained by setting the Vs=Vb=0V in the 4-port measurement, in this case, the term of source and body in (2.10) is

Y matrix can be written as

⎥⎤

⎢⎡

⎥⎤

⎢⎡

⎥ =

⎢ ⎤

⎡

2 1 22 21

12 11 2

1 Y Y V

I

(2.11)

Similarly, the common gate and common drain Y

To understand the dependency of device parameters, and develop better scaling RF model at high frequency, the extraction from

presented under various bias co

RF MOSFETs are covered in this work. In this study, four-port S parameter measurement is supported by Radio Frequency Technology Center of National Nano Device Laboratory (NDL RFIC). The device geometries of two-port 3T and four-port 4T MOSFETs are listed in Table. 2.1 and Table 2.2, respectively.

0.13 4 6,18,36,72

L(um) W(um) NF

0.18 4 6,18,36,72

0.35 4 6,18,36,72

Dummy Pad

open short

0.5 4 6,18,36,72

Table 2.2 The device geometries of four-port MOSFETs

L W NF

0.13 4 6 open NF=6 short NF=6

0.13 4 18 open NF=18

Dummy Pad

short NF=3

0.13 4 36 open NF=36 6

Fig. 2.1 Quasi-static model assumption

Fig. 2.2 Input signals and the channel charge response

Fig. 2.3 Quasi-Static and Non-Quasi-Static models for SPICE analysis

Chapter 3

Two-port 3T RF MOSFET Model Parameter Extraction

3.1 De-embedding methods and verification

The test structures of the RF MOSFET includes the actual device under test (DUT) and parasitic components form the metal interconnections to the pad structures, in order to model the behavior of the DUT accurately and extracting MOSFET parameters from measured data, to build de-embedding method is necessary for the purpose, and the de-embedding method in the thesis will use “open” and “short”

de-embedding method.

3.1.1 Open de-embeddi

st structures is the full structure take off the layer under metal1(M1), and the open

a. Measure the S p

;

3

(3.2)

c. Subtract the Y parameter of the open pad from the Y parameters of DUT.

(3.3)

ng

The dummy open pad is designed to clear the parallel coupling capacitances, the te

de-embedding step can be describe as follows.

arameters of the DUT and transform it into Y parameters.

mea mea

S → Y

(3.1) b. Measure the S parameters of the dummy open pad and transform them into Y parameters.

open open

1 3 3

C C C

op

Y +Y −Y

⎡ ⎤

S →Y

3 2

en

C C C

Y = ⎢⎣ −Y Y +Y ⎥⎦

_

mea o mea open

Y →Y −Y

Fig. 3.1 and Fig. 3.2 represent the equivalent circuit of 3T device with pad and

dummy open pad respectively, the open pad equivalent circuit is composed of capacitance mainly, in Fig. 3.1, YC1 and YC2 are coupling parameters between pads

. ZRL1 ~ ZRL3 p

rameters of device, and the parameters can be used to calculate the s in equivalent circuit model.

T mbed

pa

ad structures uses the layout of open p and reference ground, YC3 is the coupling parameter between two signal pads

arameters a

a

value of the component

he open de-e rallel with the DUT

re related to the metal line layout in each terminal of device, and the parameters will be discussed later in section 3.1.2. So far, we can get the first de-embed Y p

3.1.2 Short de-embedding

ding method can de-embed the parasitic components in , but there are still the parasitic components in series with the DUT. Thus, the dummy short pad is designed to clear the series parasitical

parameters, the dummy short p ad and

connected all terminals together in metal3, the short de-embedding step can be describe as follows.

a. Measure the S parameters of the Short pad and to execute open de-embedding.

short

short Y

S → ; Y_short −Y_open =Y_{short_o} (3.4) b. Convert Ymea_o and Yshort_o parameters into Z parameters.

;

(3.5)

(3.7)

o mea o

mea_{_}

→ Z

_{_}

Y Y

_{short_o}

→ Z

_{short_o}

⎥⎤

= ⎢

Z^short_o ⎣ Z_RL3 Z_RL2 +Z_RL3⎦

c. Subtract the Z parameter of the Zshort_o from the Z parameters of Zmea_o.

o short o

mea

dut

Z Z

Z =

_{_}

−

_{_} (3.6)

dut dut

⎡Z_RL1+Z_RL3 Z_RL3

Y

Z →

Remember that all test structure have the parasitic capacitances between the g first in order to substrate the coupling param

arameters ZRL1~ZRL3

originate from metal interconnections between the terminal of DUT and the pad. The intrinsic Z parameters of the DUT can be obtained through conventional open and short de-embedding discussed above, the

parameters or S parameters for the need. Fig. 3.4 is a good illustration of showing

3.2 Parasitic re

g can be represented s Fig. 3.5. According to the layout, the metal line connects form metal3(M3) to

ance GSG pad and ground, so that, all test structure need to do the open de-embeddin

eters. The equivalent circuit of short pad is shown In Fig. 3.3, we support that there are only parasitic p

final Z matrix also can be converted to Y

de-embedding procedures discussed in preceding paragraphs.

sistance and inductance extraction and analysis

The two-port 3T RF MOSFET is implemented with common source configuration that source and body terminals are tied together in metal3 and grounding, and the terminals of DUT connect to GSG pad by metal line. In our experience, the parasitic resistance contributed from the metal line will affect the I-V characteristic of DUT. For the purpose, we will extract the parasitic RL parameters from short pad and extract RL parameters from device directly in this session.

3.2.1 Parasitic RL extraction from short pad

The equivalent circuit of short pad after open de-embeddin a

metal8(M8), we assume that it is composed of parasitic resistance and induct only form metal interconnections between the DUT and the pad, and the parameters with subscript “ext” to represent extrinsic RL parameters.

By analysis the Z parameters of the equivalent circuit of short pad after open

de-embedding, the Z parameters can be express as follow: addition, the parasitic resistance and inductance can be expressed by arrange the

The extracted R and R have the weak frequency dependence at low frequency, the behavior indicated that there are frequency term without considered at high frequency probably. Although it has the behavior, the p

ω

arasitic RL parameters are

Table 3.1 The extracted extrinsic resistance and inductance of short pad Extracted

extrinsic RL

Rg_ext extracted at low frequency.

AVG(2~5G) 0.355 0.589 0.228 57.05 57.72 15.11

3.2.2 Parasitic RL extraction from device

In chapter 3.2.1, we discuss the approximate parasitic resistance and inductance

When MOSFET operating in strong inversion region and Vds=0V, the equivalent

circuit the

from short pad, but this part of resistance and inductance come from metal connection between metal3 and metal8 only, in order to determine total terminal resistance come form metal1 to metal8, parasitic parameters are extracted from device after open de-embedding only directly.

of DUT after open de-embedding can be represented as Fig. 3.6. Refer to

pu our ory, p RL extraction method can be summarized as the following equation.

blishing in laborat arasitic

( )

ch

( )

^dut

3.2.3 Frequency and bias dependence of Parasitic RL

It has been known that gate resistance will influe

noise performance of RF MOSFET at high frequency, for the layout of multi-finger MOSFET, the gate/drain terminal is used p

resistance. The terminal parasitic RL represe inductanc nsists of both intrinsic and e

The effective lumped resistance and inductance can be considered to have a gate bias dependent and a bias independent component, remember that the terminal of DUT connect to the GSG pad by metal only, it means that the bias independent parasitic RL contributed from the extrinsic metal interconnection between M3 and M8, and the bias dependent RL will be contributed from the intrinsic MOSFET device.

nce the input impedance and

arallel structure to reduce the gate/drain nts the effective lumped resistance and

e that co xtrinsic part.

We have extract the parameters from devices with various channel length (L) and cy, and observe that R

-1

ance and the gate electrode resist

gate finger number (NF) at several bias conditions under the suitable frequen

D and RG are almost const in short channel device but sensitive to the gate bias at long channel device, the parasitic resistance decreases with gate bias increases. Thus, the optimizing RG andRD verse (Vgs -Vth) at different geometry is plotted in Fig. 3.7 and Fig. 3.8.

The effective gate resistance that consists of the distributed channel resist ance, the effective drain resistance that consists of the electrode resistance and the resistance contributed from the channel, the expression for gate/drain resistance model can be written as:

_ _

_

_

G g poly g ch

R

g bias g const

gs th

R R

R

= +

R V V

= +

−

(3.15)

_ _

_

D d poly d ch

d bias

^d_^const

gs th

R R R

R V V

= +

−

RG versus inverse of (Vgs -Vth) is plotted to obtain Rg_poly and Rg_ch, where Rg_poly

and Rg_ch represent the gate bias independent resistance and gate bias dependent resistance respectively, Rg_poly

= R +

(3.16)

can be determined from the linear regression of mea

uation in Fig. 3.8. It provides that electrode resistance is bias independent, but distributed channel resistance is bias independent again.

surement data intercept at (Vgs -Vth)^-1=0, in addition, Rg_bias is obtained from the slope of the liner regression equation in Fig. 3.7. Similarly, Rd_const can be determined from the linear regression of measurement data intercept at (Vgs -Vth)^-1=0, Rd_bias is obtained from the slope of the liner regression eq

3.2.4 Device geometry dependence

In this session, we will discuss the geometry d

further, the optimizing R t

1/L, and resistance of NQS effect is

The extracted R and R decrease with increasing finger number (NF) in

g_const, Rd_const, Rg_bias and Rd_bias

verse inverse of NF individually

G G

ependence of gate/drain resistance

G verse channel length at different Vgs is plotted in Fig. 3.9, i shows that RG decreases first as channel length increase while showing a weak bias dependence in the region, then to increase with channel length increase above 0.18um while showing a strong bias dependence. The channel length dependence of RG is strong on longer device and at lower Vgs.

The U-shape channel length dependence of RG in Fig. 3.9 can be explained with the consideration of the distributed effects in both distributed transmission line effect on the gate and NQS effect in the channel. It has been well known that the resistance of a poly-silicon resistor is proportional to

proportional to L.

g_const g_bias

the all devices, Fig. 3.10~3.13 show that extracted R

, the result support us that the linear regression of the resistances is a good reciprocal function of NF, and the behavior proved that the resistance originate from channel distributed effect obviously.

Using the method to separate the bias and geometry dependent and independent component from the R , the total parasitic resistance R can be written as below, where α, β almost is constant.

_ _

_ _

_

G g poly g ch

g poly g nqs

g bias

gs th

_

_

*

* * ( )

g const

g ext

R R R

R R

R R

V V R L

L NF NF V

_gs

V

_th

α β

= + +

−

= +

= +

= +

−

(3.17)

The calculated Rg_poly and Rg_ch verse channel length show in the Fig. 3.14 and Fig. 3.15. Rg_poly decrease with the channel length increasing, and Rg_ch increase with the channel length increasing. When channel is short enough, the contribution of Rg_ch

is smaller than Rg_poly,, Rg_poly is gate bias insensitively and dominate the total resis

-shape channel length dependence of the total gate terminal resistance.

3.3 Extraction of device parameters in linear region

In this section, we will discuss that parameters extraction of MOSFET operating in linear region. When gate voltage is smaller than the threshold voltage and at Vds=

ce extraction and analysis

Capacitances of RF MOSFET are extracted from the intrinsic Y parameters at low acitances extra

tance. As channel length increasing, the NQS effect is more significant, Rg_ch will dominate the RG, and RG has a strong gate bias dependence. So that, it provides that Rg_poly and Rg_ch cause the U

0V, the equivalent circuit of 3T device with parasitic RL parameters and substrate network components can be shown in Fig. 3.16. Cgs0 and Cgd0 represent the gate-to-source and gate-to-drain zero bias capacitances, respectively. Cgb is the total intrinsic and extrinsic gate-to-body capacitances. Cjs and Cjd are diffusion junction capacitances, Rsub represents the substrate resistance and Cdnw is junction capacitance between substrate and deep N-well.

3.3.1 Capacitan

frequency conventionally, short de-embedding is essential for accurate cap

ction in our experience. By performing Y parameter analysis on the circuit of intrinsic DUT in Fig. 3.17, the capacitance of equivalent circuit at low frequency can be express by

( ) ( )

gg

dut C

Y₁₁ =

ω

Im (3.18)

( )

gd

dut C

Y =ω

−Im ₁₂ (3.19)

( ) (

gd jd

)

dut C C

Y₂₂ =ω +

Im (3.20)

For Vgs>Vth,

C

_gg

= C

_gd

+ C

_{gs. For Vgs<Vth,}C_gg =C_gdo +C_gso +C_gb.

Note that the capacitances Cgs and Cgd are equal almost because the symmetry es includes both intrinsic and

pad in operating open de-embedding, and the capacitances decreases by a time constant decay with frequency

goodly dummy open/short pad. Thus, we still extract the capacitances of measured data at low frequency as the initial value of the circuit.

3.3 tance bias etry dependence

structure in this bias condition. The extracted gate capacitanc

extrinsic component of the MOSFET individually, it also can be separated the bias dependent or independent part by the gate voltage. The extracted capacitances appear non-smooth curve in the smaller finger number devices with the frequency, because that small device has the small capacitances compared to the capacitances of the open

increasing, the issue can be solved by the

.2 Capaci and geom

The gate-bias dependences of the optimizing capacitances are shown in Fig.

3.18, the intrinsic capacitance is normally bias dependent while the overlap capacitance is bias independent. when gate voltage small than the threshold voltage, To observe the transcapacitances conservation, the gate capacitances cab be rewrite as the equation Cgg=Cgd0+Cgs0+Cgb, As the gate voltage increases, the channel charges build up to increase the intrinsic component of the extracted capacitances, when the channel charge can be supplied by source/drain to channel rather than body in the strong inversion region, the whole Cgb capacitance which through the active

channel area to source/drain region is very small and can be neglected, the gate capacitances can describe as Cgg=Cgd+Cgs.

In the simplified C-V model, the gate capacitance can be described as equation ce geometry dependenc

(3.21). under a given gate voltage, we will discuss the capacitan

e, Fig. 3.19 and Fig. 3.20 show that the gate capacitances are well proportioned to the NF and channel length, the intercept of Y-axis is much closed to zero, and it verifies that the proposed extraction method is accurate and reliable.

* (

^gs

)

g active active ox

Q = W L C V V

(3.21)

3.3.3 Channel resistance extraction and analysis

When MOSFET operates at strong inversion region and Vds=0V, the extracted channel resistance Rch discussed above in question (3.10), Rch is considered as a intrinsic parameter originate form the inversion layer channel charge, the bias, NF, and channel length dependent are plotted in Fig. 3.21~Fig. 3.23, individually.

As the Vgs increasing, the channel charge can be supplied by source/drain to channel is increasing, the depths

finger number but is propositional to channel length.

nsic resistance from the device only.

FET is of inversion layer is increasing similarly, the behavior will cause the Rch decrease as vgs increase, Rch also decrease as NF increase base on the multi-finger gate/drain structure, but the total Rch is sum of the distributed channel resistance at the source/drain direction, Rch will increase with the longer channel length. So that, channel resistance is inverse proportion to gate voltage and

Rch is well propositional to geometry provided that the channel resistance is dominated by the intri

3.3.4 Substrate resistance extraction and analysis

One of the most important features to be considered when the MOS

oper

T in Fig. 3.17, the parameters of equivalent circuit at low frequency can be express by:

ated at high frequencies is the impact of the substrate network on the output impedance. This substrate network consists of the junction capacitances and the substrate loss resistances, the drain junction capacitance and the bulk spreading resistance are represented by Cjd and Rsub, respectively.

As the operation frequency increases, the impedance of the junction capacitance reduces. The signal coupling through the substrate resistances from the drain to the source and from the drain/source to the substrate contact has to be carefully considered for the output admittance. By performing Y parameter analysis on the circuit of intrinsic DU

(

^{22 12}

)

Im

^{dut dut}

C

jd

= Y + Y ω

(3.22)

( )

^{22 2 2}

Re

^dut

sub jd

R = Y ω C

(3.23) We will extract the substrate parameters using (3.23) as the initial value, In order to achieve the best fit for the simulated and measured S-parameter data, optimization of all the RF component values must be done. The optimizing Cjd and Rbulk geometry dependence are plotted in Fig. 3.24 and Fig. 3.25.

3.4 Extraction of intrinsic parameters in saturation region

y channel structure and current gain. The parameters gm and gds represent the transconductance and the output conductance of the transistor respectively, and uniform channel resistance replace by Rch , Rds and Cds parameters to express the asymmetry inversion

When MOSFET operating in saturation region, the equivalent circuit of DUT after open de-embedding can be represented as Fig. 3.26, the difference between linear region and saturation region is the asymmetr

layer.

Refer to the thesis in our laboratory, and the extraction method of element can be

summarized as the following equation,

d m

gs

g I

V

= ∂

∂

^;

d ds ds

g I

V

= ∂

∂

(3.24)

1

ch ds

g

ds

= R + R

_;

R C

^{ch gs}

= R C

^{ds gd} (3.25)

1.2 0, 1.2

gs ds gs ds

jd V V V jd V V V

C C

= =

=

= = (3.26)

3.4.1 Capacitance extraction and analysis

Extraction of capacitance at Vds=0V (3.18~3.20) to be suitable for use at this condition, the gate bias dependences of extracted capacitances are shown in Fig.

3.27 and Fig. 3.28, Cgs and Cgd are composed of the intrinsic and overlap components, the intrinsic capacitance is normally bias dependent while the overlap capa

acitances.

Cgs has strong gate bias dependence in Fig. 3.27, Cg

bias increases near subthreshold region, and is saturation gradually in the strong inversion saturation region. Cgd only increases slightly with g

under saturation conditions, intrinsic capacitances of Cgd are very small because that drain voltage will deplete the drain side capacitance, an

citance is bias independent. As Vgs increases, the channel charges build up and increase the intrinsic component of the extracted cap

s increases strong as gate

ate bias in Fig. 3.28,

d the total gate-to-drain capacitance is dominated by the overlap capacitance.

From Fig. 3.27, it is observed that as Vds increases, there is a small increase in Cgs., this is because the transistor is approaching the saturation region and the channel is pinched-off when Vds=Vgs-Vth. The channel charge in the source side increases and the intrinsic capacitance of Cgs also increases. For Cgd, when the channel is approaching the pinch-off condition, the charge in the intrinsic drain region decreases and this decreases the intrinsic capacitance of Cgd.

The capacitance geometry dependence are plotted in Fig.3.29 ~ Fig. 3.32, the gate capacitances are well proportioned to the NF and channel length as the description in section 3.3.2.

Fig. 3.1 The equivalent circuit of 3T device with pad

Fig. 3.2 The equivalent circuit of open pad

Fig. 3.3 The equivalent circuit of short pad

Fig. 3.4 The illustration of de-embedding procedure for 3T device

Rg,ext Lg,ext Ld,ext Rd,ext

Rs,ext

Ls,ext

Port1 Port2

Fig. 3.5 The equivalent circuit of short pad after open de-embedding

Fig. 3.6 The equivalent circuit of 3T device at Vgs>>Vth, Vds=0V (Open_de)

0 2 4 6 8 10 12 14

2 4 6 8 10 12 14

Y =1.98+0 X

Y =2.74222+0.00159 X Y =4.89+0 X

12.71+0 X L=0.13um, Vds=0 Y =

NF=6 NF=18 NF=36 NF=72

R G

1/Vg-Vth

0 2 4 6 8 10 12 14

2 4 6 8 10 12 14

Y =1.93561+0.00755 X Y =2.37548+0.0173 X Y =3.95065+0.07304 X Y =10.0322+0.23748 X

0 L=0.18um, Vds=

NF=6 NF=18 NF=36

NF=72 R G

1/Vg-Vth

0 2 4 6 8 10 12 14

5 10 15 20

Y =1.29187+0.08814 X Y =1.93053+0.1933 X Y =2.56023+0.39036 X Y =7.59692+0.91755 X

L=0.35um, Vds=0 NF=6 NF=18 NF=36 NF=72

R G

1/Vg-Vth

0 2 4 6 8 10 12 14

2 4 6 8 10 12 14 16 18 20 22 24 L=0.5um, Vds=0

Y =1.28039+0.17593 X Y =1.38584+0.34572 X Y =2.74468+0.71231 X Y =6.65665+1.18009 X

NF=6 NF=18 NF=36 NF=72

R G

1/Vg-Vth

Fig. 3.7 linear regression of optimized RG versus (Vgs -Vth)^-1 at Vds=0V

0 2 4 6 8 10 12 14

Y =0.64563+0.00622 X Y =0.8002+0.00216 X Y =1.07174+0.00599 X

Y =1.942+5.62066E-4 X L=0.13um, Vds=0 NF=6

Y =0.4824+0.00754 X Y =0.63818+0.00846 X Y =0.9714+0.01107 X Y =2.10659+0.01477 X

L=0.18um, Vds=0 NF=6

Y =0.71329+0.03433 X Y =0.88487+0.06399 X Y =1.89061+0.04848 X Y =5.99764+0.94104 X

L=0.35um, Vds=0 NF=6

Y =0.32146+0.22044 X Y =0.7015+0.23557 X Y =2.04675+0.24657 X Y =6.53914+1.09505 X

L=0.5um, Vds=0 NF=6

Fig. 3.8 linear regression of optimized RD versus (Vgs -Vth)^-1 at Vds=0V

0.1 0.2 0.3 0.4 0.5

NF=6, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V

L (um)

NF=18, Vds=0V Vg=0.4V

NF=36, Vds=0V Vg=0.4V

NF=72, Vds=0V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V

L (um)

Fig. 3.9 The gate resistance optimized RG versus channel length at Vds=0V

0.000 0.03 0.06 0.09 0.12 0.15 0.18

0.00 0.03 0.06 0.09 0.12 0.15 0.18 0

2 4 6 8

0.00 0.03 0.06 0.09 0.12 0.15 0.18 0 Y =0.90912+70.80926 X

L=0.13um, Vds=0V

Rg_poly

1/NF

Y =1.01627+53.91991 X L=0.18um, Vds=0V

Y =1.01627+53.91991 X L=0.18um, Vds=0V

在文檔中 射頻金氧半電晶體小訊號等效電路模型參數萃取方法建立以應用於各種偏壓與幾何結構 (頁 23-0)