CHAPTER 4 EXPERIMENT RESULTS
4.6 S UMMARY
This chapter described in detail the experimental for the chip showed the measurement results of the implementation of the flash A/D converter in 0.13μm CMOS process. The total power dissipation is 88.93mW at 2GHz sampling rate. The measurement of the flash A/D converter is summarized in Table 4.2.
Parameters Measurement Results
Resolution 6 bits
Conversion Rate 2GHz
DNL @ 2GHz sampling rate +1.56 LSB / -1.00 LSB INL @ 2GHz sampling rate +1.91 LSB / -1.85 LSB
Input Range 0.5V Vpp differential
SNDR@2MHz input signal 27.97 dB
SFDR@2MHz input signal 29.04 dB
ENOB@2MHz input signal 4.3 bits
FOM 30.4 pJ
Analog/ Digital Power dissipation 64.27mW/ 24.66mW
Supply Voltage 1.2V
Technology UMC 0.13μm CMOS
Table 4. 2 Measurement performance summary
CHAPTER 5
CONCLUSIONS
5.1 Summary
A 6-bit low-power high-speed flash A/D converter is proposed for UWB wireless applications. Use sample-and-hold to improve dynamic performance of A/D converter. when the input frequency is near the Nyquist frequency. Use interpolation technique to reduce the number of preamplifier and input capacitance. The A/D converter with interpolation technique consumes less power than full flash and improves differential non-linearity (DNL) of A/D converter. Add averaging resistance to reduce the offset of preamplifier and comparator and reduce the DNL to improve linearity. About 83% power saving by averaging resistance in preamplifiers is achieved. Use digital error correction technique to reduce bubble error and metastability error. The power of (2n-1)m pipeline latches is eliminated by the digital correction circuit. By combining these techniques, the first version A/D converter consumes about 88.4mW from 1.2V power supply at 2GSample/s and the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) maintain above 29.54dB and 30.64dB for input frequency of 2MHz. The peak differential -nonlinearity (DNL) and peak integral-nonlinearity (INL) is less than 1.47LSB and 1.83LSB.
By combining above techniques, the second version A/D converter consumes about 117mW from 1.2V power supply at 2GSample/s and the SNDR and SFDR maintain above 32.2 and 33.68dB for input frequency of 976MHz. The FOM of the A/D converter is 1.81pJ. The peak
DNL and peak INL is less than 0.1LSB and 0.14LSB.
The chip of first version A/D converter is fabricated in 0.13-μm CMOS technology. The supply voltage of analog and digital circuits is 1.2V and feeds them separately. The total power dissipation is 88.93mW at 2GHz sampling rate. The measurement of the SNDR is 27.97dB and SFDR is 29.04dB under 2GHz sampling rate and 2MHz input frequency. The measured DNL and INL are +1.56/-1.00 LSB and +1.91/-1.85LSB. The effective number of bits (ENOB) is calculated equal to 4.3 bits.
5.2 Future Work
In this thesis, we have two versions of the A/D converter circuit design. We just send the first version A/D converter for tape-out and there are some design considerations which are not paid an attention. We give some recommendations and improvement in this section. First, circuit simulation time is too long to waste a lot of time. In order to eliminate the long simulation time by HSPICE or SPECTRE, the behavior model can be constructed by MATLAB/SIMULINK to understand the influence on the A/D converter due to device mismatches and also realize the dynamic performance of the A/D converter. Second, the high speed testing is difficult for digital output. In order to have a better measurement performance, the digital output signal can be decimated at A/D converter output for measurement or design low-voltage differential signaling (LVDS) drivers at digital outputs for high speed digital applications. Finally, the second version of the A/D converter circuit design will be for next time tape-out and will get better performance in the future work.
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Appendix
The first cross-coupling type S/H configuration
Figure A. 1 The first cross-coupling type S/H Configuration
Gain analysis:
Figure A. 2 The small signal of the first cross-coupling type S/H for gain calculation
2
From figure, use superposition method and then the single output voltage is given by
2
Figure A. 3 The small signal of the first cross-coupling type S/H for 3db frequency calculation
)
The second cross-coupling type S/H configuration
V
Figure A. 4 The second cross-coupling type S/H Configuration
Gain analysis:
Figure A. 5 The small signal of the second cross-coupling type S/H for gain calculation
From figure, use superposition method and then the single output voltage is given by
'
1 )
Figure A. 6 The small signal of the second cross-coupling type S/H for 3db frequency calculation
)
and 3db frequency is given by)
簡 歷
姓 名： 陳世基
性 別： 男
籍 貫： 台灣省新竹縣
生 日： 西元1973 年 2 月 7 日
地 址： 新竹縣竹北市新光街 31 巷 6 號
學 歷： 國立交通大學 電機學院 電子與光電學程 碩士班 2003/09 ~ 2007/06
私立高雄工學院 電子工程學系 1992/09 ~ 1996/06 經 歷： 鈺創科技股份有限公司 測試工程師 2000/06 ~ 2006/09 科榮股份有限公司 設備工程師 1998/06 ~ 2000/04 論文題目： A Low-Power High-Speed A/D Converter Design for UWB Wireless
Applications
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