CHAPTER 3 LOW-POWER HIGH-SPEED TECHNIQUES AND CIRCUIT DESIGN
3.10 S IMULATION R ESULTS
3.10.2 Dynamic Performance Simulation
Figure 3.41 shows the dynamic performance of first version A/D converter at 2GHz sampling rate and 2MHz input frequency. The simulated SNDR, SFDR and ENOB are 29.54dB and 30.64dB and 4.61bits.
Figure 3.42 shows the dynamic performance of first version A/D converter at 2GHz sampling rate and the SNDR is decreased due to improper conditions at the edges of the preamplifiers.
SNDR=29.54dB SFDR=30.64dB ENOB=4.61 bits
Figure 3. 41 Dynamic performance at a input frequency of 2MHz for first version A/D converter, sampled at 2GHz
Figure 3. 42 SNDR and SFDR versus input frequency for first version A/D converter, sampled at 2GHz
Figure 3.43 shows the dynamic performance of second version A/D converter at 2GHz sampling rate and 7.81MHz input frequency. The simulated SNDR, SFDR and ENOB are 37.51dB and 48.94dB and 5.93bits.
Figure 3.44 shows the dynamic performance of second version A/D converter at 2GHz sampling rate and 492.18MHz input frequency. The simulated SNDR, SFDR and ENOB are 35.22dB and 38.65dB and 5.55bits.
Figure 3.45 shows the dynamic performance of second version A/D converter at 2GHz sampling rate and 976MHz input frequency. The simulated SNDR, SFDR and ENOB are 32.20dB and 33.68dB and 5.05bits.
Figure 3.46 shows the dynamic performance of second version A/D converter at 2GHz sampling rate and input frequency from low frequency to Nyquist frequency.
SNDR=37.51dB SFDR=48.94dB ENOB=5.93 bits
Figure 3. 43 Dynamic performance at a input frequency of 7.81MHz for second version A/D converter, sampled at 2GHz
SNDR=35.22dB SFDR=38.65dB ENOB=5.55 bit
Figure 3. 44 Dynamic performance at a input frequency of 492.18MHz for second version A/D converter, sampled at 2GHz
SNDR=32.20dB SFDR=33.68dB ENOB=5.05 bits
Figure 3. 45 Dynamic performance at a input frequency of 976.52MHz for second version A/D converter, sampled at 2GHz
Figure 3. 46 SNDR and SFDR versus input frequency for second version A/D converter, sampled at 2GHz
Power consumption (mW) (interpolation)
Power consumption (mW) (full preamplifiers)
Clock generator 7.5 7.5
Sample-and-hold 17.1 17.1
Resistor ladder 0.2 0.2
Preamplifier 16.6 32.8
Comparator 73.8 73.8
Auxiliary circuit and AND gate 0.9 1
Gray-encoded ROM and TSPC 0.3 0.3
Gray-to-binary decode 0.7 0.8
Total 117.1 133.5
Table 3. 1 Power saving after using interpolation technique
Technology CMOS 0.13μm
Supply voltage 1.2 V
Resolution 6 bits
Sampling rate 2 GHz
Full scale input 0.5 Vpp
DNL/INL 0.1LSB/0.14LSB SNDR@fin=7.81MHz/976.56MHz 37.51dB/32.20dB
SFDR@fin=7.81MHz/976.56MHz 48.94dB/33.68dB ENOB@fin=7.81MHz /976.56MHz 5.93 bits/5.05 bits
Power dissipation 117mW
Table 3. 2 The summary of second version A/D converter performance
Figure 3. 47 The FOM comparison with publication paper
Table 3.1 shows the power saving after using interpolation technique. The preamplifier array can reduce 16.2mW when using interpolation technique. Table 3.2 shows the summary of second version A/D converter performance. The total power dissipation is 117mW and ENOB is 5.05 when input frequency approaches Nyquist frequency. The value of figure-of-merit (FOM) can be calculated and FOM without output buffer is 1.81pJ. The FOM comparison with other publication paper [15][22][23][24][25][26][27] are shown in Figure 3.47 The FOM is much lower than other published paper in our design by using sample-and-hold, interpolation, averaging and digital error correction technique.
CHAPTER 4
EXPERIMENT RESULTS
We have two versions of the A/D converter circuit design and just send the first version A/D converter for tape-out. After each circuit has been designed and simulated, this chapter starts with some back-end considerations for first version A/D converter, including layout technique, parasitic effects of package and bond wire, the electrostatic-discharging (ESD) protection, design of printed circuit board (PCB) and also measurement setup. While device scaling has enhanced the speed of transistors, unwanted interaction between different sections of integrated circuits as well as non-idealities in the layout and packaging increasingly limit both the speed and the precision of such systems. Today’s circuit design is very heavily influenced by back-end considerations. Since this analog-to-digital converter design operates at high frequency as several mega-hertz to giga-hertz, these back-end considerations have great influences on the performance of proposed design.
4.1 Layout Design Consideration
For A/D converter circuit design, even with the same schematic design, different layouts will make entirely difference performance of the circuit. Therefore, the design of the layout is an important topic, especially for high frequency design. The most important things of the layout are parasitic and mismatches. For example, long metal lines will cause the parasitic capacitance and resistance to decrease the bandwidth and gain loss of the circuit. Improper layout could result in large difference of performance between simulated and measurement
result, or even result in failed circuits.
Figure 4. 1 Layout floorplan of A/D converter
The chip floorplan is shown in Figure 4.1. Layout plays an important role for the A/D converter design, since there are usually analog and digital parts in a A/D converter, and the signal coupling from digital part to sensitive analog part should be avoided. The analog power supply and digital supply are separated and the double guard ring is added in analog circuits and digital circuits to prevent the analog circuits from the digital noise. The power supply for the analog part and digital parts are only 1.2V. The analog power supply is fed to sample-and-hold, the preamplifier array and the comparator array and the digital power supply is fed to auxiliary circuits, AND gates, Gray-encoded ROM, TSPC flip flops, Gray-to-Binary decoder, clock generator and output buffers. In order to avoid large supply noise and ground bounce, large decoupling capacitances are added in DC power line for whole chip area. All the line widths are drawn according to following criteria, minimizing parasitic capacitance and series resistance. The DC current paths should be wide enough to prevent electro-migration. The line length of signal path should be kept as short as possible.
The layout photograph of the flash A/D converter is shown in Figure 4.2, and the core circuit
area is 410μm x 530μm.
Decoupling Capacitor
Decoupling Capacitor Sample-and-hold Clk
Resistor Ladder Preamplifier & Averaging 1 Compar ator & Aver aging 2 Digital Error Correction Circuit Output Buffer
Figure 4. 2 Core layout photograph of the A/D converter
4.2 ESD Protection and Package
In the package, the electrostatic discharge (ESD) protection is added to each I/O pin. For thin oxide process, ESD protection is also a critical issue. Due to the process scales down, the channel is shorter and the tolerance of the gate voltage is smaller. Thus, MOSFET will be easily punctured. Figure 4.3 illustrates the ESD protection circuit used in proposed design.
The diode-chain protection will guide large number of charges to VDD or GND, and the large gate-grounded NMOS will break down once a large potential across VDD and GND resulting in the charge in VDD flowing through NMOS to GND. The ESD circuit is provided by UMC
with 3.6kV human body mode (HBM) tolerance and induces around 40fF parasitic capacitor at each pad.
Figure 4. 3 ESD protection circuit
The QFN32 package provided by SPIL is employed in proposed design. This package is limited to 32 I/O pins. The overall area of package is 5 x 5 mm2. The package model including bond wire effect of each I/O pin is depicted in Figure 4.4. The parasitic capacitor induced at each I/O pad is around 40fF while the series inductance induced by bone wire is about 1nH. Furthermore, the parallel capacitor will lead to signal coupling between adjacent pin which are the most concern of proposed design.
Figure 4. 4 Package model
Figure 4. 5 Layout photograph of the A/D converter
The final layout photograph of the A/D converter is shown in Figure 4.5 including the A/D converter core circuit and ESD circuits. The chip is separated by analog part and digital part to avoid noise coupling. The layout area include IO pad is 1686um x 1686um.
4.3 Printed Circuit Board (PCB) Design
The printed-circuit board (PCB) is designed by using Protel 99 SE. The pin assignment is shown in Figure 4.6 and the function of the pin is shown in Table 4.1. In order to prevent noise coupling from digital circuits to analog circuits, the analog part and the digital part are separated. The analog power supply and digital power supply are also separated.
Figure 4. 6 The schematic of the pin assignment
As for the implementation of printed-circuit board (PCB), we adopt “RO4003” as our dielectric owning to this material has less loss at high frequency operation. We employ four-layer board to firm up the copper signal line, and further stabilize the high frequency signal paths. The large bypass capacitors are also added in the PCB in order to provide a stable DC voltage and avoid the unexpected performance degradation. The schematic of the PCB design is shown in Figure 4.7. The input differential signal is created by a transformer and signal generator. The PCB layout view is shown in Figure 4.8.
Pin Number Pin Name Function
1 VC Comparator current bias
2 VBIAS Preamplifier current bias
3 VA Sample-and-hold current bias
4 VIN Negative differential input signal 5 VIP Positive differential input signal 6 VRT Resistor ladder top voltage 7 VRB Resistor ladder bottom voltage 8 VDDE Supply of ESD Protection 9 GNDE Ground of ESD Protection 10 VDDD Digital power supply 11 VDDD Digital power supply 12 VDDD Digital power supply 13 VDDD Digital power supply
14 GNDD Digital ground
15 GNDD Digital ground
16 GNDD Digital ground
17 SYN Synchronization for measurement 18 B5 Digital Output (MSB)
Figure 4. 7 The schematic of the PCB design.
Figure 4. 8 The layout of the PCB
Clock
Anal og Input D ig ita l O u tput
Bypass
Capacitance
Figure 4. 9 The PCB of the flash A/D converter
The clock signal is created by a signal generator and a bias-tee. The input signal and clock signal path have to concern the input matching to prevent the signal degradation and the output of the A/D converter has to assign a synchronization pin for measurement. The PCB of the A/D converter is shown in Figure 4.9. The material of the PCB is RO4003 which is suitable for high frequency operation. In order to filter the supply noise, large bypass capacitances are located near the chip.
4.4 Measurement Setup
Figure 4. 10 Measurement plan
The measurement setup is also an important issue in the A/D converter design. The measurement plan is shown in Figure 4.10. We need several instruments such as ESG, Logic Analyzer, Oscilloscope and Power Supply. The input and output of these instruments are usually single-ended, so single-to-differential conversion is needed. The single-to-differential input signal is generated by the transformer which the model is Mini-Circuits ADT4-6WT.
The analog input signal source and the clock source are generated by the ESG which is produced by Agilent E4432B and The input signal clock is produced by the Bias-T which the type is ZNBT 60-1W. The transformer and Bias-T are shown in Figure 4.11. The module of the logic analyzer is 16902A which the timing can achieve 2GHz.The testing environment is shown is Figure 4.12 and the device under test is shown in Figure 4.13.
Transformer Bias-T
Figure 4. 11 Transformer and Bias-T
ESG
DUT
Logic Analyzer Power Supply
Figure 4. 12 Testing environment
Bias Tee
Single to Differential DUT
Voltage Regulator
Figure 4. 13 Device under test
4.5 Measurement Results
The low-power high-speed flash A/D converter architecture with sample-and-hold, interpolation, resistive averaging and digital error correction technique and design concepts are described in Chapter3. In this section, we just show measurement results of first version A/D converter because second version A/D converter is not sent for tape-out and the first version circuits is fabricated by UMC 0.13μm single-poly-eight-metal (1P8M) CMOS technique. The analog power supply and digital power supply are 1.2V and the power dissipation is 88.93mW at 2GHz sampling rate. The data files are computed by the FFT testing [28] to measure the signal-to-noise-and-distortion ratio (SNDR), and spurious-free dynamic range (SFDR). The differential -nonlinearity (DNL) and integral-nonlinearity (INL) measurement is adopted by the histogram testing method [29].
4.5.1 Dynamic Testing
The dynamic testing plot from instrument is shown in Figure 4.14. The input frequency is 1.007MHz and the sampling frequency is 300MHz.
Figure 4. 14 Dynamic testing plot from Logic Analyzer
Figure 4. 15 Dynamic performance versus sampling frequency
The dynamic performance of the A/D converter is shown in Figure 4.15, the SNDR and SFDR is plotted against the sampling frequency. The input frequency is 2MHz and the SNDR is 27.97dB and SFDR is 29.04dB when the clock frequency at 2GHz. The effective number of bits is calculated equal to 4.3 bits.
4.5.1.1 Sampling Frequency at 300MHz
The dynamic performance of the A/D converter at 300MHz sampling frequency is described in this section. Figure 4.16 shows the FFT plot at 1.007M. Figure 4.17 shows the SNDR versus input frequency at 300MHz sampling rate and the SNDR is decreased due to improper conditions at the edges of the preamplifiers. Figure 4.18 shows the SFDR versus input frequency at 300MHz sampling rate. Figure 4.19 shows SNDR versus sampling rate at 1MHz input frequency. Figure 4.20 shows SFDR versus sampling rate at 1MHz input frequency.
Figure 4. 16 FFT plot at 1.007MHz input frequency.
Figure 4. 17 SNDR versus input frequency at 300MHz sampling rate
Figure 4. 18 SFDR versus input frequency at 300MHz sampling rate
Figure 4. 19 SNDR versus sampling rate at 1MHz input frequency
Figure 4. 20 SFDR versus sampling rate at 1MHz input frequency
4.5.1.2 Sampling Frequency at 2GHz
In this section, the operation frequency at 2GHz is presented. Figure 4.21 shows the SNDR versus input frequency at 2GHz sampling rate and the SNDR is decreased due to improper conditions at the edges of the preamplifiers. Figure 4.22 shows the SFDR versus input frequency at 2GHz sampling rate. Figure 4.23 shows SNDR versus sampling rate at 2MHz input frequency. Figure 4.24 shows SFDR versus sampling rate at 2MHz input frequency.
Figure 4. 21 SNDR versus input frequency at 2GHz sampling rate
Figure 4. 22 SFDR versus input frequency at 2GHz sampling rate
Figure 4. 23 SNDR versus sampling rate at 2MHz input frequency
Figure 4. 24 SFDR versus sampling rate at 2MHz input frequency
4.5.2 Static Testing
The 16384 samples of data are collected to compute the DNL and INL which is shown in Figure 4.25 and 4.26. The sampling frequency is 2GHz and input frequency 2MHz sine wave is digitalized by the A/D converter under test. The measurement DNL is between +1.56 and -1.00 LSB and the measurement INL is between +1.91 and -1.85 LSB. The offset error is bad controlled in the A/D converter design to degrade the performance.
Figure 4. 25 Measured DNL error
Figure 4. 26 Measured INL error
4.6 Summary
This chapter described in detail the experimental for the chip showed the measurement results of the implementation of the flash A/D converter in 0.13μm CMOS process. The total power dissipation is 88.93mW at 2GHz sampling rate. The measurement of the flash A/D converter is summarized in Table 4.2.
Parameters Measurement Results
Resolution 6 bits
Conversion Rate 2GHz
DNL @ 2GHz sampling rate +1.56 LSB / -1.00 LSB INL @ 2GHz sampling rate +1.91 LSB / -1.85 LSB
Input Range 0.5V Vpp differential
SNDR@2MHz input signal 27.97 dB
SFDR@2MHz input signal 29.04 dB
ENOB@2MHz input signal 4.3 bits
FOM 30.4 pJ
Analog/ Digital Power dissipation 64.27mW/ 24.66mW
Supply Voltage 1.2V
Technology UMC 0.13μm CMOS
Table 4. 2 Measurement performance summary
CHAPTER 5
CONCLUSIONS
5.1 Summary
A 6-bit low-power high-speed flash A/D converter is proposed for UWB wireless applications. Use sample-and-hold to improve dynamic performance of A/D converter. when the input frequency is near the Nyquist frequency. Use interpolation technique to reduce the number of preamplifier and input capacitance. The A/D converter with interpolation technique consumes less power than full flash and improves differential non-linearity (DNL) of A/D converter. Add averaging resistance to reduce the offset of preamplifier and comparator and reduce the DNL to improve linearity. About 83% power saving by averaging resistance in preamplifiers is achieved. Use digital error correction technique to reduce bubble error and metastability error. The power of (2n-1)m pipeline latches is eliminated by the digital correction circuit. By combining these techniques, the first version A/D converter consumes about 88.4mW from 1.2V power supply at 2GSample/s and the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) maintain above 29.54dB and 30.64dB for input frequency of 2MHz. The peak differential -nonlinearity (DNL) and peak integral-nonlinearity (INL) is less than 1.47LSB and 1.83LSB.
By combining above techniques, the second version A/D converter consumes about 117mW from 1.2V power supply at 2GSample/s and the SNDR and SFDR maintain above 32.2 and 33.68dB for input frequency of 976MHz. The FOM of the A/D converter is 1.81pJ. The peak
DNL and peak INL is less than 0.1LSB and 0.14LSB.
The chip of first version A/D converter is fabricated in 0.13-μm CMOS technology. The supply voltage of analog and digital circuits is 1.2V and feeds them separately. The total power dissipation is 88.93mW at 2GHz sampling rate. The measurement of the SNDR is 27.97dB and SFDR is 29.04dB under 2GHz sampling rate and 2MHz input frequency. The measured DNL and INL are +1.56/-1.00 LSB and +1.91/-1.85LSB. The effective number of bits (ENOB) is calculated equal to 4.3 bits.
5.2 Future Work
In this thesis, we have two versions of the A/D converter circuit design. We just send the first version A/D converter for tape-out and there are some design considerations which are not paid an attention. We give some recommendations and improvement in this section. First, circuit simulation time is too long to waste a lot of time. In order to eliminate the long simulation time by HSPICE or SPECTRE, the behavior model can be constructed by MATLAB/SIMULINK to understand the influence on the A/D converter due to device mismatches and also realize the dynamic performance of the A/D converter. Second, the high speed testing is difficult for digital output. In order to have a better measurement performance, the digital output signal can be decimated at A/D converter output for measurement or design low-voltage differential signaling (LVDS) drivers at digital outputs for high speed digital applications. Finally, the second version of the A/D converter circuit design will be for next time tape-out and will get better performance in the future work.
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