CHAPTER 1 INTRODUCTION
1.2 T HESIS O RGANIZATION
The organization of this thesis is overviewed as follows.
Chapter 2 reviews the architectures and applications of A/D converter. Chapter 3 presents wideband sample-and-hold, interpolation, cascade resistive averaging and digital error correction techniques to reach the low-power high-speed performance and then describes the design of each building block and analyzes the simulation results. Chapter 4 presents the test procedure and the experimental results obtained for the prototype and finally Chapter 5 concludes with a summary of contributions and recommendations for future work.
CHAPTER 2
Review of A/D Converter architectures and applications
In this Chapter, we first review a number of A/D converter architectures suited to different speed operation and study their speed-resolution-power trade-offs. Of interest to us are flash, pipelined, sigma-delta architectures.
Next, we describe general potential applications of A/D converters with different architectures, speed, resolution, and power dissipation. These include fiber-optic communication, digital oscilloscope, medical imaging, CCD imaging electronics, touchscreen digitizers and digital audio.
2.1 A/D Converter Architectures
A variety of A/D converters exist on the market today, with differing resolutions, bandwidths, accuracies, architectures, packaging, power requirements, and temperature ranges, as well as specifications, covering a broad range of performance needs. And indeed, there exists a variety of applications in data acquisition, communications, instrumentation, digital audio, and interfacing for signal processing, all having different requirements. Considering architectures, for some applications just about any architecture could work well; for others, there is a best choice. In some cases the choice is simple because there is a clear-cut advantage to using one architecture over another, but in some cases the choice is more subtle.
For example, flash A/D converters are most popular for applications requiring a throughput
rate of more than 1 GSPS with low resolution. Sigma delta converters are usually the best choice when very high resolution (20 bits or more) is needed. The differences in their architectures make one or the other a better choice, depending on the application. Among the variety of A/D converter architectures, the most popular presently used are flash A/D converter, pipelined A/D converter, and sigma-delta A/D converter [5][6]. In the following sections, these popular A/D converter architectures are briefly described.
2.1.1 Flash A/D Converter
The flash A/D converter architecture, also known as a fully parallel architecture, is fundamentally the fastest architecture. This architecture is conceptually the easiest to understand. An n-bit flash A/D converter consists of an array of 2n-1 comparators and a set of 2n -1 reference values, shown in Figure 2.1. Each of the comparators samples the input signal and compares the signal to one of the reference values. Each comparator then generates an output indicating whether the input signal is larger or smaller than the reference assigned to that comparator. The differences between the input and reference values are amplified to digital levels and generate thermometer code. The encoder converts the thermometer code produced by the comparators to a binary code. As seen from the figure, the comparators all operate in parallel. Thus, the conversion speed is limited only by the speed of the comparator.
For this reason, the flash A/D converter is capable of high speed and it is used for high-speed applications such as wireless receiver, digital oscilloscopes, high-density disk drives, and so on.
Figure 2. 1 Flash A/D Converter Architecture
The primary drawbacks to the flash A/D converter are the large hardware requirement and sensitivity to comparator offsets. As mentioned earlier, 2n-1 comparators are required. For example, a 6-bits flash A/D converter needs 63 comparators, but 10-bits flash A/D converter needs 1023 comparators. For this reason, a high resolution flash A/D converter requires a large circuit area and dissipates high power. Furthermore, the large number of comparators present a large capacitance to the output of the sampling circuit. The required comparator offset voltage for a flash A/D converter with n bit resolution is less than 1/2n. At high resolutions, this required comparator offset becomes very small. Because comparators with small offsets are difficult to design and expensive to build and because so many comparators are required, A/D converters with resolutions higher than 8 bits rarely use the flash architecture.
2.1.2 Pipelined A/D Converter
The pipelined architecture effectively overcomes the limitations of the flash architecture.
A pipelined converter divides the conversion task into several consecutive stages. Pipelining enables potentially faster conversion while avoiding the exponential growth of power and hardware. Figure 2.2 illustrates the block diagram of a pipelined A/D converter. The analog input is applied to the first stage in the chain, and N1 bits are detected. The analog residue is also generated and applied to the next stage. The same procedure repeats up to the end of the chain. This concept is similar to the idea of an assembly line because the interstage sampling allows all of the stages to operate concurrently. A common approach to pipelining is based on a precision multiply-by-two stage that merges most of the interstage operations into a compact circuit. Usually used with 0.5 bits of overlap, this technique provides a modular implementation.
Figure 2. 2 Pipelined A/D Converter Architecture
The pipelined architecture offers a number of advantages. First, the throughput rate is determined by the speed of only one stage in the pipeline. Second, interstage residue
amplification relaxes the precision required of subsequent stages. Third, the power and hardware of pipelined converters grow almost linearly with the number of bits. Also, overlap and digital correction can be used to allow large offsets in the comparators.
The primary drawback of the conventional pipelined topology is the need for high precision in the interstage SHAs, D/A converters, and subtractors, especially at the front end.
The precision typically mandates the use of op amps, imposing severe trade-offs among speed, voltage swing, gain, and power dissipation. As device dimensions, supply voltages, and the intrinsic gain (gm
r
o) of MOSFETs continue to scale down, the design of op amps becomes increasingly more difficult.2.1.3 Sigma-Delta A/D Converter
The sigma-delta architecture takes a fundamentally different approach than those outlined above. In its most basic form, a sigma delta converter consists of an integrator, a comparator, and a single bit D/A converter, as shown in Figure 2.3. The output of the D/A converter is subtracted from the input signal. The resulting signal is then integrated, and the integrator output voltage is converted to a single-bit digital output (1 or 0) by the comparator.
The resulting bit becomes the input to the D/A converter, and the output of the D/A converter’s is subtracted from the A/D converter input signal, etc. This closed-loop process is carried out at a very high “oversampled” rate. The digital data coming from the A/D converter is a stream of “ones” and “zeros,” and the value of the signal is proportional to the density of digital “ones” coming from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output.
Figure 2. 3 Sigma-Delta A/D Converter Architecture
One of the most advantageous features of the sigma-delta architecture is the capability of noise shaping, a phenomenon by which much of the low-frequency noise is effectively pushed up to higher frequencies and out of the band of interest. As a result, the sigma-delta architecture has been very popular for designing low- bandwidth high-resolution A/D converters for precision measurement. Also, since the input is sampled at a high
“oversampled” rate, unlike the other architectures, the requirement for external anti-alias filtering is greatly relaxed. A limitation of this architecture is its latency, which is substantially greater than that of the other types. Because of oversampling and latency, sigma-delta converters are not often used in multiplexed signal applications. To avoid interference between multiplexed signals, a delay at least equal to the decimator’s total delay must occur between conversions. These characteristics can be improved in sophisticated sigma-delta A/D converter designs by using multiple integrator stages and/or multi-bit D/A converters.
2.1.4 Summary of A/D converter Architectures
The most popular A/D converter architectures have been reviewed in the previous sections. The flash A/D converter architecture is the fastest, the Sigma-Delta A/D converter is very useful for high-resolution applications, and the pipelined A/D converter can be applied
for various applications. Each A/D converter architecture has tradeoffs among speed, resolution, and power dissipation. In summary, Table 2.1 provides the characteristics of popular A/D converter architectures [7]. In the third column, “sps” stands for samples per second. The “m” shown in the fourth column is the number of stages in the pipeline architecture.
Architecture Resolution (bits)
Speed (sps)
Latency (cycle)
Comments
Flash < 10 250M ~ 2G 1 -high input bandwidth -highest power dissipation -large die size
Pipeline 8 ~ 16 1M ~ 200M m -high throughput rate -low-power dissipation -on-chip self calibration Sigma-Delta > 14 > 200K large -high resolution
-limited sampling rates -digital on-chip filtering Table 2. 1 Summary of A/D converter architectures
2.2 A/D Converter applications
There are several applications require the different speed and resolution of A/D converters. Among these are communication, instrumentation, digital audio, digital video, and medical diagnostic equipment [8][9]. With the aid of digital signal processing (DSP), the A/D converter outputs can be processed to bring almost limitless versatility to an application. The basic building blocks of a typical system with a A/D converter include filter for analog input, A/D converter, DSP and memory system, processor and interface system, D/A converter and filter for analog output.
2.2.1 Fiber-optic Communication
High-speed fiber-optic communication requires the analog signal to be converted to digital a A/D converter. Following this the A/D converter outputs must be converted from parallel to serial output format for the driver to modulate a laser diode, as shown in Figure2.4.
This allows a single fiber-optic cable to transmit several high-speed signals if necessary. On the other end of the cable, the photodiode detects the digital light pulses, which are then converted to logic level in a parallel format. The D/A converter output is finally filtered by an analog filter. Depending on the application, an option may be to first perform digital filtering before outputting to the D/A converter.
Figure 2. 4 Fiber-optic Communication
2.2.2 Digital Oscilloscope
A block diagram of a digital storage oscilloscope is shown in Figure2.5. Two input channels are first conditioned by a programmable amplifier. The trigger circuit controls when the sampling starts, which is controlled by sample-and-holds. Buffer amplifiers are required to isolate the low-impedance A/D converter input stage from loading the sample-and-holds.
Once digitalized by the A/D converter, the input signals are stored in memory where a DSP can perform several operations (i.e., filtering, averaging, peak-to-peak time versus voltage, root-mean-square, etc.). Two D/A converters then provide both the vertical (signal measurement) and horizontal (time measurement) analog output signals. Finally the analog outputs are filtered before they go to the display driver.
Figure 2. 5 Digital Oscilloscope
2.2.3 Medical Imaging
The One form of medical imaging is digital x ray (radiography), illustrated in Figure 2.6.
With this technique, the images no longer need to be produced or stored on film. Instead, the images are stored within memory for display on a video monitor. In this system the x ray passes through a person onto photomultiplier fluoroscope sensor which converts the x rays to light. The various light intensities are then converted to an analog signal which is filtered before being digitized by the A/D converter. The DSP then enhances the image before driving the output D/A converter for the video image. The advantages to this process are that the time exposure to the x ray for a quality image is significantly shortened and stored images can be manipulated to enhance specific areas.
Figure 2. 6 Digital Radiography System
2.2.4 CCD Imaging Electronics
The charge-coupled-device (CCD) and contact-image-sensor (CIS) are widely used in consumer imaging systems such as scanners and digital cameras. A generic block diagram of an imaging system is shown in Figure 2.7. The imaging sensor (CCD, CMOS, or CIS) is exposed to the image or picture much like film is exposed in a camera. After exposure, the output of the sensor undergoes some analog signal processing and then is digitized by an A/D converter. The bulk of the actual image processing is performed using fast digital signal
processors. At this point, the image can be manipulated in the digital domain to perform such functions as contrast or color enhancement/correction, etc.
Figure 2. 7 Generic Imaging System for Scanners or Digital Cameras
2.2.5 Touchscreen Digitizers
The touchscreens have become widespread in hand held PDAs (Personal Digital Assistants) and other computer products. The majority of PDA makers use a four-wire resistive element as the touchscreen due to its low cost and simplicity. For the touchscreen to interface with the host processor, analog waveforms from the screen must first be converted to digital data . The user enters data on the screen with a stylus. An A/D converter converts this analog information to digital data that the host microprocessor uses to determine the stylus's position on the screen. During coordinate measurement, one of the resistive planes is powered through on-chip switches on the controller A/D converter. For X coordinate measurement, the X plane is powered. The Y plane senses where the pen is located on the powered plane. When the pen depresses on the screen, the planes short at this location (shown as the dotted line in the diagram). The voltage detected on the sense plane is proportional to the location of the touch on the powered plane. The four -wire resistive touchscreen interface for X coordinate measurement as shown in Figure 2.8. The Y coordinate can be measured by applying power to the Y plane, using the X plane to sense the position. Thus, X and Y coordinates can be
digitized from the screen. The digital code is then operated on by the host CPU, and character recognition and position information can be achieved.
Figure 2. 8 Four-Wire Resistive Touchscreen Interface
2.2.6 Digital Audio
Modern wireless systems, such as cellular telephone, use low pass filter, high resolution A/D converters, digital signal processor (DSP) and high resolution D/A converters. The modern cell phone handset block is shown in Figure 2.9.When we speak to other person with cell phone, the low pass filter remove noise from voice, A/D converter transform voice into digital signal and then the digital signal is dealt with DSP. Modern cellular transmission systems make use of DSP-based speech compression algorithms in order to reduce the overall data rate to acceptable levels, rather than limiting the resolution of the converters. Digital audio systems place high resolution demands on A/D converters and D/A converters because of the wide dynamic range requirements. The digital audio signal may then be stored or transmitted. Digital audio storage can be on a flash memory, or any other digital data storage device. Audio data compression techniques — such as MP3— are commonly employed to reduce the size. Digital audio can be streamed to other devices. The last step for digital audio
is to be converted back to an analog signal with a D/A converter.
Figure 2. 9 Modern Cell Phone Handset block
CHAPTER 3
Low-Power High-Speed Techniques and Circuit Design
In this chapter, the low-power high-speed architecture is proposed to reduce the input capacitance, offset errors, power dissipation, bubble errors and metastability errors by using sample-and-hold, interpolation, averaging and digital error correction techniques. With the architecture, the dynamic performance is improved, the input capacitance is reduced, 83%
power saving in preamplifiers is achieved and the power of (2n-1)m pipeline latches is removed.
The circuit design and related issues will be discussed in detail. The required resolution is 6 bits and the sampling rate is 2GHz. As the result, circuit design plays an important role to achieve the specifications. The block diagram of the proposed A/D converter is shown in Figure 3.1. The proposed A/D converter consists of analog part and digital part. The analog part consists of sample-and-hold, resistor ladder, interpolation preamplifiers, comparators and resistive averaging. The digital part consists of auxiliary circuit, AND gates, ROM, TSPC, Gray-to-binary decoder, clock generator and output buffer. The design issues of each component are discussed step by step. Finally, the static and dynamic performances simulation results are presented in the last section.
Figure 3. 1 Block diagram of the proposed low power A/D converter
3.1 Sample-and-Hold Technique
The purpose of the sample-and-hold (S/H) circuit is to track and hold the input signal long enough for the A/D converter to complete a conversion without appreciable error. The S/H circuit is a crucial part, especially for high speed sampling rates. To improve the dynamic performance of the A/D converter, a S/H circuit can be put in front of the converter. By holding the analog sample static during digitization, the S/H largely removes errors due to skews in clock delivery to a large number of comparators, limited input bandwidth prior to latch regeneration, signal-dependent dynamic nonlinearity, and aperture jitter. The distributed time skew problem of quantization is alleviated as a result of the usage of the front-end S/H
circuit. For gigahertz sampling rate operation, S/H becomes essential to achieve the desired converter resolution with wide input bandwidth.
Closed loop configuration provides good linearity and dynamic range but cannot achieve very high speeds. In order to operate at high speed, the S/H has to be a simple open-loop configuration. The basic S/H configuration shown in Figure 3.2 consists mainly of a sampling switch and a holding capacitor [3]. This single ended configuration makes it possible to design for very high speed, but it has signal-dependent charge injection and clock feedthrough.
Figure 3. 2 Basic S/H Configuration
The pseudo-differential type S/H configuration shown in Figure 3.3 is the best choice to solve signal-dependent charge injection and clock feedthrough. This type S/H consists of sampling switches, dummy switches, holding capacitors, and unity gain buffers. The dummy switches are driven by reverse of the clock signal and they are used to reduce the effect of signal-dependent charge injection and clock feedthrough released from the sampling switches [2]. The holding capacitors are made large enough to overcome the gate capacitance variation of the MOSFET. The buffer is made by PMOS whose bulk is connected to its source to suppress the body effect.
Figure 3. 3 Pseudo-Differential Type S/H Configuration
In Figure 3.3, the constant current source follower is the simplest realization of a unity gain buffer. But, it still has limitation and drawback. When the input to the buffer is fast and has large amplitude, the skew rate at the output of the circuit is limited. Thus, its speed can not be linearly improved by increasing the bias current. Although we can suppress the body effect by connecting its bulk to source, its gain still can not reach real unity. Due to the finite output resistance, its gain can only approximate 0.9. The buffer with this gain will degrades the amplitude of output signal when input frequency is very high. So, adding a PMOS loading to increase output resistance can make the gain approximates unity.
Figure 3. 4 The first cross-coupling type S/H Configuration with a PMOS Loading
Figure 3. 5 The second cross-coupling type S/H Configuration with a PMOS Loading
There are two cross-coupling types of the S/H configuration and their gain can achieve unity. The first cross-coupling type is shown in Figure 3.4 and second cross-coupling type is shown in Figure 3.5. The gain of the first cross-coupling type S/H configuration is given by (detailed analysis is shown in Appendix):
1
and its 3db frequency is given by (detailed analysis is shown in Appendix):)
The gain of the second cross-coupling type S/H configuration is given by (detailed analysis is shown in Appendix): and its 3db frequency is given by (detailed analysis is shown in Appendix):)
Give a sinusoidal input waveform with amplitude A and radian frequencyω
and assumeunity gain buffer is one pole transfer function as follows:
unity gain buffer is one pole transfer function as follows: