Digital Audio

Modern wireless systems, such as cellular telephone, use low pass filter, high resolution A/D converters, digital signal processor (DSP) and high resolution D/A converters. The modern cell phone handset block is shown in Figure 2.9.When we speak to other person with cell phone, the low pass filter remove noise from voice, A/D converter transform voice into digital signal and then the digital signal is dealt with DSP. Modern cellular transmission systems make use of DSP-based speech compression algorithms in order to reduce the overall data rate to acceptable levels, rather than limiting the resolution of the converters. Digital audio systems place high resolution demands on A/D converters and D/A converters because of the wide dynamic range requirements. The digital audio signal may then be stored or transmitted. Digital audio storage can be on a flash memory, or any other digital data storage device. Audio data compression techniques — such as MP3— are commonly employed to reduce the size. Digital audio can be streamed to other devices. The last step for digital audio

is to be converted back to an analog signal with a D/A converter.

Figure 2. 9 Modern Cell Phone Handset block

CHAPTER 3

Low-Power High-Speed Techniques and Circuit Design

In this chapter, the low-power high-speed architecture is proposed to reduce the input capacitance, offset errors, power dissipation, bubble errors and metastability errors by using sample-and-hold, interpolation, averaging and digital error correction techniques. With the architecture, the dynamic performance is improved, the input capacitance is reduced, 83%

power saving in preamplifiers is achieved and the power of (2ⁿ-1)m pipeline latches is removed.

The circuit design and related issues will be discussed in detail. The required resolution is 6 bits and the sampling rate is 2GHz. As the result, circuit design plays an important role to achieve the specifications. The block diagram of the proposed A/D converter is shown in Figure 3.1. The proposed A/D converter consists of analog part and digital part. The analog part consists of sample-and-hold, resistor ladder, interpolation preamplifiers, comparators and resistive averaging. The digital part consists of auxiliary circuit, AND gates, ROM, TSPC, Gray-to-binary decoder, clock generator and output buffer. The design issues of each component are discussed step by step. Finally, the static and dynamic performances simulation results are presented in the last section.

Figure 3. 1 Block diagram of the proposed low power A/D converter

3.1 Sample-and-Hold Technique

The purpose of the sample-and-hold (S/H) circuit is to track and hold the input signal long enough for the A/D converter to complete a conversion without appreciable error. The S/H circuit is a crucial part, especially for high speed sampling rates. To improve the dynamic performance of the A/D converter, a S/H circuit can be put in front of the converter. By holding the analog sample static during digitization, the S/H largely removes errors due to skews in clock delivery to a large number of comparators, limited input bandwidth prior to latch regeneration, signal-dependent dynamic nonlinearity, and aperture jitter. The distributed time skew problem of quantization is alleviated as a result of the usage of the front-end S/H

circuit. For gigahertz sampling rate operation, S/H becomes essential to achieve the desired converter resolution with wide input bandwidth.

Closed loop configuration provides good linearity and dynamic range but cannot achieve very high speeds. In order to operate at high speed, the S/H has to be a simple open-loop configuration. The basic S/H configuration shown in Figure 3.2 consists mainly of a sampling switch and a holding capacitor [3]. This single ended configuration makes it possible to design for very high speed, but it has signal-dependent charge injection and clock feedthrough.

Figure 3. 2 Basic S/H Configuration

The pseudo-differential type S/H configuration shown in Figure 3.3 is the best choice to solve signal-dependent charge injection and clock feedthrough. This type S/H consists of sampling switches, dummy switches, holding capacitors, and unity gain buffers. The dummy switches are driven by reverse of the clock signal and they are used to reduce the effect of signal-dependent charge injection and clock feedthrough released from the sampling switches [2]. The holding capacitors are made large enough to overcome the gate capacitance variation of the MOSFET. The buffer is made by PMOS whose bulk is connected to its source to suppress the body effect.

Figure 3. 3 Pseudo-Differential Type S/H Configuration

In Figure 3.3, the constant current source follower is the simplest realization of a unity gain buffer. But, it still has limitation and drawback. When the input to the buffer is fast and has large amplitude, the skew rate at the output of the circuit is limited. Thus, its speed can not be linearly improved by increasing the bias current. Although we can suppress the body effect by connecting its bulk to source, its gain still can not reach real unity. Due to the finite output resistance, its gain can only approximate 0.9. The buffer with this gain will degrades the amplitude of output signal when input frequency is very high. So, adding a PMOS loading to increase output resistance can make the gain approximates unity.

Figure 3. 4 The first cross-coupling type S/H Configuration with a PMOS Loading

Figure 3. 5 The second cross-coupling type S/H Configuration with a PMOS Loading

There are two cross-coupling types of the S/H configuration and their gain can achieve unity. The first cross-coupling type is shown in Figure 3.4 and second cross-coupling type is shown in Figure 3.5. The gain of the first cross-coupling type S/H configuration is given by (detailed analysis is shown in Appendix):

1

and its 3db frequency is given by (detailed analysis is shown in Appendix):

)

The gain of the second cross-coupling type S/H configuration is given by (detailed analysis is shown in Appendix): and its 3db frequency is given by (detailed analysis is shown in Appendix):

)

Give a sinusoidal input waveform with amplitude A and radian frequency

ω

and assume

unity gain buffer is one pole transfer function as follows: If the tolerable output amplitude error is lower than 2% (6 bits accuracy), we have

02

The simulation of the first and second cross-coupling type S/H configuration is shown in Figure 3.6. From this figure, the gain of the first cross-coupling type S/H configuration approximates unity and its 3db frequency is 5.33GHz. The gain of the second cross-coupling type S/H configuration is larger than unity and its 3db frequency is 2.39GHz. From equation (3.6), the buffer 3db frequency must be high than 4.926GHz. Thus, the first cross-coupling type S/H configuration fits the design requirement and the 3db frequency is 5.33GHz. The proposed design can achieve the wide bandwidth to get high dynamic performance.

3.2 Interpolation Technique

It is needless to say that the number of elements and the power dissipation increase exponentially to the resolution of flash A/D converter. The flash A/D converter architecture is considered to realize the highest conversion frequency, however, it suffers from not only large chip size and large power dissipation, but also lower dynamic performance due to large input capacitance [10]. Hence, some circuit techniques that can reduce the element count are required. Interpolation technique is the good solution to solve these problems. The interpolation architecture of preamplifier is shown in Figure 3.7. △V1(=Vy1-Vx1), △ V2(=Vy2-Vx2), △V(=Vy2-Vx1) are the outputs of the preamplifiers, Vin is the input voltage and Vr1, Vr2, Vr are the reference voltages.

Figure 3. 7 Interpolation Preamplifier Architecture

Interpolation allows the generation of intermediate voltages, so that the input voltage does not need to be compared to 63 distinct reference voltages at the front-end of a flash A/D converter. Each input to reference voltage comparison at the front-end would require its own preamplifier, consuming an unacceptable amount of power and area. Virtual zero crossing

points shown in Figure 3.8, which are not the result of the input crossing a physical reference voltage, are created through interpolation at amplification stage. In other words, in this scheme a zero crossing is obtained by interpolating between two reference levels.

Performance indices of the preamplifier such as input common-mode range, input capacitance, power dissipation, overdrive recovery speed, voltage gain, and capacitive feedthrough to the reference resistor ladder often place tight requirements on the preamplifier. Thus, using interpolation to reduce the number of preamplifiers relaxes its design requirements and can improve the differential nonlinearity [11].

However, there are some design conditions which need to be considered. Interpolation is only between close-enough preamplifier outputs to avoid non-linear zero crossing. The size of the input transistors of the preamplifier needs to be increased. Larger size can reduce the offset from the preamplifier itself. The gain of the preamplifier needs to be tuned well. Small gain of the preamplifier can not overcome the offset from comparator, but large gain of the preamplifier can cause no gain error at zero crossing shown in Figure 3.9. If no gain error at zero crossing happens, the preamplifier can not reduce the offset from the comparator. The only adequate gain of the preamplifier can generate the good zero crossing shown in Figure 3.8.

Figure 3. 8 Good Zero Crossing

Figure 3. 9 No Gain Error at Zero Crossing

3.3 Averaging Technique

High speed flash A/D Converter with medium resolution usually employs differential pairs as pre-amplifying stages before the comparators. Their offset voltages are the ultimate limitation to the linearity that may be achieved by the A/D converter. Increasing the area of the components in the differential pairs reduces offset voltages , but increases parasitic capacitances, leading to a large power dissipation, large die size and large input capacitance or to the reduction of the maximum operating frequency [12].

To partially overcome this problem an averaging scheme will be introduced. This averaging scheme uses the outputs of more active input pairs to increase the effective gate area and in this way reduce the offset voltages. The figure 3.10 shows five differential preamplifiers with load resistor R0 as part of the input preamplifier chain used in flash A/D converter. Averaging is obtained by coupling the outputs of the differential preamplifiers via averaging resistor R1. This averaging resistor chain continues to couple more input stages. As long as the input preamplifiers are active and operate in the linear signal range, then the

output signal of these active preamplifiers contribute via the averaging resistors to the signal of a differential preamplifier operating around the zero crossing level. Here preamplifier (n=0) is supposed to be the zero crossing preamplifier. The output signals from the left neighbors of the zero crossing preamplifier influence the zero crossing. The same effect is obtained from the right neighbors. As long as the neighboring preamplifiers are in the linear region it looks like that the zero crossing amplifier consists of a much bigger device with a size equal to the sum of the areas of the active linear amplifiers [3].

By adding resistors R1, not only the offset error (noise) is reduced but also the gain of the preamplifier (signal) is loss. In order to reduce the effective gain of error but one of the signal is maintained, the resistive ratio of R1/R0 have to be choice properly to perform optimum.

Figure 3. 10 Resistive Averaging Scheme and Zero Crossing

3.3.1 Spatial Filtering of the Averaging Resistive

Network

The averaging requires the summation of quantities spread into two or more samples in either time or space. In the MOSFET example, the parallel connection spreads the noisy charges. Similarly in the preamp array of a flash A/D converter the output current spreads through the lateral connections in the averaging resistor network. Summation is automatic when physical quantities such as currents and charges merge at a node in accordance with Kirchhoff’s laws.

The impulse response of the spreading network, which forms a spatial filter, characterizes the extent of spreading. Usually the wider the impulse response will get the higher the SNR. However, there are limits to this in uses such as offset averaging, where a wider impulse response also filters out signal. To correctly optimize the SNR, the properties of both signal and noise must be taken into account to find the best impulse response

Figure 3. 11 The impulse Response of a resistor network as spatial filter

The impulse response, h(n), of the spatial filter is found by injecting a unit stimulus current at one node, and noting the resulting distribution of current in each R0 at other nodes as shown in Figure 3.11. For a stimulus current injected to an arbitrary node n, Kirchhoff’s current law (KCL) requires that

i

in

where the third and fourth terms are the currents flowing into node n from node (n-1) and (n+1), respectively. Using the transform simplifies analysis. Applying the z transform to (3.7)

1 The inverse transform H(z) of yields the spatial impulse response [13]

b

n

h n

h ( ) = ( 0 )

_{, where}

b = e

^{−acosh(1+R1/2R0)}

< 1

(3.9) h (0) is a normalized coefficient. Uniform current division in the R0- R1 network leads to an impulse response that decays exponentially in n. The width of the impulse response can be controlled by the ratio of R1/R0 as shown in Figure 3.12. The impulse response acts as a low pass filter in spatial domain and the width of impulse response will influence the averaging effect. The smaller ratio of R1/R0 generates wider width of the impulse response to get effective averaging and then the larger ratio of R1/R0 generates narrower width of the impulse response to get poor averaging.

Figure 3. 12 Impulse response as a function of resistive ratio R1/R0 at node(0)

3.3.2 Error Correction Factor (ECF)

The parameter used to the averaging performance is error correction factor (ECF) [13].

The error correction factor is defined as ratio standard deviation of the original offsets and standard deviation of the input-referred offsets after averaging. Thus

)

input referred offset voltage, offset current and transconductance of the preamplifier before (after) averaging at the zero crossing node. Now let us derive the ECF for a spatial filter with the impulse response given by equation (3.9). Since the output of any filter is found by convolving its input with the impulse response, we have

∑

Where is the width of linear active region of the preamplifier which can be expressed as which leads to the standard deviation

∑

⁻ Where is the width of noise window of the preamplifier. Combining Equation (3.10), (3.11), (3.12) and (3.13), the ECF can be shown that

W

n

)

Figure 3.13 shows the error correction factor (ECF) respects to resistive ratio R1/R0. How accurate must be the ratio of R1/R0 to deliver near optimum benefits? The ratio is chosen larger than at the maximum point to prevent the gain loss. The resistive network causes the gain loss of the preamplifier as shown in Figure 3.14. The value of ECF will be higher if the value of R1/R0 is lower, but it also causes the gain loss of the preamplifier when the value of R1/R0 is lower. For example, if the ratio falls by 50% to 0.08, the ECF increases from 3.2 to 3.7 but gain loss increases from 3% to 11%. If rises by 50% to 0.24, the ECF also falls to 2.8 but gain loss approaches zero. Thus, a network with only roughly the right resistor ratio should yield close to optimum averaging. Consider =35 and choose a ratio R1/R0=0.16 in our design. From the figure 3.13 and figure 3.14, the ECF is about 3.2 and the gain loss is only within 3% when the resistive ratio 0.16 is chosen.

WZX

Figure 3. 13 The error correction factor verse resistive averaging ratio

Figure 3. 14 Gain loss verse resistive averaging ratio

Figure 3. 15 Monte-Carlo simulation setup scheme

Figure 3. 16 The preamplifier Monte-Carlo analysis with and without averaging resistor Monte-Carlo analysis is performed to verify the benefits of resistive averaging. Figure 3.15 shows the Monte-Carlo simulation setup scheme. The parameters for the device mismatch including threshold voltage mismatch and resistor mismatch are provided by foundry []. In the idea case with no transistor mismatch, the comparator output changes polarity when a slow ramp input cross the corresponding threshold. Figure 3.16 shows that the time the comparator changes polarity is randomly dispersed with respect to when the input cross zero. The preamplifier offset set voltage is 12mV when the preamplifier without averaging resistor.

Using averaging resistor, the preamplifier offset reduce to 4.1mV. The simulation result is shown in Figure3.16; it is a composite plot of 60 Monte-Carlo transient analyses.

3.3.3 Nonlinearity Error and Compensation at the Edges

Finiteness of the array of preamplifiers poses unique problems at the edges of an

averaging flash A/D converter. Usually the preamplifier array comes to an end at the upper and lower limits of the analog full scale. This will disrupt averaging at the last few preamplifiers, because at the extreme nodes there is no longer an equal number of stimuli into the resistor network from both left and right. As shown in Figure 3.17 the vertical line that crosses the zero-crossing point at the right-hand extreme of full scale intercepts zero-crossings only in the upper half plane if there are no dummy zero-crossings. In presence of the lateral resistors, those intercept points contribute positive currents to the zero-crossing node and effectively pull the zero-crossing toward the center of the array. Unless the positive intercept points are balanced with negative ones from dummies or by distorting reference taps, all the zero-crossings within the range of half width of impulse response at each edge are pulled resulting a systematic INL curvature.

Figure 3. 17 Dummy preamplifiers to reduce edge effects

Linearity across the full scale requires that no distortion should build up at the edges. A straightforward solution is to add preamplifiers on either edge of the array to extend the averaging network by at least width of the impulse response, the extent of the interaction range [13]. Therefore, half number of dummy preamplifiers is attached at each end. The current flowing in averaging resistor shows a large bending at both ends, as shown in Figure 3.18

Figure 3. 18 The current flowing in resistive network shows the boundary condition

Figure 3. 19 Dummy preamplifiers with cross connection averaging

Figure 3. 20 Impulse response as a function of resistive ratio R1/R0=0.16 at node(0) This bending is of a form as the low-to-high current in the lowest edge and the high-to-low current decreasing in the highest edge, causing the INL pattern at edge to go opposite direction. In order to keep the symmetry condition at the edge of preamplifiers, the dummy preamplifiers are added and the cross connection averaging resistor is adopted which is shown is Figure 3.19. The numbers of dummy preamplifiers are probably equal to the range of impulse response which is shown in Figure 3.20. In this design the range of impulse response of the averaging networking is about 16 dummy preamplifiers are enough to compensate the integral nonlinearity errors at the boundary condition. Figure 3.21 shows the simulation at the boundary condition with and without the dummy preamplifiers.

Figure 3. 21 Averaging current following in the load resistance

From this figure, the nonlinearity error is serous obviously at the edge of preamplifiers and the linearity range is extended with proper dummy preamplifiers at the boundary of preamplifiers array.

3.3.4 Power Saving in Preamplifiers Array

Averaging resistors are used in both preamplifiers and comparators in order to reduce the input referred offset. For unaveraged preamplifier, the standard deviation of input referred offset σ(ΔVos) is inverse proportional to the square root of the size (WL) of the input differential pair [14] as derived in Equation 3.11. With averaging resistors, the offset can be reduced by κ times. Therefore, for the same offset specification, the size of each preamplifier can be reduced κ² times compared with unaveraged one.

V WL

With the same preamplifier speed, overdrive condition and input-referred RMS offsets, the

With the same preamplifier speed, overdrive condition and input-referred RMS offsets, the

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