CHAPTER 2 REVIEW OF A/D CONVERTER ARCHITECTURES AND APPLICATIONS
2.1 A/D C ONVERTER A RCHITECTURES
A variety of A/D converters exist on the market today, with differing resolutions, bandwidths, accuracies, architectures, packaging, power requirements, and temperature ranges, as well as specifications, covering a broad range of performance needs. And indeed, there exists a variety of applications in data acquisition, communications, instrumentation, digital audio, and interfacing for signal processing, all having different requirements. Considering architectures, for some applications just about any architecture could work well; for others, there is a best choice. In some cases the choice is simple because there is a clear-cut advantage to using one architecture over another, but in some cases the choice is more subtle.
For example, flash A/D converters are most popular for applications requiring a throughput
rate of more than 1 GSPS with low resolution. Sigma delta converters are usually the best choice when very high resolution (20 bits or more) is needed. The differences in their architectures make one or the other a better choice, depending on the application. Among the variety of A/D converter architectures, the most popular presently used are flash A/D converter, pipelined A/D converter, and sigma-delta A/D converter [5][6]. In the following sections, these popular A/D converter architectures are briefly described.
2.1.1 Flash A/D Converter
The flash A/D converter architecture, also known as a fully parallel architecture, is fundamentally the fastest architecture. This architecture is conceptually the easiest to understand. An n-bit flash A/D converter consists of an array of 2n-1 comparators and a set of 2n -1 reference values, shown in Figure 2.1. Each of the comparators samples the input signal and compares the signal to one of the reference values. Each comparator then generates an output indicating whether the input signal is larger or smaller than the reference assigned to that comparator. The differences between the input and reference values are amplified to digital levels and generate thermometer code. The encoder converts the thermometer code produced by the comparators to a binary code. As seen from the figure, the comparators all operate in parallel. Thus, the conversion speed is limited only by the speed of the comparator.
For this reason, the flash A/D converter is capable of high speed and it is used for high-speed applications such as wireless receiver, digital oscilloscopes, high-density disk drives, and so on.
Figure 2. 1 Flash A/D Converter Architecture
The primary drawbacks to the flash A/D converter are the large hardware requirement and sensitivity to comparator offsets. As mentioned earlier, 2n-1 comparators are required. For example, a 6-bits flash A/D converter needs 63 comparators, but 10-bits flash A/D converter needs 1023 comparators. For this reason, a high resolution flash A/D converter requires a large circuit area and dissipates high power. Furthermore, the large number of comparators present a large capacitance to the output of the sampling circuit. The required comparator offset voltage for a flash A/D converter with n bit resolution is less than 1/2n. At high resolutions, this required comparator offset becomes very small. Because comparators with small offsets are difficult to design and expensive to build and because so many comparators are required, A/D converters with resolutions higher than 8 bits rarely use the flash architecture.
2.1.2 Pipelined A/D Converter
The pipelined architecture effectively overcomes the limitations of the flash architecture.
A pipelined converter divides the conversion task into several consecutive stages. Pipelining enables potentially faster conversion while avoiding the exponential growth of power and hardware. Figure 2.2 illustrates the block diagram of a pipelined A/D converter. The analog input is applied to the first stage in the chain, and N1 bits are detected. The analog residue is also generated and applied to the next stage. The same procedure repeats up to the end of the chain. This concept is similar to the idea of an assembly line because the interstage sampling allows all of the stages to operate concurrently. A common approach to pipelining is based on a precision multiply-by-two stage that merges most of the interstage operations into a compact circuit. Usually used with 0.5 bits of overlap, this technique provides a modular implementation.
Figure 2. 2 Pipelined A/D Converter Architecture
The pipelined architecture offers a number of advantages. First, the throughput rate is determined by the speed of only one stage in the pipeline. Second, interstage residue
amplification relaxes the precision required of subsequent stages. Third, the power and hardware of pipelined converters grow almost linearly with the number of bits. Also, overlap and digital correction can be used to allow large offsets in the comparators.
The primary drawback of the conventional pipelined topology is the need for high precision in the interstage SHAs, D/A converters, and subtractors, especially at the front end.
The precision typically mandates the use of op amps, imposing severe trade-offs among speed, voltage swing, gain, and power dissipation. As device dimensions, supply voltages, and the intrinsic gain (gm
r
o) of MOSFETs continue to scale down, the design of op amps becomes increasingly more difficult.2.1.3 Sigma-Delta A/D Converter
The sigma-delta architecture takes a fundamentally different approach than those outlined above. In its most basic form, a sigma delta converter consists of an integrator, a comparator, and a single bit D/A converter, as shown in Figure 2.3. The output of the D/A converter is subtracted from the input signal. The resulting signal is then integrated, and the integrator output voltage is converted to a single-bit digital output (1 or 0) by the comparator.
The resulting bit becomes the input to the D/A converter, and the output of the D/A converter’s is subtracted from the A/D converter input signal, etc. This closed-loop process is carried out at a very high “oversampled” rate. The digital data coming from the A/D converter is a stream of “ones” and “zeros,” and the value of the signal is proportional to the density of digital “ones” coming from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output.
Figure 2. 3 Sigma-Delta A/D Converter Architecture
One of the most advantageous features of the sigma-delta architecture is the capability of noise shaping, a phenomenon by which much of the low-frequency noise is effectively pushed up to higher frequencies and out of the band of interest. As a result, the sigma-delta architecture has been very popular for designing low- bandwidth high-resolution A/D converters for precision measurement. Also, since the input is sampled at a high
“oversampled” rate, unlike the other architectures, the requirement for external anti-alias filtering is greatly relaxed. A limitation of this architecture is its latency, which is substantially greater than that of the other types. Because of oversampling and latency, sigma-delta converters are not often used in multiplexed signal applications. To avoid interference between multiplexed signals, a delay at least equal to the decimator’s total delay must occur between conversions. These characteristics can be improved in sophisticated sigma-delta A/D converter designs by using multiple integrator stages and/or multi-bit D/A converters.
2.1.4 Summary of A/D converter Architectures
The most popular A/D converter architectures have been reviewed in the previous sections. The flash A/D converter architecture is the fastest, the Sigma-Delta A/D converter is very useful for high-resolution applications, and the pipelined A/D converter can be applied
for various applications. Each A/D converter architecture has tradeoffs among speed, resolution, and power dissipation. In summary, Table 2.1 provides the characteristics of popular A/D converter architectures [7]. In the third column, “sps” stands for samples per second. The “m” shown in the fourth column is the number of stages in the pipeline architecture.
Architecture Resolution (bits)
Speed (sps)
Latency (cycle)
Comments
Flash < 10 250M ~ 2G 1 -high input bandwidth -highest power dissipation -large die size
Pipeline 8 ~ 16 1M ~ 200M m -high throughput rate -low-power dissipation -on-chip self calibration Sigma-Delta > 14 > 200K large -high resolution
-limited sampling rates -digital on-chip filtering Table 2. 1 Summary of A/D converter architectures