Chapter 2 DC-offset Issue in RF Receiver
2.5 Summary
DC-offset issue is the most serious issue in direct-conversion receiver. Due to the frequency planning, this issue is slightly in heterodyne receiver and low-IF receiver.
From Fig. 2.5, the harmonic mixer which is free from DC-offset issue seems to be one of solution for direct-conversion to overcome DC-offset. With this faith, the research will focus on direct-conversion harmonic mixer.
Fig. 2.1 Direct conversion receiver architecture
ω
RFω
LO= ω
RFω
BB= 0
Fig. 2.2 Frequency conversion of direct conversion receiver
LO
t ω cos
LO
t ω cos
Fig. 2.3 Self-mixing of (a) LO signal, (b) a strong interferer
AMP
LO Signal
DC Offset
LO Leakage Reflected LO Signal
Reverse Isolation Amplified
AMP
LO Signal
DC Offset
LO Leakage Reflected LO Signal
Reverse
Isolation
Amplified
RF
Fig. 2.5 DC-Offset issue of (a) the conventional mixer (b) the second harmonic mixer
fRF
Fig. 2.6 Work principle of harmonic mixer
0
t cos ω
Fig. 2.7 DC-Offset compensation
Fig. 2.8 Heterodyne receiver
ω
RF ωIMω
IFω
IFω
IFω
LOω
LOLO IM
RF LO IF
ω ω
ω ω ω
−
=
−
=
ω
ω
Fig. 2.9 Frequency planning
Fig. 2.10 Feedthrough caused by substrate loss
≠0 f
RF LO f f ≠
Fig. 2.11 Low IF receiver
f
RFf =
RF LO
f
f =
f
RFf
LOf
LOf = 0
= 0 f
f
IFFig. 2.12 DC-offset issue of (a) direct conversion receiver (b) low IF receiver
Fig. 2.13 A 900MHz balanced harmonic mixer
Fig. 2.14 A 2GHz even harmonic mixer
Chapter 3
A 5.2GHz Direct-Conversion Step-Gain Harmonic Mixer
3.1 Motivation
We have introduced the DC-offset issue in direct-conversion receiver in section 2.1.1. From section 2.1.3 and Fig. 2.5, they show that the LO self-mixing problem in the direct-conversion receiver arises due to the situation that the LO signal resides at the same frequency as the RF signal. As DC-offset can’t be easily filtered out without removing any base-band signal because most modulation schemes contain significant DC and low frequency components. In section 2.1.3, it also shows that the harmonic mixer architecture resolves the DC-offset issue which the LO frequency is just at the half of RF frequency. This architecture is the most suitable solution of DC-offset issue because of needing no compensation circuits. In this chap, a harmonic mixer with step-gain function is introduced and implemented in 0.18 m CMOS process.
3.2 Analysis of the Step-Gain Harmonic Mixer
The CMOS step-gain harmonic mixer is shown in Fig. 3.1 This harmonic mixer
is composed of three parts: (1). harmonic generation stage; (2). mixing stage and
injection current source, and (3). gain tuning stage.
3.2.1 Harmonic Generation Stage
The harmonic generation stage consists of transistors MLO+ and MLO-. The
second harmonic is obtained by the inherent square-law operation of the transistor.
Each NMOS I/V curve can be shown as power series:
16
Equation (3.4) shows that in drain combined point of transistors MLO+ and MLO- .
The odd harmonic of both transistors is canceling because of the differential signal
input. In reference paper [6], both transistors are operating in saturation region.
Equation (3.4) can be rearranged to be a square-law equation:
)
where
L C W K =µn OX .
As Vg is the gate bias of both transistor, Vt is the threshold voltage, µn is the
mobility of NMOS, C is the gate capacitance and W/L is the width/length ratio of OX
the transistor.
In short channel devices, square-law operation is weakened due to velocity
saturation phenomenon.
In long channel devices (without velocity saturation):
( )
2In short channel devices (with velocity saturation):
( )
2(3.11)
As equation (3.8), the gm’ is equal to a2 in power series. In long channel device, the
square characteristic lets the a2 as a constant. In short channel device, assume the velocity saturation is large, the
L
the gm’ in equation (3.11) is zero. That means the I/V curve is linear, and the second
harmonic is unapparent.
To generate higher second harmonic component level, a current source and a
capacitor are connected to both MLO+ and MLO- transistor’s source terminals. Both
transistors operate as switches and capacitor bypass the even order harmonics. In this
operation point, the second harmonic level would be enhanced greatly.
Fig. 3.2 shows the 2nd harmonic/DC ratio curve of MOS. The dot line is the MOS
which is working in saturation region and solid line is the proposed swich-like CMOS
pair. The dot line in Fig. 3.2 shows that 2nd harmonic is degraded with Vgs and the
proposed harmonic generation generates larger 2nd harmonic than former. It also
shows that the 2nd harmonic is large in low Vgs voltage. To consider the biasing
condition of Fig. 3.3 (a), if the Vgs is biased in low voltage such as 0.6V in 0.18um
process, with the injection of large LO power, the Vgs is swing with LO voltage. The
2nd harmonic is not a constant, and is low when effective Vgs is large. This is because
that the source of MOS pair is connected to ground and Vgs is decided by gate
voltage of MOS. To solve this issue, a proposed solution is brought out as Fig 3.3 (b).
A current source is connected between common source point and ground. With
floating Vs, the overdrive of Vgs is a constant and Vs is swing with Vg. By adjust
current source, a proper Vgs is chosen for high 2nd harmonic/DC ratio. In
consideration of odd harmonics of LO, the common source point is virtual ground. In
consideration of even harmonics, the common source is high resistance. This will
degrade the 2nd harmonic as source degeneration. By connected a bypass capacitance,
the source degeneration is cancelled and the 2nd harmonic will be enhanced.
Above all, the harmonic generation stage is actually a squaring cell which
converts the differential LO voltage to the time-varying current which contains the
second harmonic. The fundamental and all odd harmonics of the MLO+ and MLO- drain
current are cancelled at the connected drain terminal. Fig. 3.4 shows both MLO+ and
MLO- transistor’s drain current and the total current Ihar at the connected point.
3.2.1.1 Define Harmonic/DC Ratio
For quantifying the second harmonic enhancement, we define a harmonic/DC
ratio R.
DC thHarmonic
I
R= I2 (3.12)
In the same biasing current, operating both MLO+ and MLO- in saturation region
the harmonic/DC ratio is about 10%. In this work, operating both MLO+ and MLO- in
switch-like operation point, the harmonic/DC ratio is 34%. It is three times more than
former one. The conversion gain will increase greatly with this scheme.
3.2.2 Mixing Stage
In the mixing stage, the differential radio frequency (RF) signal from gate of
MRF+ and MRF- and the second harmonic from both sourcesare mixed and the RF
signal is down-converted to base-band. In noise analysis, the flicker noise of MRF+ and
MRF- dominate the output noise power level. From flicker noise equation
WLC f
Where K is a device-specific constant, f is the frequency, g is the m
trans-conductance of transistor, W/L is transistor’s width/length, C is the gate OX
capacitance, ωt is the cut-off frequency, A is the gate area of transistor and I is the
DC current of the transistor.
In equation (3.15), it shows that the flicker noise current of transistor is direct
proportion to DC current and the inverse of the square of length. Increasing the
transistor length and decreasing the bias current of transistor decreases flicker noise.
Because that noise figure inverses to conversion gain, the transistor length must be
optimized for noise performance. In this work, the length is increase to 0.35 m for
decreasing flicker noise.
The purpose of the injected current is to reduce the biasing current of MRF+ and
MRF-. In equation (3.15), it reduces the flicker noise of the transistor pair MRF+ and
MRF-, which is the main noise contributor. The injected current itself will not
introduce noise in this balanced structure. Unlike the Gilbert-Cell mixer, the two RF
transistors change their current simultaneously and any noise at their common source
node will be completely cancelled out at the differential output.
At the same time, the RL can be increased to raise the mixer conversion gain but
not influences output third order inter-modulation interrupt point (OIP3) too much.
3.2.3 Gain Tuning Stage
In the gain tuning stage, the second harmonic current flows through the peaking
inductor and the parallel NMOS switch MSW . Reference papers [8] [9] introduce the
inductive peaking LNA architecture with high gain benefit.
In this stage, inductive peaking architecture is adopted for higher second
harmonic level, and with a parallel switch for gain tuning. As NMOS switch turn off
(VSW is connected to ground), the peaking inductor and loading from the other two
stages form a third-order filter with peaking effect as shown in Fig. 3.5 (a):
G
Where CL is the effective load capacitance looking into the harmonic stage, and CP /G
are the effective load capacitance/ admittance looking into the mixing stage. Fig. 3.6
shows the current flowing to mixing stage is amplified by inductive peaking. The
peaking frequency is in 5.2GHz and it means the second harmonic signal at 5.2GHz is
peaked up maximum when it flows across this stage. In this condition, it’s called that
mixer is operating in the high-gain mode. In the high-gain mode, the third-order filter
peaking at 5.2GHz makes the frequency response sharper and filters out the higher
order harmonics which degrade the output spectra.
As NMOS switch is turn on, the peaking inductor parallel with a small turn-on
resistance as showed in Fig. 3.5 (b).
G
third-order filter turns into a first-order low pass filter (LPF) with a pole at frequency
) (
2 CP CP freq G
= π + , and suppress the second harmonic. It seems that the inductance peaking effect is eliminated by the small resistance. The simulation result of turn-on
MSW is showed in Fig. 3.6. The second harmonic will not be peaked across this stage.
In this operating condition, the harmonic mixer is working in the low-gain mode.
With the inductance peaking scheme and a parallel switch, the gain tuning stage
provides two gain modes in this work. This will ensure the mixer to operate in larger
input dynamic range.
3.2.3.1 Quantify the Step Gain
In chapter 3.2.1.2, we define the harmonic/DC ratio. As equation (3.12), this
ratio is direct proportion to conversion gain. In gain tuning stage, the gain step is
associated with the ratio. With MOS switch turn-on, the second harmonic is
suppressed by low-pass filter and the ratio is around 34%. In the other condition, pass
though the third order low-pass filter with peaking, the second harmonic is amplified
and the ratio is around 96%. This is nearly 2.8 times than former. Assume the
impedance looking into mixing stage is constant, the voltage sweep ratio is equal to
current sweep ratio. Then the gain step is:
)
3.3 Discussion on Simulation and Measurement Result
This section lists the simulation and measure result of the step-gain harmonic mixer. The simulation is done by Agilent advanced Design System (ADS) and post simulation by ADS Momentum.
3.3.1 Measurement Consideration
The measurement of this chip is a question. With the restriction of measurement instruments, some of the data of measure results must be got indirectly. The first is consideration is that while RF signal transfers to base-band, the down-conversion mixer is high impedance in base-band output. Because the base-band circuit such as analog-to-digital converter (ADC) or variable gain amplifier (VGA) is high input impedance, the output of mixer could be design in high impedance for larger conversion gain.
There is a question: the input impedance of the measure instruments is 50 Is it influences the measure results of device-under-test (DUT)? In AC consideration, the large output resistance is parallel with 50 , and the effective loading is dominates by instrument loading. It influences the DUT performance greatly.
For measuring the DUT without degrading it, output buffer is added between DUT and instrument. One way is added buffer circuit such as common drain transistor and implements on-chip. Shown in Fig. 3.7, the buffer circuit consuming large current and the input capacitor degrade the DUT input matching greatly by miller-effect. The following question is how to de-embed the testing circuit without adding another buffer circuit?
The measurement way of this chip is added a unit-gain buffer amplifier between DUT and instrument, shown in Fig. 3.8. Because that the DUT output is differential end, a differential-to-single end unit-gain buffer is adopted. Trading off between influence to DUT and thermal noise of resistor, the 8.2K resistor for differential amplifier is adopted. The output of amplifier is series with 49.9 for
of the DUT and the measurement result is the point B. The power difference of point A and B is 6dB and we could get the real output results by measurement results.
3.3.2 Chip Implementation
Fig. 3.9 shows the microphotograph of the step-gain harmonic mixer circuit.
The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area
including bonding pads is 0.906 mm by 0.508 mm. Careful layout is observed in order
to maximize performance. The layout is done in a uni-directional fashion, i.e. no
signal returns close to it origins, to avoid coupling back to the input. For the layout
consideration, the RF-LO ports isolation is the first consideration and places these
ports opposite of the chip to improve port-to-port isolation and enhance DC-offset
cancellation scheme. The RF port, which the signal level is less than LO port, crosses
the IF port vertically and decreases the overlap area to minimize the couple of both
ports. The layout is placed symmetrically to minimize the mismatch of the differential
signal. In order to minimize the effect of substrate noise on the system, a solid ground
plane, constructed using a low resistive metal-1 material, is placed between the signal
pads (metal-6 and metal-5) and the substrate.
3.3.3 Simulation and Measurement Result
The simulation and measure result is listed in TABLE I. Though the DC current is 2.2mA, similar to simulation, the conversion gain is -5dB in high gain mode (HGM) and -6.5dB in low gain mode (LGM) which is 23dB and 15dB lower than simulation result in HGM and LGM. The conversion gain and IIP3 are shown in Fig. 3.10 and Fig.3.11. Because of the conversion gain is lower than expect, the IIP3 is large than simulation. The input matching is measured and showed in Fig. 3.12. The solid line is the measured data and dot line is the simulation result. The trouble shooting is described following.
First, the second harmonic of a single LO MOS is lower than simulation as shown in Fig. 3.13(a) and Fig. 3.13(b) as the circuit is connected as Fig. 3.14. Though the parallel 50 resistor will degrade the mixer gain performance, we can check the second harmonic of LO in IF port and compare to simulation and find out the reason why conversion second harmonic gain degrades so much. In Fig. 3.13 (b), the second harmonic tone will be set in -27dBm in simulation which is 7dB higher than testing result as the same schematic. That means the second harmonic may be lower than simulation.
TABLE I Simulation and measure result of the first chip Simulation Result Measure Result High Gain
Focusing on harmonic generation stage, it is combined by current source and switch-like differential pair. Fig. 3.15 shows the in bias point of 0.7V, the biasing MOS is working in saturation region as simulation. As Vbias adding over 0.75V, the biasing MOS will operation in triode region because of the drain voltage is restricted by VLO. From Fig. 3.15, the assumption that the biasing MOS is working in right operation region is well.
The measurement and simulation result of inductive peaking is shown in Fig.
3.16. The testing circuit is connected the same as measurement of conversion gain, and the buffer amplifier is connected. As RF frequency and LO frequency is change the same time. The down conversion IF frequency is located at the same frequency (3MHz). The measure result and simulation in the same frequency band are shown in Fig. 3.16 (a). It shows that the inductive is shift to lower frequency in simulation result, but the discrepancy in 3.9GHz to 6GHz is small. The measurement result seems to be influenced by RF and LO input matching. Fig. 3.16 (b) is the simulation in wider frequency range, and the inductive peaking is clear. It shifts to lower frequency slightly, and don’t degrade performance greatly.
To make a conclusion, the inductive peaking is moving to lower frequency because of the board. The switch-like harmonic generation scheme may not take effect as simulation and the second harmonic is much lower than simulation result.
This is the reason why conversion gain is much lower than we except.
3.4 Conclusion
It seems that inductive peaking for gain tuning takes effect well. As the second
harmonic is less than expected. The conversion gain is lower than simulation result. It
looks like that the differential pair working between cut-off and triode region may
generate lower second harmonic than expected. The phase and amplitude of
differential LO input degrade the odd harmonic cancellation largely.
Figure 3.1 CMOS harmonic mixer with current injection
Figure 3.2 The 2nd harmonic/DC ratio of a single MOS with Vds=1V
VB1 VB2
Vbias Cbypass
LO+ LO-
RF+ RF-
IF+ IF-
RL RL
Lpeak Vsw
MLO+ MLO-
MSW
MRF+ MRF-
I_LO+ I_LO- I_har I_inject
V_peak
Harmonic generation stage
Mixing stage
Gain tuning stage
---SAT region Proposed way
Figure 3.3 Harmonic generation stage (a) without current source (b) with current source
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Figure 3.4 Harmonic generation stage current Ihar
I_LO+
I_LO-
Figure 3.5 Small signal model of peaking inductor and parallel NMOS switch (a) switch off (b) switch on
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Figure 3.6 Inductance peaking effect (Vpeak/Ihar)
Lpeak
Cp Cp
Ihar Vpeak Ihar Vpeak
(a) (b)
C
LG G
Lpeak Rsw
C
Lturn off turn on
Figure 3.7 Implement buffer in chip
Figure 3.8 testing circuit
Figure 3.9 Microphoto of chip on board
Figure 3.10 Conversion gain and IIP3 in HGM
Figure 3.11 Conversion gain and IIP3 in LGM
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!-!
!-Figure 3.12 Simulation and measure result of S11
Figure 3.13 (a) Spectra in IF+
Figure 3.13 (b) Simulation Result in IF+
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Figure 3.14 Harmonic testing of IF port
Figure 3.15 The bias current v.s bias voltage
Figure 3.16 (a) Measurement of inductive peaking
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Figure 3.16 (b) Simulation of inductive peaking
Chapter 4
A 2.45/5.2GHz Dual-Band Low-Power Direct- Conversion Harmonic Mixer
4.1 Motivation
Multi-standard radio-frequency (RF) receivers are predicted to play a critical role
in wireless communications in the 900-5200MHz range. With cellular and cordless
phone standards operating in the 900MHz and 1.8GHz band, the Global Positioning
System (GPS) in the 1.5GHz band, and wireless local area networks (WLAN)
802.11b in the 2.4GHz band and 802.11a in 5.2GHz band, it is desirable to combine
two or more standards in one mobile unit [10].
The wireless communication specifications 802.11a and 802.11 utilizing
different frequency could be merged in single front-end and share a single digital
signal processor. In this chapter, a 2.45GHz/5.2GHz dual-band, low-power
direct-conversion harmonic mixer is designed and manufactured in tsmc 0.18 m
CMOS process.
4.2 Design Consideration
Fig. 4.1 shows the conceptual example of a dual-band receiver. The receiver
contains two antennas, two LNAs and two mixers. Thought the radio-frequency (RF)
front-end contains two independent paths, the analog circuit and digital signal
processor (DSP) could be combined and decreases the power consumption and cost.
In recently research, the dual-band RF front-end is implemented in a single path (Fig.
4.2). The dual-band LNA is designed for both bands and amplifies both signals
concurrent. In most operation condition, only one of the bands receives RF signal and
the other signal path is unused. That means the mixer must design with concurrent
input matching and only one of the bands will be transferred to output. With this
conception, this mixer is designed in concurrent dual-band input matching and
down-converting one of the receiving band to base-band which system needs. The
conception of Fig. 4.2 will be implemented with this mixer, and the RF front-end
circuit could be designed in a single path.
4.3 Analysis of the Dual-Band Low-Power Harmonic Mixer
The CMOS dual-band harmonic mixer is shown in Fig. 4.3 This harmonic mixer
The CMOS dual-band harmonic mixer is shown in Fig. 4.3 This harmonic mixer