Discussion on Simulation and Measurement Result 33

3.3 Discussion on Simulation and Measurement Result

This section lists the simulation and measure result of the step-gain harmonic mixer. The simulation is done by Agilent advanced Design System (ADS) and post simulation by ADS Momentum.

3.3.1 Measurement Consideration

The measurement of this chip is a question. With the restriction of measurement instruments, some of the data of measure results must be got indirectly. The first is consideration is that while RF signal transfers to base-band, the down-conversion mixer is high impedance in base-band output. Because the base-band circuit such as analog-to-digital converter (ADC) or variable gain amplifier (VGA) is high input impedance, the output of mixer could be design in high impedance for larger conversion gain.

There is a question: the input impedance of the measure instruments is 50 Is it influences the measure results of device-under-test (DUT)? In AC consideration, the large output resistance is parallel with 50 , and the effective loading is dominates by instrument loading. It influences the DUT performance greatly.

For measuring the DUT without degrading it, output buffer is added between DUT and instrument. One way is added buffer circuit such as common drain transistor and implements on-chip. Shown in Fig. 3.7, the buffer circuit consuming large current and the input capacitor degrade the DUT input matching greatly by miller-effect. The following question is how to de-embed the testing circuit without adding another buffer circuit?

The measurement way of this chip is added a unit-gain buffer amplifier between DUT and instrument, shown in Fig. 3.8. Because that the DUT output is differential end, a differential-to-single end unit-gain buffer is adopted. Trading off between influence to DUT and thermal noise of resistor, the 8.2K resistor for differential amplifier is adopted. The output of amplifier is series with 49.9 for

of the DUT and the measurement result is the point B. The power difference of point A and B is 6dB and we could get the real output results by measurement results.

3.3.2 Chip Implementation

Fig. 3.9 shows the microphotograph of the step-gain harmonic mixer circuit.

The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area

including bonding pads is 0.906 mm by 0.508 mm. Careful layout is observed in order

to maximize performance. The layout is done in a uni-directional fashion, i.e. no

signal returns close to it origins, to avoid coupling back to the input. For the layout

consideration, the RF-LO ports isolation is the first consideration and places these

ports opposite of the chip to improve port-to-port isolation and enhance DC-offset

cancellation scheme. The RF port, which the signal level is less than LO port, crosses

the IF port vertically and decreases the overlap area to minimize the couple of both

ports. The layout is placed symmetrically to minimize the mismatch of the differential

signal. In order to minimize the effect of substrate noise on the system, a solid ground

plane, constructed using a low resistive metal-1 material, is placed between the signal

pads (metal-6 and metal-5) and the substrate.

3.3.3 Simulation and Measurement Result

The simulation and measure result is listed in TABLE I. Though the DC current is 2.2mA, similar to simulation, the conversion gain is -5dB in high gain mode (HGM) and -6.5dB in low gain mode (LGM) which is 23dB and 15dB lower than simulation result in HGM and LGM. The conversion gain and IIP3 are shown in Fig. 3.10 and Fig.3.11. Because of the conversion gain is lower than expect, the IIP3 is large than simulation. The input matching is measured and showed in Fig. 3.12. The solid line is the measured data and dot line is the simulation result. The trouble shooting is described following.

First, the second harmonic of a single LO MOS is lower than simulation as shown in Fig. 3.13(a) and Fig. 3.13(b) as the circuit is connected as Fig. 3.14. Though the parallel 50 resistor will degrade the mixer gain performance, we can check the second harmonic of LO in IF port and compare to simulation and find out the reason why conversion second harmonic gain degrades so much. In Fig. 3.13 (b), the second harmonic tone will be set in -27dBm in simulation which is 7dB higher than testing result as the same schematic. That means the second harmonic may be lower than simulation.

TABLE I Simulation and measure result of the first chip Simulation Result Measure Result High Gain

Focusing on harmonic generation stage, it is combined by current source and switch-like differential pair. Fig. 3.15 shows the in bias point of 0.7V, the biasing MOS is working in saturation region as simulation. As Vbias adding over 0.75V, the biasing MOS will operation in triode region because of the drain voltage is restricted by VLO. From Fig. 3.15, the assumption that the biasing MOS is working in right operation region is well.

The measurement and simulation result of inductive peaking is shown in Fig.

3.16. The testing circuit is connected the same as measurement of conversion gain, and the buffer amplifier is connected. As RF frequency and LO frequency is change the same time. The down conversion IF frequency is located at the same frequency (3MHz). The measure result and simulation in the same frequency band are shown in Fig. 3.16 (a). It shows that the inductive is shift to lower frequency in simulation result, but the discrepancy in 3.9GHz to 6GHz is small. The measurement result seems to be influenced by RF and LO input matching. Fig. 3.16 (b) is the simulation in wider frequency range, and the inductive peaking is clear. It shifts to lower frequency slightly, and don’t degrade performance greatly.

To make a conclusion, the inductive peaking is moving to lower frequency because of the board. The switch-like harmonic generation scheme may not take effect as simulation and the second harmonic is much lower than simulation result.

This is the reason why conversion gain is much lower than we except.