Simulation and Measure Result

This section describes the simulation and measure result of the step-gain harmonic mixer. The pre-simulation is done by Agilent advanced Design System (ADS) and post EM-simulation is done by ADS Momentum.

4.4.1 Chip Implementation

Fig. 4.6 shows the microphotograph of the dual-band harmonic mixer circuit.

The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area

including bonding pads is 0.795mm * 0.683mm. Careful layout is observed in order to

maximize performance. The layout is done in a uni-directional fashion, i.e. no signal

returns close to it origins, to avoid coupling back to the input. For the layout

consideration, the RF-LO ports isolation is the first consideration and places these

ports opposite of the chip to improve port-to-port isolation and enhance DC-offset

cancellation scheme. The RF port, which the signal level is less than LO port, crosses

the IF port vertically and decreases the overlap area to minimize the couple of both

ports. The layout is placed symmetrically to minimize the mismatch of the differential

signal. In order to minimize the effect of substrate noise on the system, a solid ground

plane, constructed using a low resistive metal-1 material, is placed between the signal

pads (metal-6 and metal-5) and the substrate.

4.4.2 Simulation and Measurement Result

The simulation and measure result is listed in TABLE II. Because the 1.225GHz balun is unavailable, we can not measure the 2.45GHz band now. Though the DC current is similar to simulation, the conversion gain is 39dB lower than simulation result. The conversion gain and IIP3 plot is showed in Fig. 4.7. Because most of IM3 is under noise floor, the IIP3 is gained by equation (4.5).

dBm

Because that the harmonic generation stage is the same with former, the lower second harmonic is poor to driver RF MOS. With injection current nearly to zero, the conversion gain is negative. The 5.2GHz input matching is measured and showed in Fig. 4.8. Because that the input balun is narrow band, the input matching is measured separately. The solid line is the measured data and dot line is the simulation result.

TABLE II Simulation result and measure result of the second chip Simulation Result Measure Result

Band 2.45GHz 5.2GHz 2.7 GHz 5.2GHz amplifier is connected. As RF frequency and LO frequency is change the same time.

The down conversion IF frequency is located at the same frequency (3MHz). The

peaking frequency shifts to lower frequency as plot.

4.5 Conclusion

As showed in chapter 3, the differential pair working between cut-off and triode

region may generate lower second harmonic than expected. In this work, the lower

injection current for current reusable let the harmonic/DC ratio too low to drive the

RF MOS and the inductive peaking is moving to low frequency. It makes the

conversion gain is degraded substantially.

Figure 4.1 Conceptual example of a dual-band receiver

Figure 4.2 Conceptual example of a concurrent dual-band receiver

Figure 4.3 Dual-band low-power harmonic mixer

Figure 4.4 Small signal model of peaking inductor and parallel NMOS switch (a) switch off (b) switch on

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Figure 4.5 Inductance peaking effect (Vpeak/Ihar)

Figure 4.6 Chip implement

Fig 4.7 Conversion Gain and IIP3

Figure 4.8 Input matching in 5.2GHz band

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Figure 4.9 Measurement result inductive peaking in 5.2GHz band

Chapter 5

Summary and Future Works

5.1 Summary

In the chapter 2, the DC-offset of direct-conversion, heterodyne and low IF receivers are presented. The DC-offset issue is an intrinsic problem of direct-conversion receiver because of frequency planning. In the last of chapter 2, the harmonic mixer is mentioned and it seems a way to solve this issue. Besides the DC-offset consideration, two harmonic mixers are introduced. The RF signal is mixing with the second harmonic of LO signal. Both of they are influenced by low linearity.

In the chapter 3, a step-gain harmonic mixer using inductive peaking scheme and switch-like harmonic generation stage is analyzed and implemented in a standard 0.18um CMOS process. Although, measured result show that the conversion gain is lower than simulation, the switch-able inductance peaking scheme for step-gain takes effect as simulation. The trouble shooting is showed in last of chapter 3. Measured data still show that the mixer achieves -15 dB input return loss (S11), while consuming 2.2mA DC current.

In the chapter 4, a dual-band low-power harmonic mixer, intended for use in the receiver path of 802.11a/b system is designed in a standard 0.18um CMOS process.

With the same harmonic generation stage as former, the conversion gain is less than simulation result.

5.2 Future Works

Although some measure results are showed in this thesis, the measurement and trouble shooting of these chips still continues. The drilled PCB board introduces some problem such as leakage and signal loss. Since the bias voltage is fed by a large resistance as RF choke, any leakage will degrade the bias voltage. It should be considered to seek a proper PCB board for testing.

REFERENCES

[1] Abidi, A.A., “RF CMOS come of age,” VLSI Circuits, 2003, Digest of Technical Papers, pp.113-116, June, 2003.

[2] Razavi, B. RF Microelectronics, Prentice Hall PTR, 1998.

[3] Razavi, B., “Design considerations for direct-conversion receivers”; Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, pp.428-435 June, 1997.

[4]Yamaji T. and Tanimoto H., “A 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers,” Proc. of IEEE custom IC Conf., pp.193-196, May, 1997.

[5]Yamaji, T.; Tanimoto, H., and Kokatsu, H., “An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter,” IEEE J. Solid-State Circuits, vol.33, pp.2240-2246, Dec. 1998.

[6] Z. Zhang, Z. Chen and J. Lau, “A 900MHz Balanced Harmonic Mixer for Direct Conversion Receivers,” Proc. IEEE RAWCON2000, pp.219-222, Sept. 2000.

[7] S. J. Fang, S. T. Lee, and David J. Allstot, “A 2GHz CMOS Harmonic Mixer for Direct-Conversion Receivers,” ISCAS 2002, vol.4, pp.IV-807-IV-810, May 2002.

[8]C. Y. Cha, and S. G. Lee, “A low power, high gain LNA topology,” Microwave and Millimeter Wave Technology, 2000, 2nd International Conference on. ICMMT 2000, pp.420-423, Sept. 2000.

[9]Huang, J.C., R. M. Weng, C. C. Chang, K. Hsu and K. Y. Lin, “A 2 V 2.4 GHz fully integrated CMOS LNA,” Circuits and Systems, ISCAS 2001. vol.4, pp.466-469, May 2001.

[10]T. Antes and C. Conkling, “RF chip set fits multimode cellular/PCS handsets,”

Microwaves RF, pp.177-186, Dec. 1996

(Shang-Yi Liu)

(84 9 ~87 6 ) (87 9 ~91 6 )

(91 9 ~93 10 )

PUBLICATION LIST

[1]. Shang-Yi Liu and Chien-Nan Kuo, "A 5.2GHz Direct-conversion Step-gain Harmonic Mixer," VLSI/CAD Symposium, 2004.