2.45/5.2 GHz雙頻帶低功率直接降頻諧波混波器之設計

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(1)2.45/5.2 GHz. 0.18um CMOS 802.11a/b. 2.45/5.2 GHz. 802.11a. 5.2GHz. 5.2GHz. 18dB 1MHz. 16dB. -3.1dBm (IIP3) -5.6dBm. 8.7dB. 1MHz -10dBm. LO. (IIP3) 25.7dB 1.8V. 4.6mW 802.11a GHz. I. 802.11b. 2.45/5.2.

(2) 2.45GHz 2.45GHz 16.7dB. (S11) -11dB 15.5dB. (IIP3) -6dBm. (S11) -12dB 13.5dB. 5.2GHz. (IIP3) -1dBm. 1.8V. 2.3mW. II. 18.9dB -10dBm. LO. 5.2GHz.

(3) Design of 2.45/5.2 GHz Dual-band Low-power Direct-conversion Harmonic Mixer Student Shang-Yi Liu. Advisor Prof. Chien-Nan Kuo. Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University. ABSTRACT The aim in this thesis is mainly based on the design of 2.45/5.2 GHz dual-band low-power direct-conversion harmonic mixer in the receiver front-end of 802.11a/b wireless local area network (WLAN) system using standard 0.18um CMOS process. Also, a narrow band 5.2GHz step-gain direct-conversion harmonic mixer is designed and analysis for 802.11a WLAN system. The two harmonic mixers were verified through individual chips. In the first chip, a 5.2GHz step-gain direct-conversion harmonic mixer for 802.11a WLAN system is designed and analyzed. The harmonic mixer cancels the odd harmonic of LO signal by connecting the drains of the differential pair. It adopts a third-order low-pass filter with inductive peaking increasing the second harmonic level. This optimizes conversion gain and noise performance with a restricted bias current. Controlled by a switch, the simulation result shows that the mixer offers two gain levels of 18dB and 8.7dB. At high-gain mode, it achieves noise figure of 16dB at 1MHz frequency, and third-order input intercept point of -3.1dBm. At low-gain mode, it achieve noise figure of 25.7dB at 1MHz, and third-order input intercept point of. III.

(4) -5.6dBm. Differential LO power level is chosen as -10dBm. With a supply voltage of 1.8V, the total power consumption is about 4.6mW. In the second chip, a 2.45/5.2 GHz dual-band low-power direct-conversion harmonic mixer for 802.11a/b WLAN system is introduced. By tuning the peaking frequency of third-order low-pass filter, it can choose the operation frequency either in 2.45GHz or in 5.2GHz band. Simulation result shows that in 2.45GHz operation frequency, it achieves S11 of -11dB, conversion gain of 16.7dB, noise figure of 15.5dB, and third-order input intercept point of -6dBm. In 5.2GHz operation frequency, it achieves S11 of -12dB, conversion gain of 18.9dB, noise figure of 13.5dB, and third-order input intercept point of -1dBm. With1.8V power supply and -10dBm differential LO signal, the power consumption is about 2.3mW. IV.

(5) V.

(6) CONTENTS ABSTRACT (CHINESE) ...........................................I ABSTRACT (ENGLISH) ..........................................III ACKNOWLEDGEMENT ..........................................V CONTENTS.................................................................VI TABLE CAPTIONS.....................................................X FIGURE CAPTIONS..................................................XI. VI.

(7) Chapter 1 Introduction.................................................. 1 1.1 Motivation....................................................................... 1 1.2 Thesis Organization....................................................... 3. Chapter 2 DC-offset Issue in RF Receiver................... 4 2.1 Direct-conversion Receiver ........................................... 4 2.1.1 DC-Offset Issue in Direct-Conversion Receiver.............5 2.1.2 Quantification of Self-Mixing DC-Offset........................7 2.1.3 To Avoid DC-Offset: Harmonic Mixer............................8 2.1.4 Others Way to Avoid DC-Offset....................................10 2.1.4.1 DC-Free Coding with High Pass Filter.................................. 10 2.1.4.2 DC-Offset compensation....................................................... 10. 2.2 Heterodyne Receiver ................................................... 11 2.2.1 Frequency planning ....................................................... 11 2.2.2 DC-offset Issue ...............................................................12. 2.3 Low IF Receiver ........................................................... 13 2.3.1 DC-offset Issue ...............................................................13. 2.4 Some Reference Harmonic Mixers ............................ 14 2.4.1 900MHz Balanced Harmonic Mixer .............................14 2.4.2 2GHz Even Harmonic Mixer ........................................15. 2.5 Summary....................................................................... 16. Chapter 3 A 5.2GHz Direct-conversion Step-gain Harmonic Mixer ........................................................... 24 3.1 Motivation..................................................................... 24 3.2 Analysis of the Step-Gain Harmonic Mixer .............. 24 3.2.1 Harmonic Generation Stage ..........................................25 VII.

(8) 3.2.1.1 Define Harmonic/DC Ratio................................................... 28. 3.2.2 Mixing Stage...................................................................29 3.2.3 Gain Tuning Stage..........................................................31 3.2.3.1 Quantitate the Step Gain ....................................................... 33. 3.3 Discussion on Simulation and Measurement Result 33 3.3.1 Measurement Consideration .........................................34 3.3.2 Chip Implementation.....................................................35 3.3.3 Simulation and Measurement Result............................36. 3.4 Conclusion .................................................................... 37. Chapter 4 A 2.45GHz/5.2GHz Dual-band, Low- power Direct-conversion Harmonic Mixer ........................... 48 4.1 Motivation..................................................................... 48 4.2 Design Consideration................................................... 49 4.3 Analysis of the Dual-Band Low-Power Harmonic Mixer ................................................................................... 49 4.3.1 Harmonic Generation Stage ..........................................50 4.3.1.1 Define Harmonic/DC Ratio................................................... 50. 4.3.2 Mixing Stage...................................................................50 4.3.3 Frequency Tuning Stage ................................................51 4.3.3.1 Quantitate the Gain Enhancement ......................................... 53. 4.4 Simulation and Measure Result ................................. 54 4.4.1 Chip Implementation.....................................................54 4.4.2 Simulation and Measurement Result............................55. 4.5 Conclusion .................................................................... 56. Chapter 5 Summary and Future Works.................... 62 5.1 Summary....................................................................... 62 VIII.

(9) 5.2 Future Works ............................................................... 63. REFERENCES........................................................... 64 VITA..............................................................................65. IX.

(10) TABLE CAPTIONS Table. Simulation and measure result of the first chip………………………….36. Table. Simulation result and measure result of the second chip………………...55. X.

(11) FIGURE CAPTIONS Fig. 2.1 Direct conversion receiver architecture...................................................17 Fig. 2.2 Frequency conversion of direct conversion receiver...............................17 Fig. 2.3 Self-mixing of (a) LO signal, (b) a strong interferer……………………18 Fig. 2.4 Self-mixing due to LO leakage………………………………………….18 Fig. 2.5 DC-Offset issue of (a) the conventional mixer (b) the second harmonic mixer……………………………………………………………………………...19 Fig. 2.6 Work principle of harmonic mixer……………………………………….19 Fig. 2.7 DC-Offset compensation………………………………………………...20 Fig. 2.8 Heterodyne receiver……………………………………………………...20 Fig. 2.9 Frequency planning………………………………………………………21 Fig. 2.10 Feedthrough caused by substrate loss…………………………..………21 Fig. 2.11 Low IF receiver………………………………………………………….22 Fig. 2.12 DC-offset issue of (a) direct conversion receiver (b) low IF receiver…..22 Fig. 2.13 A 900MHz balanced harmonic mixer……………………………..…….23 Fig. 2.14 A 2GHz even harmonic mixer……………………………………….….23 Fig. 3.1 CMOS harmonic mixer with current injection…………………………...39 Fig. 3.2 The 2nd harmonic/DC ratio of a single MOS with Vds=1V……………...39 Fig 3.3 Harmonic generation stage (a) without current source (b) with current source………………………………………………………………………………40 Fig. 3.4 Harmonic generation stage current……………………………………….40 Fig. 3.5 Small signal model of peaking inductor and parallel NMOS switch(a) switch off (b) switch on…………………………………………………………...41 Fig. 3.6 Inductance peaking effect (Vpeak/Ihar)…………………………………….41 Fig. 3.7 Implement buffer in chip…………………………………………….…...42 XI.

(12) Fig. 3.8 testing circuit……………………………………………………….….….42 Fig. 3.9 Microphoto of chip on board…………………….………………….…….43 Fig. 3.10 Conversion gain and IIP3 in HGM…………………………..….…….....43 Fig. 3.11 Conversion gain and IIP3 in LGM……………………………..………..44 Fig. 3.12 Simulation and measure result of S11………………………..………….44 Fig. 3.13 (a) Spectra in IF+. (b) Simulation Result in IF+..………………...……45. Fig. 3.14 Harmonic testing of IF port…………………………………….………..46 Fig. 3.15 The bias current v.s bias voltage………………………………….……..46 Fig. 3.16 (a) Measurement of inductive peaking (b) Simulation result of inductive peaking………………………………………………………………...…………..47 Fig. 4.1 Conceptual example of a dual-band receiver……………………..………57 Fig. 4.2 Conceptual example of a concurrent dual-band receiver…………………57 Fig. 4.3 Dual-band low-power harmonic mixer……………………………………58 Fig. 4.4 Small signal model of peaking inductor and parallel NMOS switch(a) switch off (b) switch on…………………………………………………………….58 Fig. 4.5 Inductance peaking effect (Vpeak/Ihar)……………………………………...59 Fig. 4.6 Chip implement…………………………………………………….……...59 Fig. 4.7 Conversion Gain and IIP3…………..…………...………………….…..…60 Fig. 4.8 Input matching in 5.2GHz band…….……………...………….…….…….60 Fig. 4.9 Inductive peaking in 5.2GHz band…………………………..……….……61. XII.

(13) Chapter 1 Introduction. 1.1 Motivation Wireless communications at multi-gigahertz frequencies has made much progress since the first radio frequency (RF) transceiver was published. All CMOS RF transceivers and systems-on-chip (SoC) solutions are rapidly making inroads into a WLAN market that was dominated by bipolar and BiCMOS solutions for years [1]. The typical RF receivers were assembled by such as low-noise amplifier (LNA), mixer and voltage control oscillator (VCO). The first stage of a receiver is a LNA, whose main function is to provide enough gain to suppress the noise of subsequent stages as well as adding as little noise as possible in itself. The VCO generates precise LO signal for down-conversion. The mixer connects the LNA and VCO which mixes the RF signal with the LO signal and generates intermediate frequency (IF) or base-band (BB) signal. In heterodyne receiver architecture, there are more than two mixers and VCO(s) which convert RF signal to base-band access more than one IF. In direct-conversion architecture, there is only one mixer and VCO. Because the direct-conversion receiver. 1.

(14) (DCR) architecture is consisted of fewer components than heterodyne one, in recent years, the DCR architecture has gained much attention as a promising solution for a single-chip RF receiver because of its low-power, low-complexity, imagerejection-free and easy-to-integrate properties. However, design of direct-conversion receivers is required to resolve many issues such as self-mixing induced DC-offset, flicker noise, even-order distortion, I/Q mismatch, and so on. DC-offset is one of the most important issues and it can saturate the following stage in mixer output. To avoid DC-offset, harmonic mixer structure for DRC is published. In this thesis, two harmonic mixers for the receiver of 5.2GHz narrow band and 2.45/5.2GHz dual band is designed and analyzed. The first chip for narrow band application, inductive peaking principle is applied in inter-stage of harmonic mixer for peaking of the second harmonic of LO. With a parallel switch that eliminates inductive peaking, the mixer has two gain modes. It ensures the system operating in larger input dynamic range. The second chip for 2.45/5.2 GHz dual band system, the switchable peaking frequency third-order low-pass filter chooses the operation frequency. The dual-band input matching makes the two bands coexisted and the peaking inductor chooses the operation frequency either in 2.45GHz or in 5.2GHz. The power consumption is half of the first one, while the performance does not degrade too much.. 2.

(15) 1.2 Thesis Organization In the Chapter 2 of the thesis, the DC-offset issue in different receiver architecture is introduced. Although in direct-conversion receiver, this issue is the most important problem to overcome. Two harmonic mixers are introduced. Based on the first harmonic mixer, two harmonic mixers in this these is designed and measured in following chapter. In Chapter 3, a narrow band harmonic mixer using inductance peaking topology intended for application of the 5.2GHz wireless direct-conversion receiver is introduced. The detailed circuit analysis and design equation is presented. The odd-harmonic cancellation scheme and the second harmonic enhancement by inductance peaking are also discussed. Finally, measurement result of the mixer fabricated by TSMC 0.18um CMOS technology is discussed. In Chapter 4, a 2.45/5.2-GHz dual-band low-power harmonic mixer intended for 802.11a/b system is proposed. The switchable inductance peaking scheme is adopted for switching frequency. Based on chapter 3, the harmonic mixer is designed in lower power and two bands input matching. Finally, measurement result of the mixer fabricated by TSMC 0.18um CMOS technology is discussed. In the last chapter, all the work is summarized and concluded.. 3.

(16) Chapter 2 DC-Offset Issue in RF Receiver In this Chapter, the DC-offset issue is analyzed in different situations. DC-offset issues in direct-conversion receivers are analyzed in section 2.1. In this section, the DC-offset issue would be discussed about how the DC-offset influence the directconversion receiver and how to avoid or release it. It also shows the DC-offset-free characteristic of the harmonic mixer. DC-offset issue would be discussed in low-IF receiver and in heterodyne receiver in section 2.2 and section 2.3. In these sections, they show the DC-offset issue is migrated cleverly by the architecture design but these architectures induce other issues at the same time.. 2.1 Direct-conversion Receiver The direct-conversion receiver (DCR) [Fig. 2.1] is also called “homodyne” or “zero-IF” architecture because that the RF signal transfers to output and is downconverted to zero-frequency. Shown in Fig. 2.2 is a simple frequency conversion of DCR, where the local oscillator (LO) frequency is equal to the input radio frequency (RF) carrier and the channel selection requires only a low-pass filter with relatively sharp cutoff characteristics [2]. This architecture was invented many decades ago, and was improved greatly in recent years. The reasons that this architecture has recently become the topic of active research, perhaps to a much greater extent than before are accounted for this renaissance: (1). Direct-conversion architecture which eliminates of SAW filter and all of 4.

(17) subsequent down-conversion stages are replaced with low-pass filters, in principle, lends itself to monolithic integration much more easily than heterodyne receivers; (2). The problem of image is circumvented because of ω IF = 0 . As a result, no image filter is required, and the LNA need not drive a 50-. load for off-chip SAW. filters; (3). Direct-conversion architecture’s past failures arose primarily from effects that could not be removed in discrete implementations, but may be controlled and suppressed in integrated circuits. In other words, direct-conversion architecture is one of few reception techniques whose drawbacks can be remedied through the use of only more transistors [3]. Nevertheless, the DRC direct translation of the spectrum to zero frequency entail a number of issues that do not exist or are not as serious in a heterodyne receiver. One of the most serious issues is the DC-offset issue.. 2.1.1 DC-Offset Issue in Direct-Conversion Receiver Since in the direct-conversion topology, the down-converted band extends to zero frequency, extraneous offset voltage can corrupt the signal and, more importantly, saturate the following stages. To understand the origin and impact of DC-offsets, consider the receiver shown in Fig. 2.3, where the LPF is followed by an amplifier and an A/D converter. The LPF would not decrease the DC-offset value, and it can easy saturate the following stage. The DC-offset is caused by three sources mainly. (1). Self-mixing due to LO Leakage [Fig. 2.3(a)]: The isolation between the LO port and the input of the mixer and the LNA is finite. This effect arise from capacitive feed-through and substrate coupling and, if the 5.

(18) LO signal is provided externally, bond wire coupling. The LO signal leaks into point A or point B, and is reflected at the output port of RF amplifier and at the antenna connector. The reflected LO signal is self-mixed at the mixer and results in DC-offset [4]. In most receiver architectures, the LO signal power level is much greater than RF signal power level. That means, in designing of DCR, it always considers the restriction of the mixer LO-to-RF input isolation and the low-noise amplifier (LNA) reverse isolation to avoid the base-band output with large DC-offset which will saturate the following stage. This is the main DC-offset generator in DRC architecture. (2). Self-mixing due to large interferer in RF port [Fig. 2.3(b)]: This is similar to former because that isolation between the LO port and the input of the mixer and the LNA is finite. The effect occurs if a large interferer leaks from the LNA and mixer LO input, point C, and is multiplied by itself to result in DC-offset. (3). Mismatch of component: The mismatch of differential pair also cause DC-offset in output. This can be solved by mismatch compensation circuit design. For example: the total gain from the antenna to point X is typically around 80 to 100 dB so as to amplify the microvolt input signal to a level that can be digitized by a low-cost, low power analog-to-digital converter (ADC). Of this gain, typically 25 to 30 dB is contributed by the LNA/mixer combination. With the above observations, we can obtain a rough estimated of the offset resulting from self-mixing to appreciate the problem. Suppose in Fig. 2.3 (a) the LO signal has a peak-to-peak swing of 0.63V (0 dBm in a 50. system) and experiences. an attenuation of 60 dB as it couples to point A. If the gain of the mixer is on the order. 6.

(19) of 10mV, we also note that the desired signal level at this point can be as low as approximately 30 Vrms. Thus, if directly amplified by the remaining gain of 50 to 70 dB, the offset voltage saturates the following circuits, there by prohibiting the amplification of the desired signal [2].. 2.1.2 Quantification of Self-Mixing DC-Offset Fig. 2.4 shows the self-mixing mechanism. The LO frequency is set at the same frequency as the received signal frequency, and the received signal is down-converted to base-band directly. The LO signal leaks to the RF signal input port of the mixer and is reflected at the output port of the low noise amplifier (LNA) and at the antenna. The reflected LO signal is down-converted at the mixer and results in a DC-offset. The offset voltage at the mixer output due to self-mixing Vself is described by. Vself = Vleak Ramp G LO − BB. (2.1). where Vleak is the leaked LO signal voltage, Ramp is the reflection factor at the RF amplifier output port, and G LO − BB is the conversion gain of the mixer from LO signal frequency to base-band. The RF amplifier gain is often switched depending on received signal strength. Therefore, the self-mixing output is not a stable DC-offset. The equation (2.1) suggests three ways to reduce the offset Vself . The first is reducing LO signal leakage Vleak . The second is reducing Ramp . Note that the Ramp is varied depending on the electromagnetic environment of the antenna and the reverse and/or forward gains of the RF amplifier, and it is difficult to realize extremely small Ramp practice. The last is reducing the conversion gain G LO − BB . In the usual direct-conversion case, reducing conversion gain does not improve desire7.

(20) signal to undesired-signal ratio, therefore a raw output offset voltage cannot be a measure for self-mixing. In reference paper [4] [5], it uses the equivalent RF amplitude Veq at mixer input while assuming the worst case of Ramp = 1 as the measure of self-mixing:. Veq = Vleak. G LO − BB G RF − BB. (2.2). where G RF − BB is the conversion gain from received signal frequency to baseband. The way to reduce Veq are (1) to reduce Vleak , and (2) to reduce. G LO − BB . This will G RF − BB. describe the efficient realization of these conditions by this thesis. For example, in a typical direct-conversion receiver, assuming the LO signal is -10dBm, -50dBm Vleak from the RF input port (i.e. 40dB isolation), and the -14dB reflection factor at the RF amplifier output ( VSWR ≈ 1.5 ), reflected LO signal is -64dBm (140 µVrms ) at mixer input. This is 57dB higher than thermal noise in 200kHz bandwidth from 50. resistor.. 2.1.3 To Avoid DC-Offset: Harmonic Mixer Fig.2.5 (a) shows that the LO self-mixing problem in a DCR arises due to the situation that LO signal resides at the same frequency as the RF signal. As DC-offset can’t be easily filtered out without removing any base-band signal because most modulation schemes contain significant DC and low frequency components. Because DC-offset is caused by self-mixing of LO signal mainly, one should apparently. 8.

(21) separate the RF and LO frequencies in order to avoid the problem. That means: if LO frequency is separated far away from RF frequency, there is no DC-offset problem. For the harmonic mixer shown in Fig.2.5 (b), it is the second harmonic of the LO signal that takes part in the mixing process. In equation (2.2), the. Veq is zero because the LO leakage in receiving frequency in RF input is zero. As a result, the LO leakage generates no DC component but an output the LO frequency and can be easily filtered out with a low-pass filter (LPF). Fig.2.6 shows the typical working principal of a direct-conversion harmonic mixer. The LO frequency is just in the 1/n of RF frequency. It not only simplifies the oscillator design consideration but solves the DC-offset issue of DCR. The CMOS balance harmonic mixer proposed by Zhang [6] generates the second harmonic of LO frequency by odd harmonic cancellation and mixes it with RF signal in the NMOS pair which is operating in sub-threshold region. It adopts current injection to decrease transistor’s current and lower flicker noise. The harmonic mixer proposed by Fang [7] receives quadrature LO signal with two cascaded transistors and operation as a switch at twice frequency of LO signal. These works, however, suffer from the low third-order input intercept point (IIP3) problem and fixed conversion gain.. 9.

(22) 2.1.4 Others Way to Avoid DC-Offset This section shows some DC-offset cancellation scheme. DC free coding and DC-offset compensation will be introduced in following paragraph.. 2.1.4.1 DC-Free Coding with High Pass Filter The base-band signal in the transmitter can be encoded such that, after modulating and down-conversing to base-band, it contains little energy near DC. With accessing a high pass filter, the DC-offset problem can be solved by wasting few of signals. Called “DC-free coding,” this is particularly suited to wideband channel, for example, in DECT, where a few kilohertz of the channel can be wasted with no significant drop in the data rate.. 2.1.4.2 DC-Offset compensation This technique exploits the idle time intervals in digital wireless standards to carry out offset cancellation. Shown in Fig.2.7 is an example, where a capacitor C1 stores the offset between consecutive TDMA bursts, while introducing a virtually zero corner frequency during the reception of data. For a typical TDMA frame of a few milliseconds, offset cancellation is performed with sufficient frequency to take into account variations due to moving objects.. 10.

(23) 2.2 Heterodyne Receiver Fig.2.8 shows the heterodyne receiver architecture with one intermediate frequency (IF) before the RF signal down-converts to base-band. The “Heterodyne” means that there is one or more IF before base-band signal. This is the most mature receiver design scheme today because each performance would trade of properly in each stage. The heterodyne architecture has some issues compare to homodyne architecture, such as image problem. The image reject filters require high Q and need off-chip SAW components usually. For this reason, the heterodyne receiver is hardly to cost down and applies to system-on-chip (SoC) designs.. 2.2.1 Frequency planning How to choose the LO frequency and the IF frequency? The principal consideration here is the “image problem.” To understand the issue, note that a simple analog multiplier does not preserve the polarity of the difference between its two input frequencies, i.e., for x1 (t ) = A1 cos ω1t and x2 (t ) = A2 cos ω2t , the mixer output products of x1 (t ) and x2 (t ) is the from cos(ω1 − ω2 )t , no different from cos(ω2 − ω1 )t . Thus, in a heterodyne architecture, the bands symmetrically located above and below the LO frequency are down-converted to the same center frequency [Fig.2.9] if the received band of interest is centered around ω1 (= ωLO − ωIF ) , then the image is around 2ωLO − ω1 (= ωLO + ωIF ) and vice versa.. 11.

(24) 2.2.2 DC-offset Issue The DC-offset issue in heterodyne receiver is so slight that most papers have not make mention of it. Chapter 2.1.1 describes that DC-offset is caused by (1) Self-mixing due to LO Leakage [Fig. 2.3(a)] (2) Self-mixing due to large interferer in RF port [Fig. 2.3(b)] (3) Mismatch of components. The DC-offset which is caused by mismatch could compensation by negative feedback or digital signal process and fully calibrated. The DC-offset which is caused by self-mixing of leakage is due to the coupling effect or substrate loss between LO and RF input. The coupling effect is proportion of operation frequency. In other words, the heterodyne architecture has slight DC-offset due to coupling effect because of the lower LO frequency. Fig.2.10 is the basic substrate model. The substrate behaves as a resistor. The metal line and substrate have parasitic capacitance effect which the resistance is the function of frequency. The resistance between LO and RF input is. Req = l × Rsub +. 1 1 + j 2πfCRF j 2πfC LO. (2.3). where l is the distance between RF and LO input, Rsub is the substrate resistance per unit, CRF and CLO is the capacitance of both port to substrate. Equation (2.3) show the substrate loss between these ports is influenced by layout scheme and the frequency. In heterodyne receiver, the frequency of the final mixing stage is less than the homodyne one’s. In most of the heterodyne architecture, the final mixing stage LO frequency has less than the one-fifth of the received signal. The DC-offset which is 2 caused by self-mixing is direct proportion of Vleakage , and with this reason, the. DC-offset in heterodyne receiver could be ignored.. 12.

(25) 2.3 Low IF Receiver In the heterodyne architecture of Fig.2.8, low frequency operations such as the second set of mixing and filtering can be performed more efficiently in the digital domain. Shown in Fig.2.11 is an example where the first IF signal is digitized, “mixed” with the quadrature phases of a digital sinusoid, and low-pass filtered to yield the quadrature base-band signal. This approach is sometimes called a “digital-IF architecture.” This principal issue in this approach is the performance required of the analog-to-digital converter (ADC). Since the signal level at AMP output in Fig.2.11 is typically no higher than a few hundred micro-volts, the quantization and thermal noise of the ADC must not exceed a few tens of micro-volts. Furthermore, if the first IF band-pass filter cannot adequately suppress adjacent interferes, the nonlinearity of the ADC must be sufficiently small to minimize corruption of the signal by intermodulation. Also, the ADC dynamic range must be wide enough to accommodate variations in the signal level due to path loss and multi-path fading. Additionally, the ADC must achieve an input bandwidth commensurate with the value of IF while consuming a reasonable amount of power.. 2.3.1 DC-offset Issue In low IF structure, the DC-offset issue is migrated cleverly because that the frequency of DC-offset is different to IF signal. As shown in Fig.2.12 (b). In Fig.2.12 (a), the self-mixing introducing DC-offset is in the zero frequency, while the conventional direct-conversion mixer suffers this issue because of the signal is 13.

(26) down-converted to zero frequency and overlaps the DC-offset in frequency. As DC-offset can’t be easily filtered out without removing any base-band signal because most modulation schemes contain significant DC and low frequency components. Low IF architecture becomes a possible solution to DC-offset, but it suffers from the complex digital process and high speed ADC to convert base-band signal from IF signal. The low IF structure also suffers from the image problem as heterodyne receiver.. 2.4 Some Reference Harmonic Mixers In this section, some harmonic mixer is introduced. All of these are designed in the cause of DC-offset-free. Some of these is done in symmetrical, and they could increase the second-order input intercept point (IIP2).. 2.4.1 900MHz Balanced Harmonic Mixer The “A 900MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receiver” is published in Proc. IEEE RAWCON2000 [6]. It’s fabricated in a 0.35um standard digital CMOS process. In Fig. 2.13, the second harmonic is easily obtained because of the inherent square-law operation of the CMOS transistor. The LO stage is actually a squaring cell with converts the differential LO voltage to the time-varying current which contains the second harmonic. In principle, the fundamental and all odd harmonics of the LO will be cancelled out at the connected drain terminals and the DC offset problem will be mitigated. Flicker noise is an issue in direct conversion receivers. When the transistor size is increased, however, it is found that the optimal point moves towards the weak. 14.

(27) inversion region. To reduce the flicker noise, the RF part can be biased near this region. At a biasing current, a larger W/L ratio drives the device toward the moderate or weak inversion region. The objective of the injected current source is to reduce the current in the two upper transistors driven by the RF signal. This helps to reduce the 1/f noise of the upper transistor pair. The injected current itself will not introduced noise in this balanced structure. Unlike the normal Gilbert-type mixer, the two RF transistors change their currents simultaneously and any noise at their common source node will be completely cancelled out at the differential output. 2.4.2 2GHz Even Harmonic Mixer Fig. 2.14 show a double-balanced version of the CMOS even-harmonic mixer; it provides down conversion mixing of the differential RF input signal with even harmonics of the LO differential signal while suppressing RF mixing with the LO fundamental and odd harmonics. This circuit is reference from ISCAS 2002 [7], and it’s fabricated in a 0.25um standard digital CMOS process. As shown, suppression of odd harmonic mixing is accomplished by summing differential signal at the drains of M5 and M6 (BB+), and M7 and M8 (BB-). In order to quickly switch ON and OFF the MOSFETs and obtain adequate amplitudes of the even harmonics, a non-50% duty cycle square-wave LO signal is required. As shown in Fig. 2.14, by cascading 90. (LO90) and 270. LO (LO270) switches with 0. (LO0) and 180 LO (LO180). switches, respectively, the input RF signal behaves as if it is mixed with an LO signal with a non-50% duty cycle. Hence, this topology generates the even harmonics required for the mixing operation and enables the use of square-wave LO signals for. 15.

(28) good noise performance.. 2.5 Summary DC-offset issue is the most serious issue in direct-conversion receiver. Due to the frequency planning, this issue is slightly in heterodyne receiver and low-IF receiver. From Fig. 2.5, the harmonic mixer which is free from DC-offset issue seems to be one of solution for direct-conversion to overcome DC-offset. With this faith, the research will focus on direct-conversion harmonic mixer.. 16.

(29) Fig. 2.1 Direct conversion receiver architecture. ω. RF. ω LO = ω RF. ω BB = 0. Fig. 2.2 Frequency conversion of direct conversion receiver. 17.

(30) cosω LO t. cosω LO t. Fig. 2.3 Self-mixing of (a) LO signal, (b) a strong interferer. Reflected Amplified LO Signal. DC Offset. AMP Reverse LO Leakage Isolation. LO Signal. Fig. 2.4 Self-mixing due to LO leakage 18.

(31) RF Signal LO Leakage. f = f RF. BB Signal. DC Offset. f LO = f RF. BB Signal. RF Signal LO Leakage. f LO =. f RF 2. f =0. f = f RF. 2 f LO. f =0. LPF. f = f LO. Fig. 2.5 DC-Offset issue of (a) the conventional mixer (b) the second harmonic mixer. freq = f RF. freq =. 1 f RF n. n = 2.3........ Fig. 2.6 Work principle of harmonic mixer 19.

(32) cosω 0 t. Fig. 2.7 DC-Offset compensation. Fig. 2.8 Heterodyne receiver. 20.

(33) ωIF ω RF. ωIF. ωLO. ω IM. ω. ωIF ωLO. ω IF = ω LO − ω RF = ω IM − ω LO. Fig. 2.9 Frequency planning. Fig. 2.10 Feedthrough caused by substrate loss. 21. ω.

(34) f ≠0. f LO ≠ f RF. Fig. 2.11 Low IF receiver. f = f RF. f LO f RF. f LO = f RF. f LO. f =0. f = 0 f IF. Fig. 2.12 DC-offset issue of (a) direct conversion receiver (b) low IF receiver 22.

(35) Fig. 2.13 A 900MHz balanced harmonic mixer. Fig. 2.14 A 2GHz even harmonic mixer. 23.

(36) Chapter 3 A 5.2GHz Direct-Conversion Step-Gain Harmonic Mixer. 3.1 Motivation We have introduced the DC-offset issue in direct-conversion receiver in section 2.1.1. From section 2.1.3 and Fig. 2.5, they show that the LO self-mixing problem in the direct-conversion receiver arises due to the situation that the LO signal resides at the same frequency as the RF signal. As DC-offset can’t be easily filtered out without removing any base-band signal because most modulation schemes contain significant DC and low frequency components. In section 2.1.3, it also shows that the harmonic mixer architecture resolves the DC-offset issue which the LO frequency is just at the half of RF frequency. This architecture is the most suitable solution of DC-offset issue because of needing no compensation circuits.. In this chap, a harmonic mixer with. step-gain function is introduced and implemented in 0.18. m CMOS process.. 3.2 Analysis of the Step-Gain Harmonic Mixer The CMOS step-gain harmonic mixer is shown in Fig. 3.1 This harmonic mixer is composed of three parts: (1). harmonic generation stage; (2). mixing stage and injection current source, and (3). gain tuning stage.. 24.

(37) 3.2.1 Harmonic Generation Stage The harmonic generation stage consists of transistors MLO+ and MLO-. The second harmonic is obtained by the inherent square-law operation of the transistor. Each NMOS I/V curve can be shown as power series:. I _ LO + = a0 + a1. Vin V2 V3 V4 + a2 in + a3 in + a4 in 2 4 8 16. (3.1). Vin V2 V3 V4 + a 2 in − a3 in + a 4 in 2 4 8 16. (3.2). I _ LO − = a 0 − a1. I _ har = ( I _ LO +) + ( I _ LO −) = 2a0 + a2. = ( 2 a0 +. Vin2 V4 + a4 in 2 8. 1 3 a2 + a4 ) + (a2 + a4 ) cos 2ωt + a4 cos 4ωt 2 4. (3.3). (3.4). Where Vin = cos ωt . Equation (3.4) shows that in drain combined point of transistors MLO+ and MLO- . The odd harmonic of both transistors is canceling because of the differential signal input. In reference paper [6], both transistors are operating in saturation region. Equation (3.4) can be rearranged to be a square-law equation: I _ har = ( I _ LO +) + ( I _ LO −). =. V V 1 K (Vg + in cos ωt − Vt ) 2 + (Vg − in cos ωt − Vt ) 2 2 2 2. = K (Vg − Vt ) 2 +. Vin2 KVin2 + cos 2ωt 8 4. 25. (3.5).

(38) where K = µ nCOX. W . L. As Vg is the gate bias of both transistor, Vt is the threshold voltage, µ n is the mobility of NMOS, COX is the gate capacitance and W/L is the width/length ratio of the transistor. In short channel devices, square-law operation is weakened due to velocity saturation phenomenon. In long channel devices (without velocity saturation):. ID ≈. µ n COX W 2. gm = g m' =. L. (VGS − Vt )2. (3.6). ∂I D µ C W = n OX (VGS − Vt ) ∂ VGS L. µ nCOX W. (3.7). (3.8). L. In short channel devices (with velocity saturation):. ID ≈. gm =. g m' =. µnCOX. W (VGS − Vt )2 V − Vt L 2 1 + GS εC L. (3.9). ∂I D 1 µ C W (VGS − Vt ) 2 + 2K = n OX V − Vt ∂VGS 2ε c L (1 + VGS − Vt ) 2 (1 + GS ) εcL εcL. (3.10). 1 1 µ nCOX W 2 (VGS − Vt ) 2 VGS − Vt +2 + 2(1 + ) − Vt − − V V V V V 2ε c L ε c L (1 + GS ε c L (1 + GS t ) 2 t 3 ) (1 + GS ) εcL εcL εcL. 26.

(39) (3.11) As equation (3.8), the gm’ is equal to a2 in power series. In long channel device, the square characteristic lets the a2 as a constant. In short channel device, assume the velocity saturation is large, the. V − Vt VGS − Vt term >>0, then term is large. Let GS εcL εcL. the gm’ in equation (3.11) is zero. That means the I/V curve is linear, and the second harmonic is unapparent. To generate higher second harmonic component level, a current source and a capacitor are connected to both MLO+ and MLO- transistor’s source terminals. Both transistors operate as switches and capacitor bypass the even order harmonics. In this operation point, the second harmonic level would be enhanced greatly. Fig. 3.2 shows the 2nd harmonic/DC ratio curve of MOS. The dot line is the MOS which is working in saturation region and solid line is the proposed swich-like CMOS pair. The dot line in Fig. 3.2 shows that 2nd harmonic is degraded with Vgs and the proposed harmonic generation generates larger 2nd harmonic than former. It also shows that the 2nd harmonic is large in low Vgs voltage. To consider the biasing condition of Fig. 3.3 (a), if the Vgs is biased in low voltage such as 0.6V in 0.18um process, with the injection of large LO power, the Vgs is swing with LO voltage. The 2nd harmonic is not a constant, and is low when effective Vgs is large. This is because 27.

(40) that the source of MOS pair is connected to ground and Vgs is decided by gate voltage of MOS. To solve this issue, a proposed solution is brought out as Fig 3.3 (b). A current source is connected between common source point and ground. With floating Vs, the overdrive of Vgs is a constant and Vs is swing with Vg. By adjust current source, a proper Vgs is chosen for high 2nd harmonic/DC ratio. In consideration of odd harmonics of LO, the common source point is virtual ground. In consideration of even harmonics, the common source is high resistance. This will degrade the 2nd harmonic as source degeneration. By connected a bypass capacitance, the source degeneration is cancelled and the 2nd harmonic will be enhanced. Above all, the harmonic generation stage is actually a squaring cell which converts the differential LO voltage to the time-varying current which contains the second harmonic. The fundamental and all odd harmonics of the MLO+ and MLO- drain current are cancelled at the connected drain terminal. Fig. 3.4 shows both MLO+ and MLO- transistor’s drain current and the total current Ihar at the connected point.. 3.2.1.1 Define Harmonic/DC Ratio. For quantifying the second harmonic enhancement, we define a harmonic/DC ratio R.. 28.

(41) R=. I 2thHarmonic I DC. (3.12). In the same biasing current, operating both MLO+ and MLO- in saturation region the harmonic/DC ratio is about 10%. In this work, operating both MLO+ and MLO- in switch-like operation point, the harmonic/DC ratio is 34%. It is three times more than former one. The conversion gain will increase greatly with this scheme.. 3.2.2 Mixing Stage In the mixing stage, the differential radio frequency (RF) signal from gate of MRF+ and MRF- and the second harmonic from both sources are mixed and the RF signal is down-converted to base-band. In noise analysis, the flicker noise of MRF+ and MRF- dominate the output noise power level. From flicker noise equation. g m2 K i = ⋅ ⋅ ∆f f WLCox2 2 n. ≈. (3.13). K ⋅ ωt2 ⋅ A ⋅ ∆f f. (3.14). From equation (3.13):. i n2 =. ∆f 2 KI ⋅ 2 2 f L C ox. (3.15). 29.

(42) Where K is a device-specific constant,. f. is the frequency,. gm. is the. trans-conductance of transistor, W/L is transistor’s width/length, COX is the gate capacitance, ωt is the cut-off frequency, A is the gate area of transistor and I is the DC current of the transistor. In equation (3.15), it shows that the flicker noise current of transistor is direct proportion to DC current and the inverse of the square of length. Increasing the transistor length and decreasing the bias current of transistor decreases flicker noise. Because that noise figure inverses to conversion gain, the transistor length must be optimized for noise performance. In this work, the length is increase to 0.35. m for. decreasing flicker noise. The purpose of the injected current is to reduce the biasing current of MRF+ and MRF-. In equation (3.15), it reduces the flicker noise of the transistor pair MRF+ and MRF-, which is the main noise contributor. The injected current itself will not introduce noise in this balanced structure. Unlike the Gilbert-Cell mixer, the two RF transistors change their current simultaneously and any noise at their common source node will be completely cancelled out at the differential output. At the same time, the RL can be increased to raise the mixer conversion gain but not influences output third order inter-modulation interrupt point (OIP3) too much. Adjust RL could tune the conversion gain to our prefer value. 30.

(43) 3.2.3 Gain Tuning Stage In the gain tuning stage, the second harmonic current flows through the peaking inductor and the parallel NMOS switch MSW . Reference papers [8] [9] introduce the inductive peaking LNA architecture with high gain benefit. In this stage, inductive peaking architecture is adopted for higher second harmonic level, and with a parallel switch for gain tuning. As NMOS switch turn off (VSW is connected to ground), the peaking inductor and loading from the other two stages form a third-order filter with peaking effect as shown in Fig. 3.5 (a):. V peak = I har ×. 2. s C R C P ( sL peak. 1 RSW ) + sC L ( sL peak RSW )G + s(C P + C L ) + G 3.16). if. RSW >> sL peak. V peak = I har ×. then. 1 s C R C P L peak + s C L L peak G + s (C P + C L ) + G 3. 2. (3.17). Where CL is the effective load capacitance looking into the harmonic stage, and CP /G are the effective load capacitance/ admittance looking into the mixing stage. Fig. 3.6 shows the current flowing to mixing stage is amplified by inductive peaking. The peaking frequency is in 5.2GHz and it means the second harmonic signal at 5.2GHz is peaked up maximum when it flows across this stage. In this condition, it’s called that. 31.

(44) mixer is operating in the high-gain mode. In the high-gain mode, the third-order filter peaking at 5.2GHz makes the frequency response sharper and filters out the higher order harmonics which degrade the output spectra. As NMOS switch is turn on, the peaking inductor parallel with a small turn-on resistance as showed in Fig. 3.5 (b).. V peak = I har ×. if. s C R C P ( sL peak. RSW ≈ 0. V peak = I har ×. 2. 1 RSW ) + sC L ( sL peak RSW )G + s(C P + C L ) + G. (3.18). then. 1 s (C P + C L ) + G. (3.19). When turn-on resistance RSW is small, the term ( sL peak Rsw ). is nearly zero. The. third-order filter turns into a first-order low pass filter (LPF) with a pole at frequency freq =. G , and suppress the second harmonic. It seems that the inductance 2π (C P + C P ). peaking effect is eliminated by the small resistance. The simulation result of turn-on MSW is showed in Fig. 3.6. The second harmonic will not be peaked across this stage. In this operating condition, the harmonic mixer is working in the low-gain mode. With the inductance peaking scheme and a parallel switch, the gain tuning stage provides two gain modes in this work. This will ensure the mixer to operate in larger input dynamic range.. 32.

(45) 3.2.3.1 Quantify the Step Gain. In chapter 3.2.1.2, we define the harmonic/DC ratio. As equation (3.12), this ratio is direct proportion to conversion gain. In gain tuning stage, the gain step is associated with the ratio. With MOS switch turn-on, the second harmonic is suppressed by low-pass filter and the ratio is around 34%. In the other condition, pass though the third order low-pass filter with peaking, the second harmonic is amplified and the ratio is around 96%. This is nearly 2.8 times than former. Assume the impedance looking into mixing stage is constant, the voltage sweep ratio is equal to current sweep ratio. Then the gain step is: Gain step = 20 log. R2 = 20 log 2.8 = 8.9(dB) R1. (3.20). In simulation result, the gain step is 9.3dB. This approaches to the calculation result (3.20).. 3.3 Discussion on Simulation and Measurement Result This section lists the simulation and measure result of the step-gain harmonic mixer. The simulation is done by Agilent advanced Design System (ADS) and post simulation by ADS Momentum.. 33.

(46) 3.3.1 Measurement Consideration The measurement of this chip is a question. With the restriction of measurement instruments, some of the data of measure results must be got indirectly. The first is consideration is that while RF signal transfers to base-band, the down-conversion mixer is high impedance in base-band output. Because the base-band circuit such as analog-to-digital converter (ADC) or variable gain amplifier (VGA) is high input impedance, the output of mixer could be design in high impedance for larger conversion gain. There is a question: the input impedance of the measure instruments is 50. Is. it influences the measure results of device-under-test (DUT)? In AC consideration, the large output resistance is parallel with 50 , and the effective loading is dominates by instrument loading. It influences the DUT performance greatly. For measuring the DUT without degrading it, output buffer is added between DUT and instrument. One way is added buffer circuit such as common drain transistor and implements on-chip. Shown in Fig. 3.7, the buffer circuit consuming large current and the input capacitor degrade the DUT input matching greatly by miller-effect. The following question is how to de-embed the testing circuit without adding another buffer circuit? The measurement way of this chip is added a unit-gain buffer amplifier between DUT and instrument, shown in Fig. 3.8. Because that the DUT output is differential end, a differential-to-single end unit-gain buffer is adopted. Trading off between influence to DUT and thermal noise of resistor, the 8.2K. resistor for. differential amplifier is adopted. The output of amplifier is series with 49.9. for. matching with instrument. As shown in Fig. 3.8, the point A is the real output voltage 34.

(47) of the DUT and the measurement result is the point B. The power difference of point A and B is 6dB and we could get the real output results by measurement results.. 3.3.2 Chip Implementation Fig. 3.9 shows the microphotograph of the step-gain harmonic mixer circuit. The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area including bonding pads is 0.906 mm by 0.508 mm. Careful layout is observed in order to maximize performance. The layout is done in a uni-directional fashion, i.e. no signal returns close to it origins, to avoid coupling back to the input. For the layout consideration, the RF-LO ports isolation is the first consideration and places these ports opposite of the chip to improve port-to-port isolation and enhance DC-offset cancellation scheme. The RF port, which the signal level is less than LO port, crosses the IF port vertically and decreases the overlap area to minimize the couple of both ports. The layout is placed symmetrically to minimize the mismatch of the differential signal. In order to minimize the effect of substrate noise on the system, a solid ground plane, constructed using a low resistive metal-1 material, is placed between the signal pads (metal-6 and metal-5) and the substrate.. 35.

(48) 3.3.3 Simulation and Measurement Result The simulation and measure result is listed in TABLE I. Though the DC current is 2.2mA, similar to simulation, the conversion gain is -5dB in high gain mode (HGM) and -6.5dB in low gain mode (LGM) which is 23dB and 15dB lower than simulation result in HGM and LGM. The conversion gain and IIP3 are shown in Fig. 3.10 and Fig.3.11. Because of the conversion gain is lower than expect, the IIP3 is large than simulation. The input matching is measured and showed in Fig. 3.12. The solid line is the measured data and dot line is the simulation result. The trouble shooting is described following. First, the second harmonic of a single LO MOS is lower than simulation as shown in Fig. 3.13(a) and Fig. 3.13(b) as the circuit is connected as Fig. 3.14. Though the parallel 50. resistor will degrade the mixer gain performance, we can check the. second harmonic of LO in IF port and compare to simulation and find out the reason why conversion second harmonic gain degrades so much. In Fig. 3.13 (b), the second harmonic tone will be set in -27dBm in simulation which is 7dB higher than testing result as the same schematic. That means the second harmonic may be lower than simulation.. Process S11 DC current Conversion Gain Noise Figure IIP3. TABLE I Simulation and measure result of the first chip Simulation Result Measure Result High Gain Low Gain High Gain Low Gain Mode Mode Mode Mode 0.18u < -20 dB < -15 dB 2.6mA 2.2mA. 18.0 dB. 8.7 dB. -5 dB. -6.5 dB. 16.0 dB -3.1 dBm. 25.7 dB -5.6 dBm. 8 dBm. 9 dBm. 36.

(49) Focusing on harmonic generation stage, it is combined by current source and switch-like differential pair. Fig. 3.15 shows the in bias point of 0.7V, the biasing MOS is working in saturation region as simulation. As Vbias adding over 0.75V, the biasing MOS will operation in triode region because of the drain voltage is restricted by VLO. From Fig. 3.15, the assumption that the biasing MOS is working in right operation region is well. The measurement and simulation result of inductive peaking is shown in Fig. 3.16. The testing circuit is connected the same as measurement of conversion gain, and the buffer amplifier is connected. As RF frequency and LO frequency is change the same time. The down conversion IF frequency is located at the same frequency (3MHz). The measure result and simulation in the same frequency band are shown in Fig. 3.16 (a). It shows that the inductive is shift to lower frequency in simulation result, but the discrepancy in 3.9GHz to 6GHz is small. The measurement result seems to be influenced by RF and LO input matching. Fig. 3.16 (b) is the simulation in wider frequency range, and the inductive peaking is clear. It shifts to lower frequency slightly, and don’t degrade performance greatly. To make a conclusion, the inductive peaking is moving to lower frequency because of the board. The switch-like harmonic generation scheme may not take effect as simulation and the second harmonic is much lower than simulation result. This is the reason why conversion gain is much lower than we except.. 3.4 Conclusion It seems that inductive peaking for gain tuning takes effect well. As the second harmonic is less than expected. The conversion gain is lower than simulation result. It 37.

(50) looks like that the differential pair working between cut-off and triode region may generate lower second harmonic than expected. The phase and amplitude of differential LO input degrade the odd harmonic cancellation largely.. 38.

(51) RL. RL. stage. VB1. IF+. Mixing. RF+. IF-. I_inject. MRF+. VB2. MRF-. RF-. V_peak. Vsw. MSW. Lpeak I_har. Harmonic generation. I_LO+. LO+. Gain tuning stage. I_LO-. LOMLO-. MLO+. Vbias. Cbypass. stage Figure 3.1 CMOS harmonic mixer with current injection. ---SAT region Proposed way Figure 3.2 The 2nd harmonic/DC ratio of a single MOS with Vds=1V 39.

(52) Figure 3.3 Harmonic generation stage (a) without current source (b) with current. !. ". source. Ihar I_LO+ I_LO-. Figure 3.4 Harmonic generation stage current. 40.

(53) Lpeak Ihar. Rsw Vpeak Ihar. C L Cp. Vpeak. Lpeak C L Cp. G. (a). G. (b). Figure 3.5 Small signal model of peaking inductor and parallel NMOS switch (b) switch on. ' (). *+. ". (a) switch off. turn off turn on. # $ % &. Figure 3.6 Inductance peaking effect (Vpeak/Ihar). 41.

(54) Figure 3.7 Implement buffer in chip. Figure 3.8 testing circuit. 42.

(55) Figure 3.9 Microphoto of chip on board. Figure 3.10 Conversion gain and IIP3 in HGM. 43.

(56) ,. *+. Figure 3.11 Conversion gain and IIP3 in LGM. !!. # $ % &. Figure 3.12 Simulation and measure result of S11. 44. !!-.

(57) . ! *+. Figure 3.13 (a) Spectra in IF+. # $ % &. Figure 3.13 (b) Simulation Result in IF+. 45.

(58) Figure 3.14 Harmonic testing of IF port. Figure 3.15 The bias current v.s bias voltage. 46.

(59) ! *+. Figure 3.16 (a) Measurement of inductive peaking. /# # $ % &. Figure 3.16 (b) Simulation of inductive peaking. 47.

(60) Chapter 4 A. 2.45/5.2GHz. Dual-Band. Low-Power. Direct-. Conversion Harmonic Mixer. 4.1 Motivation Multi-standard radio-frequency (RF) receivers are predicted to play a critical role in wireless communications in the 900-5200MHz range. With cellular and cordless phone standards operating in the 900MHz and 1.8GHz band, the Global Positioning System (GPS) in the 1.5GHz band, and wireless local area networks (WLAN) 802.11b in the 2.4GHz band and 802.11a in 5.2GHz band, it is desirable to combine two or more standards in one mobile unit [10]. The wireless communication specifications 802.11a and 802.11 utilizing different frequency could be merged in single front-end and share a single digital signal processor. In this chapter, a 2.45GHz/5.2GHz dual-band, low-power direct-conversion harmonic mixer is designed and manufactured in tsmc 0.18 CMOS process.. 48. m.

(61) 4.2 Design Consideration Fig. 4.1 shows the conceptual example of a dual-band receiver. The receiver contains two antennas, two LNAs and two mixers. Thought the radio-frequency (RF) front-end contains two independent paths, the analog circuit and digital signal processor (DSP) could be combined and decreases the power consumption and cost. In recently research, the dual-band RF front-end is implemented in a single path (Fig. 4.2). The dual-band LNA is designed for both bands and amplifies both signals concurrent. In most operation condition, only one of the bands receives RF signal and the other signal path is unused. That means the mixer must design with concurrent input matching and only one of the bands will be transferred to output. With this conception, this mixer is designed in concurrent dual-band input matching and down-converting one of the receiving band to base-band which system needs. The conception of Fig. 4.2 will be implemented with this mixer, and the RF front-end circuit could be designed in a single path.. 4.3 Analysis of the Dual-Band Low-Power Harmonic Mixer The CMOS dual-band harmonic mixer is shown in Fig. 4.3 This harmonic mixer is composed of three parts: (1) harmonic generation stage; (2) mixing stage, and (3). 49.

(62) frequency tuning stage.. 4.3.1 Harmonic Generation Stage The harmonic generation stage is following section 3.2.1. For low power design, the biasing current is set as half of former design. By a current source, the Vgs of LO MOS is restricted in lower voltage for higher second harmonic.. 4.3.1.1 Define Harmonic/DC Ratio. For quantifying the second harmonic enhancement, the harmonic/DC ratio R (3.12) in section 3.2.1.1 is used. In the same biasing current, operating both MLO+ and MLO- in saturation region the harmonic/DC ratio is about 10%. In this work, operating both MLO+ and MLO- in switch-like operation point, the harmonic/DC ratio is 35%. It is three times more than former one. The conversion gain will increase greatly with this scheme.. 4.3.2 Mixing Stage The design of this stage is following as section 3.2.2. The bias current flowing to 50.

(63) both RF MOS is set similar as former for linearity consideration. That means, the injection current is lower than former.. 4.3.3 Frequency Tuning Stage In the frequency tuning stage, the second harmonic current flows through the peaking inductor and the parallel NMOS switch MSW . Reference papers [8] [9] introduce the inductive peaking LNA architecture with high gain benefit. In this stage, inductive peaking architecture is adopted for higher second harmonic level, and with a parallel switch for frequency tuning. As NMOS switch turn off (VSW is connected to ground), the second harmonic of LO will flow into inductor L1+L2. As shown in Fig. 4.4 (a), the inductor and loading from the other two stages form a third-order filter with peaking effect. As equation (4.2), the large inductance L1+L2 will form a third order low-pass-filter with peaking frequency in lower frequency. It means that the mixer is operating in low frequency mode. As shown in Fig. 4.5 dot line, all of the frequency except frequency near 3GHz will be filtered out by frequency selection effect, and only low-side band of RF input will down-convert to base-band.. 51.

(64) V peak = I har ×. 1 s C R CP ( sL1 + ( sL2 RSW )) + sCL ( sL1 + ( sL2 RSW ))G + s (C P + CL ) + G 2. 4.1) if. RSW >> sL2. V peak = I har ×. then. 1 s C R C P ( L1 + L2 ) + s C L ( L1 + L2 )G + s (C P + C L ) + G 3. (4.2). 2. Where CL is the effective load capacitance looking into the harmonic stage, and CP/G are the effective load capacitance/admittance looking into the mixing stage. As NMOS switch turns on, the peaking inductor L2 parallel with a small turn-on resistance as shown in Fig. 4.4 (b). The small signal equation will be:. V peak = I har ×. 1 s C R CP ( sL1 + ( sL2 RSW )) + sCL ( sL1 + ( sL2 RSW ))G + s (C P + CL ) + G 2. (4.3). if. RSW ≈ 0. V peak = I har ×. then 1 s C R C P L1 + s C L L1G + s(C P + C L ) + G 3. 2. When turn-on resistance RSW is small, the term ( sL2 Rsw ). (4.4). is nearly zero. The. third-order filter will be peaked by inductor L1 and the peaking frequency will be in higher frequency than that in switch off. As shown in Fig 4.5 solid line, the band-pass -filter will filter out all frequency except frequency near 5.2GHz, and only up-side band of RF input will down-convert to base-band. In this operation mode, the mixer is 52.

(65) working in high frequency mode. With the inductance peaking scheme and a parallel switch, the frequency tuning stage provides two frequency modes in this work. By frequency selection of the inductive peaking effect, the mixer decides one of the RF input band will be transferred to base-band. By this mixer, the conception of Fig. 4.2 will be implemented.. 4.3.3.1 Quantitate the Gain Enhancement. In chapter 3.2.1.2, we define the harmonic/DC ratio. As equation (3.12), this ratio is direct proportion to conversion gain. In gain tuning stage, the gain step is associated with the ratio. With MOS switch turn-on, the third-order low-pass filter will be peaked in 2.45GHz, the second harmonic of 1.225GHz LO frequency. The second harmonic of 1.225GHz is peaked by low-pass filter and the ratio is around 89%. This is nearly 2.5 times than former without inductive peaking. In the other condition, pass though the third order low-pass filter which is peaked in 5.2GHz, the second harmonic of 2.6GHz LO frequency is amplified and the ratio is around 96%. This is nearly 2.7 times than that without inductive peaking.. 53.

(66) 4.4 Simulation and Measure Result This section describes the simulation and measure result of the step-gain harmonic mixer. The pre-simulation is done by Agilent advanced Design System (ADS) and post EM-simulation is done by ADS Momentum.. 4.4.1 Chip Implementation Fig. 4.6 shows the microphotograph of the dual-band harmonic mixer circuit. The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area including bonding pads is 0.795mm * 0.683mm. Careful layout is observed in order to maximize performance. The layout is done in a uni-directional fashion, i.e. no signal returns close to it origins, to avoid coupling back to the input. For the layout consideration, the RF-LO ports isolation is the first consideration and places these ports opposite of the chip to improve port-to-port isolation and enhance DC-offset cancellation scheme. The RF port, which the signal level is less than LO port, crosses the IF port vertically and decreases the overlap area to minimize the couple of both ports. The layout is placed symmetrically to minimize the mismatch of the differential signal. In order to minimize the effect of substrate noise on the system, a solid ground plane, constructed using a low resistive metal-1 material, is placed between the signal pads (metal-6 and metal-5) and the substrate.. 54.

(67) 4.4.2 Simulation and Measurement Result The simulation and measure result is listed in TABLE II. Because the 1.225GHz balun is unavailable, we can not measure the 2.45GHz band now. Though the DC current is similar to simulation, the conversion gain is 39dB lower than simulation result. The conversion gain and IIP3 plot is showed in Fig. 4.7. Because most of IM3 is under noise floor, the IIP3 is gained by equation (4.5). IIP3 dBm =. ∆P dB. 2. + Pin. (4.5). dBm. Because that the harmonic generation stage is the same with former, the lower second harmonic is poor to driver RF MOS. With injection current nearly to zero, the conversion gain is negative. The 5.2GHz input matching is measured and showed in Fig. 4.8. Because that the input balun is narrow band, the input matching is measured separately. The solid line is the measured data and dot line is the simulation result.. TABLE II. Band. Simulation result and measure result of the second chip Simulation Result Measure Result. 2.45GHz. < -12 dB. 16.7 dB. 18.9 dB. Noise Figure. 15.5 dB. 13.5 dB. IIP3. -6.0 dBm. -1 dBm. Gain. 5.2GHz. 1.15 mA. < -11 dB. Conversion. 2.7 GHz. 1.28 mA. DC current. S11. 5.2GHz. -12 dB. -13 dB. -21 dB. 18 dBm. The measurement result of inductive peaking is shown in Fig.4.9. The testing circuit is connected the same as measurement of conversion gain, and the buffer amplifier is connected. As RF frequency and LO frequency is change the same time. The down conversion IF frequency is located at the same frequency (3MHz). The 55.

(68) peaking frequency shifts to lower frequency as plot.. 4.5 Conclusion As showed in chapter 3, the differential pair working between cut-off and triode region may generate lower second harmonic than expected. In this work, the lower injection current for current reusable let the harmonic/DC ratio too low to drive the RF MOS and the inductive peaking is moving to low frequency. It makes the conversion gain is degraded substantially.. 56.

(69) Figure 4.1 Conceptual example of a dual-band receiver. Figure 4.2 Conceptual example of a concurrent dual-band receiver. 57.

(70) Figure 4.3 Dual-band low-power harmonic mixer. Figure 4.4 Small signal model of peaking inductor and parallel NMOS switch (a) switch off. (b) switch on. 58.

(71) " *+ ' (). # $ % &. Figure 4.5 Inductance peaking effect (Vpeak/Ihar). Figure 4.6 Chip implement 59.

(72) ,. *+. Fig 4.7 Conversion Gain and IIP3. , !0 ! # $ % &. Figure 4.8 Input matching in 5.2GHz band. 60.

(73) Figure 4.9 Measurement result inductive peaking in 5.2GHz band. 61.

(74) Chapter 5 Summary and Future Works 5.1 Summary In the chapter 2, the DC-offset of direct-conversion, heterodyne and low IF receivers are presented. The DC-offset issue is an intrinsic problem of direct-conversion receiver because of frequency planning. In the last of chapter 2, the harmonic mixer is mentioned and it seems a way to solve this issue. Besides the DC-offset consideration, two harmonic mixers are introduced. The RF signal is mixing with the second harmonic of LO signal. Both of they are influenced by low linearity. In the chapter 3, a step-gain harmonic mixer using inductive peaking scheme and switch-like harmonic generation stage is analyzed and implemented in a standard 0.18um CMOS process. Although, measured result show that the conversion gain is lower than simulation, the switch-able inductance peaking scheme for step-gain takes effect as simulation. The trouble shooting is showed in last of chapter 3. Measured data still show that the mixer achieves -15 dB input return loss (S11), while consuming 2.2mA DC current. In the chapter 4, a dual-band low-power harmonic mixer, intended for use in the receiver path of 802.11a/b system is designed in a standard 0.18um CMOS process. With the same harmonic generation stage as former, the conversion gain is less than simulation result.. 62.

(75) 5.2 Future Works Although some measure results are showed in this thesis, the measurement and trouble shooting of these chips still continues. The drilled PCB board introduces some problem such as leakage and signal loss. Since the bias voltage is fed by a large resistance as RF choke, any leakage will degrade the bias voltage. It should be considered to seek a proper PCB board for testing.. 63.

(76) REFERENCES [1] Abidi, A.A., “RF CMOS come of age,” VLSI Circuits, 2003, Digest of Technical Papers, pp.113-116, June, 2003. [2] Razavi, B. RF Microelectronics, Prentice Hall PTR, 1998. [3] Razavi, B., “Design considerations for direct-conversion receivers”; Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, pp.428-435 June, 1997.. [4]Yamaji T. and Tanimoto H., “A 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers,” Proc. of IEEE custom IC Conf., pp.193-196, May, 1997. [5]Yamaji, T.; Tanimoto, H., and Kokatsu, H., “An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter,” IEEE J. Solid-State Circuits, vol.33, pp.2240-2246, Dec. 1998. [6] Z. Zhang, Z. Chen and J. Lau, “A 900MHz Balanced Harmonic Mixer for Direct Conversion Receivers,” Proc. IEEE RAWCON2000, pp.219-222, Sept. 2000. [7] S. J. Fang, S. T. Lee, and David J. Allstot, “A 2GHz CMOS Harmonic Mixer for Direct-Conversion Receivers,” ISCAS 2002, vol.4, pp.IV-807-IV-810, May 2002. [8]C. Y. Cha, and S. G. Lee, “A low power, high gain LNA topology,” Microwave and Millimeter Wave Technology, 2000, 2nd International Conference on. ICMMT 2000, pp.420-423, Sept. 2000.. [9] Huang, J.C., R. M. Weng, C. C. Chang, K. Hsu and K. Y. Lin, “A 2 V 2.4 GHz fully integrated CMOS LNA,”. Circuits and Systems, ISCAS 2001. vol.4, pp.466-469, May. 2001. [10]T. Antes and C. Conkling, “RF chip set fits multimode cellular/PCS handsets,” Microwaves RF, pp.177-186, Dec. 1996. 64.

(77) (Shang-Yi Liu). (84. 9. ~87. 6. ). (87. 9. ~91. 6. ). (91. 9. ~93. 10. PUBLICATION LIST [1]. Shang-Yi Liu and Chien-Nan Kuo, "A 5.2GHz Direct-conversion Step-gain Harmonic Mixer," VLSI/CAD Symposium, 2004.. 65. ).

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