Chapter 1 Introduction
1.2 Thesis Organization
In the Chapter 2 of the thesis, the DC-offset issue in different receiver architecture is introduced. Although in direct-conversion receiver, this issue is the most important problem to overcome. Two harmonic mixers are introduced. Based on the first harmonic mixer, two harmonic mixers in this these is designed and measured in following chapter.
In Chapter 3, a narrow band harmonic mixer using inductance peaking topology intended for application of the 5.2GHz wireless direct-conversion receiver is introduced. The detailed circuit analysis and design equation is presented. The odd-harmonic cancellation scheme and the second harmonic enhancement by inductance peaking are also discussed. Finally, measurement result of the mixer fabricated by TSMC 0.18um CMOS technology is discussed.
In Chapter 4, a 2.45/5.2-GHz dual-band low-power harmonic mixer intended for 802.11a/b system is proposed. The switchable inductance peaking scheme is adopted for switching frequency. Based on chapter 3, the harmonic mixer is designed in lower power and two bands input matching. Finally, measurement result of the mixer fabricated by TSMC 0.18um CMOS technology is discussed.
In the last chapter, all the work is summarized and concluded.
Chapter 2
DC-Offset Issue in RF Receiver
In this Chapter, the DC-offset issue is analyzed in different situations. DC-offset issues in direct-conversion receivers are analyzed in section 2.1. In this section, the DC-offset issue would be discussed about how the DC-offset influence the direct- conversion receiver and how to avoid or release it. It also shows the DC-offset-free characteristic of the harmonic mixer. DC-offset issue would be discussed in low-IF receiver and in heterodyne receiver in section 2.2 and section 2.3. In these sections, they show the DC-offset issue is migrated cleverly by the architecture design but these architectures induce other issues at the same time.
2.1 Direct-conversion Receiver
The direct-conversion receiver (DCR) [Fig. 2.1] is also called “homodyne” or
“zero-IF” architecture because that the RF signal transfers to output and is down- converted to zero-frequency. Shown in Fig. 2.2 is a simple frequency conversion of DCR, where the local oscillator (LO) frequency is equal to the input radio frequency (RF) carrier and the channel selection requires only a low-pass filter with relatively sharp cutoff characteristics [2]. This architecture was invented many decades ago, and was improved greatly in recent years. The reasons that this architecture has recently become the topic of active research, perhaps to a much greater extent than before are accounted for this renaissance:
subsequent down-conversion stages are replaced with low-pass filters, in principle, lends itself to monolithic integration much more easily than heterodyne receivers;
(2). The problem of image is circumvented because of ωIF =0. As a result, no image filter is required, and the LNA need not drive a 50- load for off-chip SAW filters;
(3). Direct-conversion architecture’s past failures arose primarily from effects that could not be removed in discrete implementations, but may be controlled and suppressed in integrated circuits.
In other words, direct-conversion architecture is one of few reception techniques whose drawbacks can be remedied through the use of only more transistors [3].
Nevertheless, the DRC direct translation of the spectrum to zero frequency entail a number of issues that do not exist or are not as serious in a heterodyne receiver. One of the most serious issues is the DC-offset issue.
2.1.1 DC-Offset Issue in Direct-Conversion Receiver
Since in the direct-conversion topology, the down-converted band extends to zero frequency, extraneous offset voltage can corrupt the signal and, more importantly, saturate the following stages. To understand the origin and impact of DC-offsets, consider the receiver shown in Fig. 2.3, where the LPF is followed by an amplifier and an A/D converter. The LPF would not decrease the DC-offset value, and it can easy saturate the following stage. The DC-offset is caused by three sources mainly.
(1). Self-mixing due to LO Leakage [Fig. 2.3(a)]:
The isolation between the LO port and the input of the mixer and the LNA is finite. This effect arise from capacitive feed-through and substrate coupling and, if the
LO signal is provided externally, bond wire coupling. The LO signal leaks into point A or point B, and is reflected at the output port of RF amplifier and at the antenna connector. The reflected LO signal is self-mixed at the mixer and results in DC-offset [4]. In most receiver architectures, the LO signal power level is much greater than RF signal power level. That means, in designing of DCR, it always considers the restriction of the mixer LO-to-RF input isolation and the low-noise amplifier (LNA) reverse isolation to avoid the base-band output with large DC-offset which will saturate the following stage. This is the main DC-offset generator in DRC architecture.
(2). Self-mixing due to large interferer in RF port [Fig. 2.3(b)]:
This is similar to former because that isolation between the LO port and the input of the mixer and the LNA is finite. The effect occurs if a large interferer leaks from the LNA and mixer LO input, point C, and is multiplied by itself to result in DC-offset.
(3). Mismatch of component:
The mismatch of differential pair also cause DC-offset in output. This can be solved by mismatch compensation circuit design.
For example: the total gain from the antenna to point X is typically around 80 to 100 dB so as to amplify the microvolt input signal to a level that can be digitized by a low-cost, low power analog-to-digital converter (ADC). Of this gain, typically 25 to 30 dB is contributed by the LNA/mixer combination.
With the above observations, we can obtain a rough estimated of the offset resulting from self-mixing to appreciate the problem. Suppose in Fig. 2.3 (a) the LO signal has a peak-to-peak swing of 0.63V (0 dBm in a 50 system) and experiences an attenuation of 60 dB as it couples to point A. If the gain of the mixer is on the order
of 10mV, we also note that the desired signal level at this point can be as low as approximately 30 Vrms. Thus, if directly amplified by the remaining gain of 50 to 70 dB, the offset voltage saturates the following circuits, there by prohibiting the amplification of the desired signal [2].
2.1.2 Quantification of Self-Mixing DC-Offset
Fig. 2.4 shows the self-mixing mechanism. The LO frequency is set at the same frequency as the received signal frequency, and the received signal is down-converted to base-band directly. The LO signal leaks to the RF signal input port of the mixer and is reflected at the output port of the low noise amplifier (LNA) and at the antenna.
The reflected LO signal is down-converted at the mixer and results in a DC-offset.
The offset voltage at the mixer output due to self-mixing V is described by self
BB amplifier output port, and GLO−BB is the conversion gain of the mixer from LO signal frequency to base-band. The RF amplifier gain is often switched depending on received signal strength. Therefore, the self-mixing output is not a stable DC-offset.
The equation (2.1) suggests three ways to reduce the offset V . The first is self reducing LO signal leakage V . The second is reducing leak Ramp. Note that the Ramp is varied depending on the electromagnetic environment of the antenna and the reverse and/or forward gains of the RF amplifier, and it is difficult to realize extremely small Ramp practice. The last is reducing the conversion gain GLO−BB. In the usual direct-conversion case, reducing conversion gain does not improve desire-
signal to undesired-signal ratio, therefore a raw output offset voltage cannot be a
describe the efficient realization of these conditions by this thesis.
For example, in a typical direct-conversion receiver, assuming the LO signal is -10dBm, -50dBm V from the RF input port (i.e. 40dB isolation), and the -14dB leak reflection factor at the RF amplifier output (VSWR≈1.5), reflected LO signal is -64dBm (140µVrms) at mixer input. This is 57dB higher than thermal noise in 200kHz bandwidth from 50 resistor.
2.1.3 To Avoid DC-Offset: Harmonic Mixer
Fig.2.5 (a) shows that the LO self-mixing problem in a DCR arises due to the
situation that LO signal resides at the same frequency as the RF signal. As DC-offset
can’t be easily filtered out without removing any base-band signal because most
modulation schemes contain significant DC and low frequency components. Because
DC-offset is caused by self-mixing of LO signal mainly, one should apparently
separate the RF and LO frequencies in order to avoid the problem.
That means: if LO frequency is separated far away from RF frequency, there is
no DC-offset problem. For the harmonic mixer shown in Fig.2.5 (b), it is the second
harmonic of the LO signal that takes part in the mixing process. In equation (2.2), the
V is zero because the LO leakage in receiving frequency in RF input is zero. As a eq
result, the LO leakage generates no DC component but an output the LO frequency
and can be easily filtered out with a low-pass filter (LPF).
Fig.2.6 shows the typical working principal of a direct-conversion harmonic
mixer. The LO frequency is just in the 1/n of RF frequency. It not only simplifies the
oscillator design consideration but solves the DC-offset issue of DCR. The CMOS
balance harmonic mixer proposed by Zhang [6] generates the second harmonic of LO
frequency by odd harmonic cancellation and mixes it with RF signal in the NMOS
pair which is operating in sub-threshold region. It adopts current injection to decrease
transistor’s current and lower flicker noise. The harmonic mixer proposed by Fang [7]
receives quadrature LO signal with two cascaded transistors and operation as a switch
at twice frequency of LO signal. These works, however, suffer from the low
third-order input intercept point (IIP3) problem and fixed conversion gain.
2.1.4 Others Way to Avoid DC-Offset
This section shows some DC-offset cancellation scheme. DC free coding and DC-offset compensation will be introduced in following paragraph.
2.1.4.1 DC-Free Coding with High Pass Filter
The base-band signal in the transmitter can be encoded such that, after modulating and down-conversing to base-band, it contains little energy near DC. With accessing a high pass filter, the DC-offset problem can be solved by wasting few of signals. Called “DC-free coding,” this is particularly suited to wideband channel, for example, in DECT, where a few kilohertz of the channel can be wasted with no significant drop in the data rate.
2.1.4.2 DC-Offset compensation
This technique exploits the idle time intervals in digital wireless standards to carry out offset cancellation. Shown in Fig.2.7 is an example, where a capacitor C1 stores the offset between consecutive TDMA bursts, while introducing a virtually zero corner frequency during the reception of data. For a typical TDMA frame of a few milliseconds, offset cancellation is performed with sufficient frequency to take into account variations due to moving objects.
2.2 Heterodyne Receiver
Fig.2.8 shows the heterodyne receiver architecture with one intermediate frequency (IF) before the RF signal down-converts to base-band. The “Heterodyne”
means that there is one or more IF before base-band signal. This is the most mature receiver design scheme today because each performance would trade of properly in each stage. The heterodyne architecture has some issues compare to homodyne architecture, such as image problem. The image reject filters require high Q and need off-chip SAW components usually. For this reason, the heterodyne receiver is hardly to cost down and applies to system-on-chip (SoC) designs.
2.2.1 Frequency planning
How to choose the LO frequency and the IF frequency? The principal consideration here is the “image problem.” To understand the issue, note that a simple analog multiplier does not preserve the polarity of the difference between its two input frequencies, i.e., for x1(t)= A1cosω1t and x2(t)= A2cosω2t, the mixer output products of x1(t) and x2(t) is the from cos(ω −1 ω2)t , no different from
t )
cos(ω2−ω1 . Thus, in a heterodyne architecture, the bands symmetrically located above and below the LO frequency are down-converted to the same center frequency [Fig.2.9] if the received band of interest is centered around ω1 (=ωLO−ωIF), then the image is around 2ωLO−ω1(=ωLO+ωIF) and vice versa.
2.2.2 DC-offset Issue
The DC-offset issue in heterodyne receiver is so slight that most papers have not make mention of it. Chapter 2.1.1 describes that DC-offset is caused by (1) Self-mixing due to LO Leakage [Fig. 2.3(a)] (2) Self-mixing due to large interferer in RF port [Fig. 2.3(b)] (3) Mismatch of components. The DC-offset which is caused by mismatch could compensation by negative feedback or digital signal process and fully calibrated. The DC-offset which is caused by self-mixing of leakage is due to the coupling effect or substrate loss between LO and RF input. The coupling effect is proportion of operation frequency. In other words, the heterodyne architecture has slight DC-offset due to coupling effect because of the lower LO frequency. Fig.2.10 is the basic substrate model. The substrate behaves as a resistor. The metal line and substrate have parasitic capacitance effect which the resistance is the function of frequency. The resistance between LO and RF input is
LO
where l is the distance between RF and LO input, Rsub is the substrate resistance per unit, CRF and CLO is the capacitance of both port to substrate. Equation (2.3) show the substrate loss between these ports is influenced by layout scheme and the frequency.
In heterodyne receiver, the frequency of the final mixing stage is less than the homodyne one’s. In most of the heterodyne architecture, the final mixing stage LO frequency has less than the one-fifth of the received signal. The DC-offset which is caused by self-mixing is direct proportion of Vleakage2 , and with this reason, the DC-offset in heterodyne receiver could be ignored.
2.3 Low IF Receiver
In the heterodyne architecture of Fig.2.8, low frequency operations such as the second set of mixing and filtering can be performed more efficiently in the digital domain. Shown in Fig.2.11 is an example where the first IF signal is digitized,
“mixed” with the quadrature phases of a digital sinusoid, and low-pass filtered to yield the quadrature base-band signal. This approach is sometimes called a “digital-IF architecture.”
This principal issue in this approach is the performance required of the analog-to-digital converter (ADC). Since the signal level at AMP output in Fig.2.11 is typically no higher than a few hundred micro-volts, the quantization and thermal noise of the ADC must not exceed a few tens of micro-volts. Furthermore, if the first IF band-pass filter cannot adequately suppress adjacent interferes, the nonlinearity of the ADC must be sufficiently small to minimize corruption of the signal by inter- modulation. Also, the ADC dynamic range must be wide enough to accommodate variations in the signal level due to path loss and multi-path fading. Additionally, the ADC must achieve an input bandwidth commensurate with the value of IF while consuming a reasonable amount of power.
2.3.1 DC-offset Issue
In low IF structure, the DC-offset issue is migrated cleverly because that the frequency of DC-offset is different to IF signal. As shown in Fig.2.12 (b). In Fig.2.12 (a), the self-mixing introducing DC-offset is in the zero frequency, while the conventional direct-conversion mixer suffers this issue because of the signal is
down-converted to zero frequency and overlaps the DC-offset in frequency. As DC-offset can’t be easily filtered out without removing any base-band signal because most modulation schemes contain significant DC and low frequency components. Low IF architecture becomes a possible solution to DC-offset, but it suffers from the complex digital process and high speed ADC to convert base-band signal from IF signal.
The low IF structure also suffers from the image problem as heterodyne receiver.
2.4 Some Reference Harmonic Mixers
In this section, some harmonic mixer is introduced. All of these are designed in the cause of DC-offset-free. Some of these is done in symmetrical, and they could increase the second-order input intercept point (IIP2).
2.4.1 900MHz Balanced Harmonic Mixer
The “A 900MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receiver” is published in Proc. IEEE RAWCON2000 [6]. It’s fabricated in a 0.35um standard digital CMOS process. In Fig. 2.13, the second harmonic is easily obtained because of the inherent square-law operation of the CMOS transistor. The LO stage is actually a squaring cell with converts the differential LO voltage to the time-varying current which contains the second harmonic. In principle, the fundamental and all odd harmonics of the LO will be cancelled out at the connected drain terminals and the DC offset problem will be mitigated.
Flicker noise is an issue in direct conversion receivers. When the transistor size is increased, however, it is found that the optimal point moves towards the weak
inversion region. To reduce the flicker noise, the RF part can be biased near this region. At a biasing current, a larger W/L ratio drives the device toward the moderate or weak inversion region.
The objective of the injected current source is to reduce the current in the two upper transistors driven by the RF signal. This helps to reduce the 1/f noise of the upper transistor pair. The injected current itself will not introduced noise in this balanced structure. Unlike the normal Gilbert-type mixer, the two RF transistors change their currents simultaneously and any noise at their common source node will be completely cancelled out at the differential output
2.4.2 2GHz Even Harmonic Mixer
Fig. 2.14 show a double-balanced version of the CMOS even-harmonic mixer; it provides down conversion mixing of the differential RF input signal with even harmonics of the LO differential signal while suppressing RF mixing with the LO fundamental and odd harmonics. This circuit is reference from ISCAS 2002 [7], and it’s fabricated in a 0.25um standard digital CMOS process. As shown, suppression of odd harmonic mixing is accomplished by summing differential signal at the drains of M5 and M6 (BB+), and M7 and M8 (BB-). In order to quickly switch ON and OFF the MOSFETs and obtain adequate amplitudes of the even harmonics, a non-50%
duty cycle square-wave LO signal is required. As shown in Fig. 2.14, by cascading 90 (LO90) and 270 LO (LO270) switches with 0 (LO0) and 180 LO (LO180) switches, respectively, the input RF signal behaves as if it is mixed with an LO signal with a non-50% duty cycle. Hence, this topology generates the even harmonics required for the mixing operation and enables the use of square-wave LO signals for
good noise performance.
2.5 Summary
DC-offset issue is the most serious issue in direct-conversion receiver. Due to the frequency planning, this issue is slightly in heterodyne receiver and low-IF receiver.
From Fig. 2.5, the harmonic mixer which is free from DC-offset issue seems to be one of solution for direct-conversion to overcome DC-offset. With this faith, the research will focus on direct-conversion harmonic mixer.
Fig. 2.1 Direct conversion receiver architecture
ω
RFω
LO= ω
RFω
BB= 0
Fig. 2.2 Frequency conversion of direct conversion receiver
LO
t ω cos
LO
t ω cos
Fig. 2.3 Self-mixing of (a) LO signal, (b) a strong interferer
AMP
LO Signal
DC Offset
LO Leakage Reflected LO Signal
Reverse Isolation Amplified
AMP
LO Signal
DC Offset
LO Leakage Reflected LO Signal
Reverse
Isolation
Amplified
RF
Fig. 2.5 DC-Offset issue of (a) the conventional mixer (b) the second harmonic mixer
fRF
Fig. 2.6 Work principle of harmonic mixer