Chapter 3 A 5.2GHz Direct-conversion Step-gain
3.4 Conclusion
It seems that inductive peaking for gain tuning takes effect well. As the second
harmonic is less than expected. The conversion gain is lower than simulation result. It
looks like that the differential pair working between cut-off and triode region may
generate lower second harmonic than expected. The phase and amplitude of
differential LO input degrade the odd harmonic cancellation largely.
Figure 3.1 CMOS harmonic mixer with current injection
Figure 3.2 The 2nd harmonic/DC ratio of a single MOS with Vds=1V
VB1 VB2
Vbias Cbypass
LO+ LO-
RF+ RF-
IF+ IF-
RL RL
Lpeak Vsw
MLO+ MLO-
MSW
MRF+ MRF-
I_LO+ I_LO- I_har I_inject
V_peak
Harmonic generation stage
Mixing stage
Gain tuning stage
---SAT region Proposed way
Figure 3.3 Harmonic generation stage (a) without current source (b) with current source
!"
Figure 3.4 Harmonic generation stage current Ihar
I_LO+
I_LO-
Figure 3.5 Small signal model of peaking inductor and parallel NMOS switch (a) switch off (b) switch on
# $ % &
'()*+"
Figure 3.6 Inductance peaking effect (Vpeak/Ihar)
Lpeak
Cp Cp
Ihar Vpeak Ihar Vpeak
(a) (b)
C
LG G
Lpeak Rsw
C
Lturn off turn on
Figure 3.7 Implement buffer in chip
Figure 3.8 testing circuit
Figure 3.9 Microphoto of chip on board
Figure 3.10 Conversion gain and IIP3 in HGM
Figure 3.11 Conversion gain and IIP3 in LGM
# $ % &
,*+
!-
!-!
!-Figure 3.12 Simulation and measure result of S11
Figure 3.13 (a) Spectra in IF+
Figure 3.13 (b) Simulation Result in IF+
# $ % &
. ! * +
Figure 3.14 Harmonic testing of IF port
Figure 3.15 The bias current v.s bias voltage
Figure 3.16 (a) Measurement of inductive peaking
/# # $ % &
!*+
Figure 3.16 (b) Simulation of inductive peaking
Chapter 4
A 2.45/5.2GHz Dual-Band Low-Power Direct- Conversion Harmonic Mixer
4.1 Motivation
Multi-standard radio-frequency (RF) receivers are predicted to play a critical role
in wireless communications in the 900-5200MHz range. With cellular and cordless
phone standards operating in the 900MHz and 1.8GHz band, the Global Positioning
System (GPS) in the 1.5GHz band, and wireless local area networks (WLAN)
802.11b in the 2.4GHz band and 802.11a in 5.2GHz band, it is desirable to combine
two or more standards in one mobile unit [10].
The wireless communication specifications 802.11a and 802.11 utilizing
different frequency could be merged in single front-end and share a single digital
signal processor. In this chapter, a 2.45GHz/5.2GHz dual-band, low-power
direct-conversion harmonic mixer is designed and manufactured in tsmc 0.18 m
CMOS process.
4.2 Design Consideration
Fig. 4.1 shows the conceptual example of a dual-band receiver. The receiver
contains two antennas, two LNAs and two mixers. Thought the radio-frequency (RF)
front-end contains two independent paths, the analog circuit and digital signal
processor (DSP) could be combined and decreases the power consumption and cost.
In recently research, the dual-band RF front-end is implemented in a single path (Fig.
4.2). The dual-band LNA is designed for both bands and amplifies both signals
concurrent. In most operation condition, only one of the bands receives RF signal and
the other signal path is unused. That means the mixer must design with concurrent
input matching and only one of the bands will be transferred to output. With this
conception, this mixer is designed in concurrent dual-band input matching and
down-converting one of the receiving band to base-band which system needs. The
conception of Fig. 4.2 will be implemented with this mixer, and the RF front-end
circuit could be designed in a single path.
4.3 Analysis of the Dual-Band Low-Power Harmonic Mixer
The CMOS dual-band harmonic mixer is shown in Fig. 4.3 This harmonic mixer
is composed of three parts: (1) harmonic generation stage; (2) mixing stage, and (3)
frequency tuning stage.
4.3.1 Harmonic Generation Stage
The harmonic generation stage is following section 3.2.1. For low power design,
the biasing current is set as half of former design. By a current source, the Vgs of LO
MOS is restricted in lower voltage for higher second harmonic.
4.3.1.1 Define Harmonic/DC Ratio
For quantifying the second harmonic enhancement, the harmonic/DC ratio R
(3.12) in section 3.2.1.1 is used.
In the same biasing current, operating both MLO+ and MLO- in saturation region
the harmonic/DC ratio is about 10%. In this work, operating both MLO+ and MLO- in
switch-like operation point, the harmonic/DC ratio is 35%. It is three times more than
former one. The conversion gain will increase greatly with this scheme.
4.3.2 Mixing Stage
both RF MOS is set similar as former for linearity consideration. That means, the
injection current is lower than former.
4.3.3 Frequency Tuning Stage
In the frequency tuning stage, the second harmonic current flows through the
peaking inductor and the parallel NMOS switch MSW . Reference papers [8] [9]
introduce the inductive peaking LNA architecture with high gain benefit.
In this stage, inductive peaking architecture is adopted for higher second
harmonic level, and with a parallel switch for frequency tuning. As NMOS switch
turn off (VSW is connected to ground), the second harmonic of LO will flow into
inductor L1+L2. As shown in Fig. 4.4 (a), the inductor and loading from the other two
stages form a third-order filter with peaking effect. As equation (4.2), the large
inductance L1+L2 will form a third order low-pass-filter with peaking frequency in
lower frequency. It means that the mixer is operating in low frequency mode. As
shown in Fig. 4.5 dot line, all of the frequency except frequency near 3GHz will be
filtered out by frequency selection effect, and only low-side band of RF input will
down-convert to base-band.
G
Where CL is the effective load capacitance looking into the harmonic stage, and CP/G
are the effective load capacitance/admittance looking into the mixing stage.
As NMOS switch turns on, the peaking inductor L2 parallel with a small turn-on
resistance as shown in Fig. 4.4 (b). The small signal equation will be:
G
third-order filter will be peaked by inductor L1 and the peaking frequency will be in
higher frequency than that in switch off. As shown in Fig 4.5 solid line, the band-pass
-filter will filter out all frequency except frequency near 5.2GHz, and only up-side
band of RF input will down-convert to base-band. In this operation mode, the mixer is
working in high frequency mode.
With the inductance peaking scheme and a parallel switch, the frequency tuning
stage provides two frequency modes in this work. By frequency selection of the
inductive peaking effect, the mixer decides one of the RF input band will be
transferred to base-band. By this mixer, the conception of Fig. 4.2 will be
implemented.
4.3.3.1 Quantitate the Gain Enhancement
In chapter 3.2.1.2, we define the harmonic/DC ratio. As equation (3.12), this
ratio is direct proportion to conversion gain. In gain tuning stage, the gain step is
associated with the ratio. With MOS switch turn-on, the third-order low-pass filter
will be peaked in 2.45GHz, the second harmonic of 1.225GHz LO frequency. The
second harmonic of 1.225GHz is peaked by low-pass filter and the ratio is around
89%. This is nearly 2.5 times than former without inductive peaking. In the other
condition, pass though the third order low-pass filter which is peaked in 5.2GHz, the
second harmonic of 2.6GHz LO frequency is amplified and the ratio is around 96%.
This is nearly 2.7 times than that without inductive peaking.
4.4 Simulation and Measure Result
This section describes the simulation and measure result of the step-gain harmonic mixer. The pre-simulation is done by Agilent advanced Design System (ADS) and post EM-simulation is done by ADS Momentum.
4.4.1 Chip Implementation
Fig. 4.6 shows the microphotograph of the dual-band harmonic mixer circuit.
The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area
including bonding pads is 0.795mm * 0.683mm. Careful layout is observed in order to
maximize performance. The layout is done in a uni-directional fashion, i.e. no signal
returns close to it origins, to avoid coupling back to the input. For the layout
consideration, the RF-LO ports isolation is the first consideration and places these
ports opposite of the chip to improve port-to-port isolation and enhance DC-offset
cancellation scheme. The RF port, which the signal level is less than LO port, crosses
the IF port vertically and decreases the overlap area to minimize the couple of both
ports. The layout is placed symmetrically to minimize the mismatch of the differential
signal. In order to minimize the effect of substrate noise on the system, a solid ground
plane, constructed using a low resistive metal-1 material, is placed between the signal
pads (metal-6 and metal-5) and the substrate.
4.4.2 Simulation and Measurement Result
The simulation and measure result is listed in TABLE II. Because the 1.225GHz balun is unavailable, we can not measure the 2.45GHz band now. Though the DC current is similar to simulation, the conversion gain is 39dB lower than simulation result. The conversion gain and IIP3 plot is showed in Fig. 4.7. Because most of IM3 is under noise floor, the IIP3 is gained by equation (4.5).
dBm
Because that the harmonic generation stage is the same with former, the lower second harmonic is poor to driver RF MOS. With injection current nearly to zero, the conversion gain is negative. The 5.2GHz input matching is measured and showed in Fig. 4.8. Because that the input balun is narrow band, the input matching is measured separately. The solid line is the measured data and dot line is the simulation result.
TABLE II Simulation result and measure result of the second chip Simulation Result Measure Result
Band 2.45GHz 5.2GHz 2.7 GHz 5.2GHz amplifier is connected. As RF frequency and LO frequency is change the same time.
The down conversion IF frequency is located at the same frequency (3MHz). The
peaking frequency shifts to lower frequency as plot.
4.5 Conclusion
As showed in chapter 3, the differential pair working between cut-off and triode
region may generate lower second harmonic than expected. In this work, the lower
injection current for current reusable let the harmonic/DC ratio too low to drive the
RF MOS and the inductive peaking is moving to low frequency. It makes the
conversion gain is degraded substantially.
Figure 4.1 Conceptual example of a dual-band receiver
Figure 4.2 Conceptual example of a concurrent dual-band receiver
Figure 4.3 Dual-band low-power harmonic mixer
Figure 4.4 Small signal model of peaking inductor and parallel NMOS switch (a) switch off (b) switch on
# $ % &
'()*+"
Figure 4.5 Inductance peaking effect (Vpeak/Ihar)
Figure 4.6 Chip implement
Fig 4.7 Conversion Gain and IIP3
Figure 4.8 Input matching in 5.2GHz band
# $ % &
,*+
,
!-0 !
Figure 4.9 Measurement result inductive peaking in 5.2GHz band
Chapter 5
Summary and Future Works
5.1 Summary
In the chapter 2, the DC-offset of direct-conversion, heterodyne and low IF receivers are presented. The DC-offset issue is an intrinsic problem of direct-conversion receiver because of frequency planning. In the last of chapter 2, the harmonic mixer is mentioned and it seems a way to solve this issue. Besides the DC-offset consideration, two harmonic mixers are introduced. The RF signal is mixing with the second harmonic of LO signal. Both of they are influenced by low linearity.
In the chapter 3, a step-gain harmonic mixer using inductive peaking scheme and switch-like harmonic generation stage is analyzed and implemented in a standard 0.18um CMOS process. Although, measured result show that the conversion gain is lower than simulation, the switch-able inductance peaking scheme for step-gain takes effect as simulation. The trouble shooting is showed in last of chapter 3. Measured data still show that the mixer achieves -15 dB input return loss (S11), while consuming 2.2mA DC current.
In the chapter 4, a dual-band low-power harmonic mixer, intended for use in the receiver path of 802.11a/b system is designed in a standard 0.18um CMOS process.
With the same harmonic generation stage as former, the conversion gain is less than simulation result.
5.2 Future Works
Although some measure results are showed in this thesis, the measurement and trouble shooting of these chips still continues. The drilled PCB board introduces some problem such as leakage and signal loss. Since the bias voltage is fed by a large resistance as RF choke, any leakage will degrade the bias voltage. It should be considered to seek a proper PCB board for testing.
REFERENCES
[1] Abidi, A.A., “RF CMOS come of age,” VLSI Circuits, 2003, Digest of Technical Papers, pp.113-116, June, 2003.
[2] Razavi, B. RF Microelectronics, Prentice Hall PTR, 1998.
[3] Razavi, B., “Design considerations for direct-conversion receivers”; Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, pp.428-435 June, 1997.
[4]Yamaji T. and Tanimoto H., “A 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers,” Proc. of IEEE custom IC Conf., pp.193-196, May, 1997.
[5]Yamaji, T.; Tanimoto, H., and Kokatsu, H., “An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter,” IEEE J. Solid-State Circuits, vol.33, pp.2240-2246, Dec. 1998.
[6] Z. Zhang, Z. Chen and J. Lau, “A 900MHz Balanced Harmonic Mixer for Direct Conversion Receivers,” Proc. IEEE RAWCON2000, pp.219-222, Sept. 2000.
[7] S. J. Fang, S. T. Lee, and David J. Allstot, “A 2GHz CMOS Harmonic Mixer for Direct-Conversion Receivers,” ISCAS 2002, vol.4, pp.IV-807-IV-810, May 2002.
[8]C. Y. Cha, and S. G. Lee, “A low power, high gain LNA topology,” Microwave and Millimeter Wave Technology, 2000, 2nd International Conference on. ICMMT 2000, pp.420-423, Sept. 2000.
[9]Huang, J.C., R. M. Weng, C. C. Chang, K. Hsu and K. Y. Lin, “A 2 V 2.4 GHz fully integrated CMOS LNA,” Circuits and Systems, ISCAS 2001. vol.4, pp.466-469, May 2001.
[10]T. Antes and C. Conkling, “RF chip set fits multimode cellular/PCS handsets,”
Microwaves RF, pp.177-186, Dec. 1996
(Shang-Yi Liu)
(84 9 ~87 6 ) (87 9 ~91 6 )
(91 9 ~93 10 )
PUBLICATION LIST
[1]. Shang-Yi Liu and Chien-Nan Kuo, "A 5.2GHz Direct-conversion Step-gain Harmonic Mixer," VLSI/CAD Symposium, 2004.