Chapter 1 Introduction
1.2 Thesis Organization
The theme of this thesis is the development of parasitic RLC extraction methods, the equivalent circuit analysis and verification for 4 terminals sub- m MOSFET.
In Chapter 2, I will introduce the influence of interconnect capacitance and how to minimize it by layout optimization. In Chapter 3 to Chapter 5, the extraction methods adopted in this study will be described. Some necessary modifications have been done to conform to our test-key in which the equivalent circuit, numerical analysis, and equation derivation will be provided. The extraction method is built and verified for 0.13 m RF CMOS technology.
It is continuous from Chapter 3 to Chapter 5. In Chapter3, I introduce the measurement set and explain the de-embedding methods. Besides, according to my specific consideration, there is some minor modification on the de-embedding method.
In Chapter 4, I elaborate every extraction method of each parameter I extract. It includes my consideration and revision to make the extraction suitable for my test-key.
In Chapter 5, I demonstrate all extracted parameters and their curves from measured data. After that, I analyze their characteristics and bring up a new extraction method of Gate and Drain resistance. Finally, in Chapter 6, I explain the appropriate, reformed layout and extraction for next tape-out. This thesis can provide an extraction reference for others research workers.
Chapter 2
Interconnect Capacitance
2.1 Introduction
A NMOS transistor is composed of p-substrate, n+ doped source and drain regions, n+ poly-Gate, and so on. A circuit designer will put the transistor in his circuit and use metal to connect it with other devices. Based on MOSFET layout analysis, we see that both metal-to-metal and metal to contact introduce interconnect coupling capacitances. Because they belong to device, they are more complicated to be analyzed and extracted than the general inter-metal coupling capacitance introduced by back-end process as pure interconnection lines.
If the transistor is not very small, and the circuit is not operated at very high frequency, these capacitances can be neglected because they are too small compared with intrinsic capacitances. However, if the transistor is very small, and the operating frequency is very high, these capacitances should not be neglected because of the small intrinsic capacitances and the small impedance across the interconnect capacitance. Please see Fig.2-1. (The impedance across capacitance is 1/ C)
In this Chapter, I name the capacitance with a suffix “m”. It means the interconnect capacitance is coupled between metals inner device.
Figure 2 - 1: the interconnect capacitance chart
These capacitances will affect the performance of MOS. For example, fT, the cut-off frequency, is a parameter to know how fast this transistor can operate. There is a rough formula can estimate fT:
gd gs
T C mC
f g when Cgs increase, fT decreases.
It shows the fact that when device is very small, interconnect capacitance will degrade the performance.
2.2 Layout Analysis and Optimization Strategy
Fig.2-2 and Fig.2-4 are the layout of NMOS transistor before and after layout optimization. Now I analyze their interconnect capacitance from the view of their structure to explain that after optimization, the interconnect capacitance effect decreases. The cross-section views of the layout before and after optimizing are showed in Fig.2-2 and Fig.2-3.
Figure 2 - 2: the cross-section view of NMOS before optimizing
Figure 2 - 3: the cross-section view of NMOS after optimizing
2.2.1 Gate to Source Coupling Capacitance - Cgs_m
The gate to source coupling capacitance (Cgs_m) in Fig.2-2 is mainly contributed from the first element Gate-M3 and Source-M2 coupling and the second element from Gate-M1 and Source-M1 coupling. But, in Fig.2-3, the capacitance value decreases much because 1st: Source metal is stacked to M3, and connect to terminal in X-direction; 2nd: the Gate-poly terminator in Fig.2-3 is connect in U-shape. So the Gate-M3 doesn’t overlap Source metal. Besides, Gate-M1 and Source-M1 are staggered and separated in a distance. Such a layout design decrease the interconnect Cgs value.
2.2.2 Gate to Drain Coupling Capacitance - Cgd_m
Cgd_m value is contributed by Gate-poly and Drain-M1 coupling. Because the layout shape of Drain doesn’t change much, the Cgd_m values of Fig.2-2 and Fig.2-3 are closed. Because the space between Gate-poly and Drain-M1 in Fig.2-2 is wider than in Fig.2-3, Cgd value in Fig.2-3 is larger than in Fig.2-2.
2.2.3 Drain to Source Coupling Capacitance - Cds_m
Cds_m value is mainly contributed by Drain-M1 and Source-M1 coupling. When the transistor is smaller, the space between Drain-M1 and Source-M1 is narrower.
And it explains that Cds_m value in Fig.2-3 is larger than in Fig.2-2.
2.3 Simulation result analysis
In section 2.2, Fig.2-3 layout is the optimized result of Fig.2-2 layout to reduce interconnecting coupling capacitance. To prove it, I use the software Calibre-xRC developed by Mentor-Graphic to calculate the coupling capacitance between different metals. Table 2-1 is the simulation result. The device used to be simulated is 0.13 m NMOS whose finger number is 18.
Unit: fF Cgs_m Cgd_m Cds_m
Before optimize 4.36988 2.1651 2.8203
After optimize 1.68503 2.3036 4.53245
Table 2 - 1: the interconnect capacitance values of NMOS whose finger number is 18 (unit:fF)
According to Table 2-1, the Cgs_m value decreases much, Cgd_m value increases little and Cds_m value increases much.
2.3.1 Gate to Source Coupling Capacitance - Cgs_m
Compare Tab.2-2 and Tab.2-3, we can find that before layout optimizing, interconnect Cgs_m is mainly contributed by (1)Gate-M3 and Source-M2 overlap coupling and (2)Gate-M1 and Source-M1 sideward coupling. After layout optimizing, the overlap coupling and sideward coupling are eliminated or minimized. This layout design results in interconnect Cgs_m decreasing.
2.3.2 Gate to Drain Coupling Capacitance - Cgd_m
Drain layout shape is not changed after optimizing. The interconnect Cgd_m
value is not changed much which is mainly contributed by Gate-poly and Source-M1 coupling.
2.3.3 Drain to Source Coupling Capacitance - Cds_m
Interconnect Cds_m is mainly contributed by Drain-M1 and Source-M1 sideward coupling. We hope the device size smaller, and then the space between Drain-M1 and Source-M1 will be narrower. Because device performance is not affected by Cds_m
much, decrease in Cgs_m value is chosen first in the optimization work.
Besides, Table 2-4 is the simulated interconnect capacitance between every
terminal.
Cgs_m Cgd_m Cds_m Cgb_m Cdb_m Cbs_m
NF=18 1.68503 2.3036 4.53245 0.200926 0.451989 0.262949 NF=36 3.0508 4.45151 9.04583 0.233144 0.833048 0.278357 NF=72 5.78234 8.74732 18.0726 0.297582 1.59517 0.309175
Table 2 - 2: simulated interconnect capacitance of each finger number NMOS (unit:fF)
2.4 Spacer Fringing Capacitance Analysis
2.4.1 Introduction
Not only the metal coupling capacitance, but also the capacitances between Gate-poly and Drain/Source diffusion region through spacer should not be neglected when the device is scaled down to nanometer level.
Please see the figure showed below left, C1 represents the coupling capacitance between Gate-poly and contact and C2 represents the coupling capacitance through spacer. When device is not very small, the space between Gate-poly and contact is wide and C1, C2 values are small relative to intrinsic Cgs. However, because fast development of the semiconductor technology, the device size has been extreme small and the space between Gate-poly and contact has been very narrow. Therefore, C1
and C2 values should not be neglected.
However, there is not effective method to measure the values of these capacitances. De-embedding process at least removes the capacitance coupling higher than contact. The C1 and C2 in above figure are always included in extracted capacitance values. Nevertheless, we can calculate out these values by the 3-D simulation tools such as Raphael. We are not sure the accuracy of the simulated intrinsic capacitance which is coupling through the substrate. However we can simplify the device situation. We design a test-key, and the region under Poly-Gate is not channel but oxide. The cross-section view of the test-key is showed below left.
Of course it is not MOS transistor anymore but it simplify the situation of interconnect coupling because semiconductor intrinsic capacitance is excluded. Because there must been a minimum space between diffusion active region and Poly-Gate, the coupling capacitance between Poly-Gate and contact and through spacer are not the same as mentioned formerly. In the above left figure, I use C1’ and C2’ to distinguish from former ones. Furthermore, C3 represents the coupling capacitance through the oxide under Poly-Gate.
We use RF measurement equipment to measure the s-parameters of the test-key and then extract Cgs, Cgd values from the measured data (About the RF measurement, it will be introduced in Chapter 3). In addition, we use the TCAD tool: Raphael to calculate the capacitance values. Here I name the calculated spacer capacitance with a suffix “sp”. If the measured capacitance values are close to simulated values, it means that the simulation tool: TCAD is reliable about the capacitance-in-oxide calculation.
(The materials of spacer are oxide, too)
2.4.2 Measurement and simulation analysis
“S” in the Table 2-5 represents the distance from poly edge to active region edge. Because the region under Gate-poly is oxide, the equivalent circuit is quite simple. Therefore we can extract the capacitances from the formulas:
) Y C Im(
C
Cgg gs gd 11
The extracted capacitances are showed in Table 2-5.
S=0.07, NF=36 S=0.14, NF=36 S=0.21, NF=36
Cgg_sp=Cgs_sp+Cgd_sp 0.312986 0.281111 0.285417
Table 2 - 3: the extracted Cgg values of test-key (unit: fF/um)
Besides, we build a device structure of test-key and import the source file to Raphael, and then simulating the sum of capacitance values which are coupled from Gate to Source and Gate to Drain.
Moreover, the extracted capacitances include interconnect capacitance because the open pad used for de-embedding just reserve the metals higher than M3. Therefore, the simulated interconnect capacitances should be added. Here I use the tool:
Calibre-xRC to calculate the interconnect capacitance of the test-key. The simulated result is showed in Table.2-6.
S=0.07 S=0.14 S=0.21
Interconnect Cgg_m 0.059084 0.06018 0.069056
Spacer Cgg_sp 0.243308 0.188227 0.164437
sum 0.302392 0.248407 0.233493
Table 2 - 4: the simulated Cgg values of test-key (unit: fF/um)
Comparing Table 2-5 and Table 2-6, we can find the simulated value and the measured values are close. This fact tells up that the simulation is believable and hence, the effects we analyze by the help of the tools such as interconnect capacitance and spacer capacitance are reliable.
Chapter 3
RF Measurement and De-embedding
3.1 RF Measurement
For the purpose of extracting MOS transistor parameters from measured data, on-chip RF measurement is adopted because of its accuracy. The data we get not only includes device’s performance but also the influence of the pad, coaxial cable and equipment. Before we put the die in the probe station, system calibration needs to be performed first to remove the influence of equipment, signal line and make the reference plane locates at the probe tips. (Fig.3-1)
Figure 3 - 1: illustration of RF measurement for a two-port system
2-port system is adopted. (Please see Fig.3-2) It is because our measurement equipment (which will be mentioned in 3.1.2), system calibration technique and de-embedding method (which will be mentioned in 3.2) are mainly for 2-port measurement. We can still design a 4-port test patter to extract parameters, but the measurement system with special calibration techniques, and the de-embedding method are more complicated and not complete enough.
Figure 3 - 2: illustration of RF measurement for a two-port transistor
Typically speaking, the system calibration for on-wafer measurement is done by using a so-called impedance standard substrate (ISS) that can provide high-accuracy and low-loss standards for two-port calibration procedures such as short-open-load-through (SOLT) and through-reflect-line (TRL). The SOLT calibration has been widely used because it is supported by virtually every VNA. [1]
3.1.1 Two-Port Scattering Parameters
It is more suitable for two-port RF measurement to use scattering parameters
(s-parameters) to replace impedance and admittance parameters (z-, y-parameters).
Because when device is operated at high frequency, it is quite difficult to provide adequate shorts or opens, particularly over a broad frequency range. Furthermore, active high-frequency circuits are frequently rather fussy about the impedance into which they operate, and may oscillate or even expire when terminated in open or short circuit. [2]
Please see the figure showed below, s-parameters defines input and output variables in terms of incident and reflected (scattered) voltage waves, rather than port voltage or current. Furthermore, the source and load termination are Z0.
2
The normalization by the square root of Z0 is a convenience that makes square of the magnitude of the various an and bn equal to the power of the corresponding
incident or reflected wave. s11 is simply the input reflection coefficient, s12 is the reverse transmission, s21 is a sort of gain and s22 is the output reflection coefficient. [2]
3.1.2 RF Measurement Equipment
The figure showed below illustrates our setup of HF measurement system for on-wafer RF measurements. ICCAP is used to send the commands to instruments (Agilent E8364B PNA, and HP4142B) and the probing station is to perform the measurements for a specific DUT and to gather the measured data for extraction. [1]
3.2 Two-Port de-embedding
After system calibration is accomplished, the reference plane is located at the probe tips. However, the measured data still includes the pad effects which consist of capacitive, inductive and resistive effects. Our goal is to get the measured data of
“pure” device. It is necessary to remove the parasitic effect of the pads including the metal line connecting signal pad and device. There are some techniques developed to remove these pad parasitic effect which is so-called de-embedding.
3.2.1 Open pad de-embedding
The most conventional and easiest method for obtaining the “pure” transistor’s measured data is to use an extra “open” pad.
When the transistor device is measured with the GSG pad, the layout is like Fig.3-3, the equivalent circuit is as Fig.3-4 and the open pad’s equivalent circuit is as Fig.3-5 and Fig.3-6.
Figure 3 - 3: the illustration of device with pad (S and B are connected)
Figure 3 - 4: the equivalent circuit of device with pad
Figure 3 - 5: the illustration of open pad layout
Figure 3 - 6: the equivalent circuit of open pad
After getting the measured s-parameters from device with pad and from open pad, we transform them to y-parameters and then we can get the transistor y-parameters by subtracting YP1, YP2 and YP3 from the measured data of transistor with pad. Theoretically, after this step, we get the pure measured data of transistor.
We name the y-parameter of device with pad “Ymeas”, and the y-parameter of
3.2.2 Open, short pads de-embedding
The de-embedding method expounded in 3.2.1 has a defect that it neglects pad parasitic series effects of the connecting metal line. When device is very small, and operating frequency is very high, the resistive and inductive effect caused by the metal line should not be neglected. So it is necessary to use one more extra dummy pad such as “short” pad to remove the series parasitic components.
Under the considering of pad parasitic series effect, the equivalent circuit of device with GSG pad is as Fig.3-7. The short pad’s equivalent circuit is as Fig.3-8, Fig, 3-9.
Figure 3 - 7: the equivalent circuit of device with pad
Figure 3 - 8: the illustration of short pad
Figure 3 - 9: the equivalent circuit of short pad
The first step is to get the YP1~YP3 value by measuring open pad and the method is mentioned in 3.2.1. After removing YP1~YP3, secondly, we have to remove ZL1~ZL3. We measure the s-parameters of short pad and transform it to y-parameter, and then use y-parameter matrix calculation to remove YP1, YP2 and YP3 in short pad.
Finally, we transform all measured data to z-parameters and use z-parameter matrix
calculation to remove ZL1, ZL2 and ZL3 in the measured data of device with pad.
Please see Fig.3-10 and the equations are showed below [3].
11
Figure 3 - 10: the illustration of de-embedding procedure
3.2.3 Revised de-embedding method for our case
The de-embedding method mentioned in 3.2.1 and 3.2.2 is based on an important fact that the transistor is under 2-port GSG pad measurement. So, it is necessary to connect Source and Body together inter device and then connect to ground pad (Fig.3-3). However, 4-terminal (Gate, Drain, Source, and Body) MOS transistor is more practical to circuit designer because it is more flexible. They would
like to connect Body terminals to ground line individually to make sure the pn-junction between p-substrate and n+ Drain in nMOS is under reverse-bias and prevent substrate affecting nMOS operation. And designer might bring into Body effect by connecting Body to other node except Source or ground to make his circuit fit specification.
Therefore, the latest sample layout which foundry provides to customers doesn’t connect Source and Body inter-device. We didn’t change the indigenous layout and connect the Gate, Drain to two individual signal pads and connect Source, Body to ground pads separately. (Fig.3-11)
Figure 3 - 11: the illustration of device with pad (S and B are separated)
Furthermore, 4-terminal transistor under 4-port RF measurement and corresponding system calibration, de-embedding methods are continuous developed, but not matured yet and will be very complicated expectedly.
Here I provide a revised de-embedding procedure which comes from my
practical measurement experience. And it is suitable for 4-terminal transistor but under 2-port GSG pad (Fig.3-11).
The equivalent circuit of measured device with pad is as Fig.3-12. I change the characters of the pad parasitic series components for later explanation. Zg_ext means the parasitic effect of the metal line connecting signal pad and Gate terminal of transistor and so do Zd_ext, Zb_ext, and Zs_ext. If the Source and Body are connected together first and then connect to ground pad, Zs_ext and Zb_ext are parallel and can be represented by ZL3 in Fig.3-7.
Figure 3 - 12: the equivalent circuit of device with pad (S and B are separated)
First, I extract YP1, YP2, and YP3 from measured data of open pad (equation 3.1) and then subtract “just” YP1 and YP2 from measured data of device with pad (Fig.3-13 (a)).
Second, I extract Zg_ext and Zd_ext from measured data of short pad (equation 3.2)
and then subtract them from the data after first step (Fig.3-13(b)).
Third, subtract YP3 from the data after second step. The reason subtracting YP3
at last is the YP3 is almost capacitive and contributed by near metals which are located at the end of connecting metal line of port 1 and port 2. The original equivalent circuit shows that the nodes of YP3 are at the pad which contacts probe tip. It is not reasonable that they should be at the terminators of metal lines. So YP3 should be subtracted at last. (Fig.3-13)
Although the metal lines connecting to Source and Body are retained, it is practicable to put external resistance or inductance to fit the measured curve. If we just use the de-embedding method mentioned in 3.3.2 which is designed under the consideration of Source and Body tied together first, it will generates an irrelevant data because of the incongruous de-embedding steps. And the model-building work cannot go on.
Figure 3 - 13: the revised de-embedding procedure
3.3 Extraction of PAD parasitic resistance and inductance
The ZL1 and ZL2 in Fig.3-9 are regarded the same as Zg_ext and Zd_ext in Fig.3-12.
However, each time you raise your probe and put down again to measure, the parasitic series resistances are different. The short pad de-embedding includes measured errors innately. But de-embedding procedure is still necessary because it at least decreases much pad effects from measured data of DUT. We can just observe the pad parasitic series resistance and inductance by the short pads.
The right above figure in Fig.3-10 shows that the short pad equivalent circuit subtracting YP1, YP2. And then ZL1 and ZL2 can be extracted from the formulas which
Chapter 4
Model Parameters Extraction
The extraction work is divided into two steps. First, extracting parameter values and second, using these values as initial values of each component in model
The extraction work is divided into two steps. First, extracting parameter values and second, using these values as initial values of each component in model