Chapter 3 RF Measurement and De-embedding
3.3 Extraction of PAD parasitic resistance and inductance
The ZL1 and ZL2 in Fig.3-9 are regarded the same as Zg_ext and Zd_ext in Fig.3-12.
However, each time you raise your probe and put down again to measure, the parasitic series resistances are different. The short pad de-embedding includes measured errors innately. But de-embedding procedure is still necessary because it at least decreases much pad effects from measured data of DUT. We can just observe the pad parasitic series resistance and inductance by the short pads.
The right above figure in Fig.3-10 shows that the short pad equivalent circuit subtracting YP1, YP2. And then ZL1 and ZL2 can be extracted from the formulas which
Chapter 4
Model Parameters Extraction
The extraction work is divided into two steps. First, extracting parameter values and second, using these values as initial values of each component in model equivalent circuit and fine-tuning them to make the simulated curves of equivalent circuit match the measured curves. In the first step, the substrate effect is neglected to simplify the equivalent circuit and make it easier to extract most parameters. I will extract intrinsic resistances and intrinsic capacitances in Vgs>Vth, Vds=0 or 1.2V and then extract substrate parameters in Vgs=Vds=0. Therefore, before second step, we will have many initial values of parameters including interconnect capacitances which are expounded in Chapter 2. There is one point noticeable: in first step, the path through junction capacitance Cjd is neglected because we ignore substrate effect, but the path through Cjs need to be handle carefully because the inductance Ls_ext makes the real part of the impedance see into node “ns” (Please see Fig.4-2) to ground is serious frequency-dependent [Appendix [a.3]].
4.1 Intrinsic Resistance
In Chapter 3, I explain the little revised de-embedding method I use. And I utilize short pad to extract the extrinsic resistances and inductances which result from the connecting metal line between Gate-port1 and Dran-port2. In this section, I will extract the resistances which belong to “intrinsic” transistor. These resistances are so-called intrinsic resistance. The extrinsic resistances have been removed after
de-embedding.
Basically, the intrinsic resistance is composed of two-parts: one is bias-independent which results from process materials such like Poly-silicon, salicide and the other is bias-dependent which results from channel characteristics.
4.1.1 Gate, Drain resistances extraction
1. Vds=0, Vgs>Vth
Here I bring up a new method to extract the Gate and Drain bias-independent resistances. And then extract the channel resistance under Vds=0, Vgs>Vth. In BSIM model card, channel resistance is used to model non-quasi-static (NQS) effect which is a very important parameter when device is operated at high frequency [4]. When a MOS is operated at Vds=0 and Vgs>Vth, the channel is formed. If the operating frequency is very high, the region under the gate is like a distributed, uniform, resistance-capacitance (RC) transmission line.
Figure 4 - 1: channel RC transmission line
In the Fig.4-1, Zch represents the two-port z-matrix of the channel which is a RC transmission line. The total capacitance under gate is Cch and the total resistance is Rch. We can derive the Zch matrix and the result is showed below [5]:
The assumption can be satisfied when the transistor length is very short and the channel opening is higher than 20% of the total channel height. It means that when Vgs is larger, the channel resistance will be smaller and this matrix is more appropriate
[5].
Figure 4 - 2: the equivalent circuit of transistor with gsg pad
The Fig.4-2 represents the equivalent circuit of the device with the pad. The pad part is marked with orange color. On the one hand, the parasitic series resistances and inductances are named with suffix “ext”, on the other hand, the resistances belong to
device are named with suffix “int” such as Rg_int, Rd_int and Rs_int. Besides the channel transmission line, the capacitances coupled between Gate-Source, Gate-Drain, and Drain-Source are named “Cgso”, “Cgdo” and “Cds”. The suffix “o” means overlap.
Because here we define channel capacitance Cch which is always categorized to Cgd
and Cgs, the surplus Cgs and Cgd mainly come from overlap capacitances which are coupling through the overlap thin oxide. Therefore, for clear identification, I name the Gate-Drain and Gate-Source coupled capacitance “Cgdo” and “Cgso”. The junction capacitances between Drain-Substrate and Source-Substrate are represented by Cjd
and Cjs. And the substrate is represented by a resistance “Rbulk”.
After de-embedding (expounded in Chapter 3), the equivalent circuit is represented by Fig.4-3. As mentioned in Chapter 3, the parasitic series resistances and inductances connecting Source-Ground and Body-Ground are retained.
Figure 4 - 3: the equivalent circuit after de-embedding
Figure 4 - 4: the equivalent circuit of mos under Vgs>Vth and Vds=0
As previously mention, the path through Cjd is neglected temporarily but the impedance seen into “ns” to ground is not. This impedance is represented by Zns. According to the analysis [Appendix], the existence of Ls_ext will cause the real part of Zns
serious frequency-dependent. The frequency-dependent components consist of Ls_ext, Rs_ext and Cjs. Besides, the imaginary part of Zns is approximate equal to Ls. Therefore, the equivalent circuit becomes as Fig.4-4 and the z-parameter is showed below which has been modified for our case: [5]
)
According to this matrix, I get an inspiration that we can eliminate the complex component Zns( )by Z11-Z12 and Z22-Z12. Because Vds=0, Cgso=Cgdo, the formulas become:
ch
The two equations demonstrate a good thinking for us. Now taking Re(Z22-Z12) as example. According to the formulas, Re(Z22-Z12) can be divided into two parts: one is Drain resistance (Rd_int) which is gate-bias-independent and the other is half channel resistance which is gate-bias-dependent.
Re(Z11-Z12) is similar to Re(Z22-Z12) except another additional frequency
dependent component ch
gdo constant values, because the bias-dependent component (channel resistance) is reduced to minimum value even approaches to zero under high Vgs. Under this condition, the extracted Re(Z11-Z12) and Re(Z22-Z12) should only be Vgs-bias independent components which result from materials. Therefore, we can extract the bias-independent resistance under high Vgs. But we must be careful that do not give too high voltage in Gate otherwise the device will be damaged.
2. V =1.2V, V >V
Figure 4 - 5: the equivalent circuit of mos under Vgs>Vth and Vds=1.2V
When the device is operated at saturation region (Vds=1.2V, Vgs>Vth), the equivalent circuit is Fig.4-5, and here we ignore the path through the junction capacitance Cjd temporarily. Zns( ) means the impedance seen into node “ns” to ground. Here the resistances are added suffix “sat” to distinguish from the resistance extracted under Vds=0 and Vgs<Vth (Fig.4-3), The components surrounded by dotted box are intrinsic components and can be represented by Yi parameters.
)
And the z-parameters of the full equivalent circuit are [6]:
21i
Here, the equivalent circuit and the z-parameters have been modified little for our case. And then the Gate and Drain resistance extraction equations can be derived:
2
4.1.2 Source Resistance
Because of the existence of Ls_ext which causes some frequency dependent component in measured z-parameters, Source resistance is hard to be extracted from RF measured data. I extract source resistance from DC measurement.
Source resistance will cause gm degradation. According to fundamental electronics, we can derive this formula:
)
Source resistance includes the pad parasitic series resistance. (Rs=Rs_int+Rs_ext in Fig.4-2)
4.2 Intrinsic Capacitance
4.2.1 Vds=0, Vgs>Vth
When Vds=0, Vgs>Vth, the equivalent circuit is like Fig.4-3. And the Z11-Z12 has been derived in section 4.1 which is:
)
According the equation, the imaginary part of Z11 is
) connecting Drain and Source. Therefore, Cch can be incorporated to Drain and Source.
Here I define the Cgs and Cgd as:
Under this bias situation, the transistor is operated at saturation region, and its equivalent circuit is showed in Fig.4-5. Cgg and Cgd are extracted from the formulas:
)
However, these extraction formulas are on a premise that after de-embedding,
the source resistance has been removed completely. In our case, there are two considerations. First: the Source parasitic series inductance is retained and make real part of Zns( ) [appendix] increases with frequency. Second: although we can extract the capacitance at lower frequency to reduce the frequency-dependent effect of real part of Zns( ), the real part of Zns( ), which is approximate to Source resistance at lower frequency, is not zero. When finger number of transistor increases, the gm value will increase and make the current flow through node “ns” increases. And then, the extracted Cgg and Cgd values are inaccurate.
So before extracting the capacitance value, I subtract the Source resistance first to make Vns closer to zero and extract at lower frequency for fear of the frequency-dependent effect of Re(Zns( )):
)
When transistor is operated at saturation region, Cgg is roughly equal to Cgs+Cgd, therefore,Cgs Cgg Cgd
4.3 Substrate Model
Substrate model is very important for RF model. When the device is operated at high frequency, the impedance of the junction capacitance becomes very small.
Therefore, substrate resistance will affect the small-signal output characteristics of the transistor because the small-signal in substrate will go through the junction capacitance to Drain. How to model the substrate effect accurately is an important issue. Here I adopt the model equivalent circuit showed in Fig.4-6.
Figure 4 - 6: the equivalent circuit of mos under Vgs=Vds=0
When the transistor is operated at Vgs<Vth and Vds=0, the equivalent circuit is like Fig.4-6. The substrate is represented by Rbulk. Cjd, and Cjs. Cjd and Cjs are junction capacitances and Cgd0, Cgs0 represent gate-to-drain and gate-to-source capacitance.
The suffix “0” means they are under zero Vgs bias. Cgb represents the sum of intrinsic and extrinsic gate-to-body capacitances. Because the device is operated at Vgs<Vth, most intrinsic components of the transistor are negligible. The Gate, Drain, and Source resistance are neglected here because the impedance of them is much smaller than the impedance of junction capacitance and substrate resistance [7].
After deriving the y-parameters of the equivalent circuit, we can get the
However, this extraction method doesn’t match our case because our test-key retains the pad parasitic series resistances and inductances in Source and Body
terminals. The existence of inductance will seriously affect the y-parameters. The extracted parameter curve is not stable with frequency. Nevertheless, this method still supports initial values of Cjd, Cjd and Rbulk for us. I extract the initial values under low frequency and then do some fine-tune work to make the simulated y-parameters curves of equivalent circuit fit the y-parameter curve of measured data.
According the NMOS layout, we can figure out the junction area between Drain or Source diffusion region and Substrate. And then we can derive one capacitance from another. According to the layout, the two-side diffusion regions are Source.
Besides, the areas of the two-side diffusions are little larger than others. The Cjs can be calculated by the equation (0.73 and 0.42 are the edge length of the Drain region and two-side Source region. Please see the figure showed in the left side of next calculated result because one side of the diffusion region is oxide except substrate for the two-side diffusion region. Please see dotted circuit in left Figure. Therefore, this equation provides the initial value of Cjs
from Cjd but we have to decrease little to fine-tune the curve.
Besides, the equivalent circuit in Fig.4-6 doesn’t include Cds which appears in other equivalent circuit. I think the Cds only comes from the interconnect capacitance.
Hence I use the value simulated by Calibre-xRC to represent Cds value. It has been demonstrated in Table 2-4 in Chapter 2.
During my fine-tune process, I find that if I add two additional components to the equivalent circuit of Fig.4-6, the simulated curves will fit measured curves better.
These two components are one capacitance and one resistance in series. Moreover, this series resistance and capacitance are parallel with the substrate resistance (Rbulk of Fig.4-6).
I conjecture that these two components come from the Deep N-Well process which is for RF design to prevent noise going through substrate. When a circuit designer arranges his circuit layout, he can put N-well layer surrounding NMOS and then put a Deep N-well layer in rectangular shape which covers the inner edge of N-well “Ring”. And then, the N-well and deep N-well will be like a bowl and the p-substrate will be protected in it. The pick-up of the N-well is usually bias to the highest voltage to make the junction between p-substrate and n-well reverse-bias. This structure is designed to prevent outside noise into the p-substrate and affecting the performance of NMOS. The instruction of this structure is showed in Fig.4-7.
Figure 4 - 7: illustration of Deep N-well in sectional drawing
Therefore, the additional capacitance results from the junction capacitance between N-well (including Deep N-well and sideward N-well) and p-substrate. I name it “Cdnw“. The additional resistance results from the impedance of the small-signal path in Deep N-well. I name it “Rdnw”. Please see Fig.4-8 as the more clear illustration.
Figure 4 - 8: the equivalent circuit which is added Cdnw and Rdnw
Although I do some fine-tune work, I am not aimless. There are two basic principles: first is getting the value under low frequency to minimum the retained inductive effect; second is following the simplified equivalent circuit for Y22 which is showed in Fig.4-10.
I explain my substrate model extraction steps for summarization:
(1) Operating the transistor at Vgs=Vds=0 and the equivalent circuit is like Fig.4-9. (Rs_int and Rs_ext are summed up to Rs which extracted in section 4.1.2; Rb_ext, Ls_ext and Lb_ext results from our test-key situation which is mentioned in chapter 3; Moreover, Cdnw and Rdnw are added to the circuit.) (2) Extracting Cgs0 and Cgd0 and Cgb from the measured data according to
equation 4.4. Because there is no current flowing into the node “ns”, the
results of revised extraction mentioned in section 4.2 is almost the same as un-revised. However we still extract capacitance from revised extraction method because the initial values of Rbulk and Cjd are extracted at low frequency too.
(3) Rg_int and Rd_int are bias-independent because the channel doesn’t exist.
Their values are extracted from Re(Z11-Z12) and Re(Z22-Z12) under Vds=0 and Vgs is large enough. (Please see the explanation in section 4.1.1.)
(4) According to equation 4.4 and 4.5, and calculating the Rsub, Cjd and Cjs
values. They will vary with frequency. Observing the curves, and take the values under lower frequency (about lower 3 GHz) as initial values for fine-tuning.
(5) Extracting Ls_ext value according to equation 4.6. (This extraction will be explained in next 4.4.) Lb_ext is assumed equal to Ls_ext.
(6) The Cds value comes from simulated interconnect Cds value which is discussed in chapter 2.
(7) After steps (1) to (6), we now have all initial values of parameters in Fig.4-9 except Rdnw and Cdnw. Next, we build a circuit like Fig.4-9 in software: ADS and then simulating its y-parameters. After the calculating and fine-tuning parameters, we can get these parameters final. The calculating equation is showed in Fig.4-10. Basically, the parameters which don’t belong to substrate are not tuned.
Figure 4 - 9: the equivalent circuit of NMOS under Vgs=Vds=0V
Figure 4 - 10: the R , C fine-tuning extraction process
4.4 Source Extrinsic Inductance
In Chapter 3, I expound the de-embedding procedure and mention that the pad parasitic series resistance and inductance are retained in the Source and Body terminals. In 3.3, I introduced that we can extract the pad parasitic series resistance and inductance of Gate and Drain terminals from Short and Open pads. To extract the pad parasitic inductance in Source terminal, we have to bias the device under Vgs>Vth
and Vds=0 and the equivalent circuit is like Fig.4-3. To explain easier, here we can just use a small resistance Rch to replace the RC transmission line in Fig.4-3. And according to the analysis in Appendix [a.3], the real part of Zns( ) is serious frequency-dependent but the imaginary part of Zns( ) is approximate equal to Ls. If the finger number is larger, the Cjs value will be larger and it will make the approximation incredible. Therefore, I extract the Source extrinsic inductance from the measured data of NF=18 transistor and take the average of the imaginary part of Z12 at frequency=5GHz~40GHz.
The Z12 of Fig.4-3 which is mentioned in 4.1.1 is
Chapter 5
Experiment and Analysis
5.1 Pad parasitic series resistance and inductance
Theoretically, after de-embedding, the pad parasitic effect can be removed.
Actually, it is hard to achieve. However, it is still a very important procedure that de-embedding can remove some critical pad parasitic effect initially such as inductive and capacitive effects.
5.1.1 Inductance
When operating frequency is very high, the thin metal line will behave as an inductance. We can extract the Gate, Drain parasitic series inductances from the short pad which subtracts the pad parasitic capacitive effect. It is mentioned in 3.3.
Besides, the source inductance extraction need to be extracted by the help of small channel resistance under Vgs>Vth and Vds=0. It is mentioned in 4.4.
The inductive effect becomes obvious when frequency is high enough. We take the average value of frequency=5GHz to 40GHz as the extracted parasitic inductance values. They are:
Gate parasitic inductance
Drain parasitic inductance
Source parasitic inductance
Unit: pH 48.82 47.39 50.64
Table 5 - 1: extracted parasitic inductance values
5.1.2 Resistance
We take the average of the values at frequency=5GHz to 40GHz as the extracted parasitic resistance. They are:
Gate parasitic resistance Drain parasitic resistance
Unit: 1.14 1.067
Table 5 - 2: extracted parasitic resistance values
5.2 Intrinsic resistance
According to the demonstration in section 4.1.1, the Gate and Drain resistance can be extracted from Re(Z11-Z12) and Re(Z22-Z12). They include two parts:
bias-dependent and bias independent.
5.2.1 Gate, Drain resistances
1. Vds=0, Vgs>Vth (average of 15GHz~30GHz)
I name the extracted values of Re(Z11-Z12) and Re(Z22-Z12) “RG” and “RD”.
First, we see the extraction curve of R , (Fig.5-1). We can find that the curve is not
flat at lower frequency. It is because the extraction method expounded in 4.1.1 is under the situation that the channel is like a transmission line. If the frequency is not high enough, the RC delay in the channel is not obviously. Besides, although the channel resistance is small, and under this bias condition, we neglect the substrate effect, we have to sample the data carefully especially when extracting RD which will be influenced by Cjd easily. Therefore, I sample the data at 15GHz to 30GHz and take average as the extracted value. We can find the curves of Re(Z22-Z12) become unstable when the frequency is higher than 30GHz.
0 10G 20G 30G 40G
-505 1015 2025 3035 4045 5055 6065 70
Vgs=1.2
Vgs=0.5V Vgs=1.2V
RG
Frequency
Vgs=0.5
Figure 5 - 1: extracted RG of NF=18 NMOS under Vds=0, Vgs=0.5 and 1.2V
The extracted RG and RD values under Vgs>Vth and Vds=0 are showed in Table 5-3 and Table 5-4.
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 -3.03 0.448 1.76 2.37 2.7 2.92 3.08 3.21
N36 -0.978 0.782 1.38 1.66 1.81 1.89 1.98 2.05 N72 -0.857 0.244 0.636 0.744 0.82 0.866 0.933 1.07
Table 5 - 3: extracted RG values under Vds=0 (unit: )
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Now I plot the extracted RG figure according to Table 5-3 and show in above.
Observing the curves, we can find the extracted values vary with Vgs. We take the equation mentioned in section 4.1.1:
Observing the curves, we can find the extracted values vary with Vgs. We take the equation mentioned in section 4.1.1: