Chapter 4 Model Parameters Extraction
4.4 Source Extrinsic Inductance
In Chapter 3, I expound the de-embedding procedure and mention that the pad parasitic series resistance and inductance are retained in the Source and Body terminals. In 3.3, I introduced that we can extract the pad parasitic series resistance and inductance of Gate and Drain terminals from Short and Open pads. To extract the pad parasitic inductance in Source terminal, we have to bias the device under Vgs>Vth
and Vds=0 and the equivalent circuit is like Fig.4-3. To explain easier, here we can just use a small resistance Rch to replace the RC transmission line in Fig.4-3. And according to the analysis in Appendix [a.3], the real part of Zns( ) is serious frequency-dependent but the imaginary part of Zns( ) is approximate equal to Ls. If the finger number is larger, the Cjs value will be larger and it will make the approximation incredible. Therefore, I extract the Source extrinsic inductance from the measured data of NF=18 transistor and take the average of the imaginary part of Z12 at frequency=5GHz~40GHz.
The Z12 of Fig.4-3 which is mentioned in 4.1.1 is
Chapter 5
Experiment and Analysis
5.1 Pad parasitic series resistance and inductance
Theoretically, after de-embedding, the pad parasitic effect can be removed.
Actually, it is hard to achieve. However, it is still a very important procedure that de-embedding can remove some critical pad parasitic effect initially such as inductive and capacitive effects.
5.1.1 Inductance
When operating frequency is very high, the thin metal line will behave as an inductance. We can extract the Gate, Drain parasitic series inductances from the short pad which subtracts the pad parasitic capacitive effect. It is mentioned in 3.3.
Besides, the source inductance extraction need to be extracted by the help of small channel resistance under Vgs>Vth and Vds=0. It is mentioned in 4.4.
The inductive effect becomes obvious when frequency is high enough. We take the average value of frequency=5GHz to 40GHz as the extracted parasitic inductance values. They are:
Gate parasitic inductance
Drain parasitic inductance
Source parasitic inductance
Unit: pH 48.82 47.39 50.64
Table 5 - 1: extracted parasitic inductance values
5.1.2 Resistance
We take the average of the values at frequency=5GHz to 40GHz as the extracted parasitic resistance. They are:
Gate parasitic resistance Drain parasitic resistance
Unit: 1.14 1.067
Table 5 - 2: extracted parasitic resistance values
5.2 Intrinsic resistance
According to the demonstration in section 4.1.1, the Gate and Drain resistance can be extracted from Re(Z11-Z12) and Re(Z22-Z12). They include two parts:
bias-dependent and bias independent.
5.2.1 Gate, Drain resistances
1. Vds=0, Vgs>Vth (average of 15GHz~30GHz)
I name the extracted values of Re(Z11-Z12) and Re(Z22-Z12) “RG” and “RD”.
First, we see the extraction curve of R , (Fig.5-1). We can find that the curve is not
flat at lower frequency. It is because the extraction method expounded in 4.1.1 is under the situation that the channel is like a transmission line. If the frequency is not high enough, the RC delay in the channel is not obviously. Besides, although the channel resistance is small, and under this bias condition, we neglect the substrate effect, we have to sample the data carefully especially when extracting RD which will be influenced by Cjd easily. Therefore, I sample the data at 15GHz to 30GHz and take average as the extracted value. We can find the curves of Re(Z22-Z12) become unstable when the frequency is higher than 30GHz.
0 10G 20G 30G 40G
-505 1015 2025 3035 4045 5055 6065 70
Vgs=1.2
Vgs=0.5V Vgs=1.2V
RG
Frequency
Vgs=0.5
Figure 5 - 1: extracted RG of NF=18 NMOS under Vds=0, Vgs=0.5 and 1.2V
The extracted RG and RD values under Vgs>Vth and Vds=0 are showed in Table 5-3 and Table 5-4.
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 -3.03 0.448 1.76 2.37 2.7 2.92 3.08 3.21
N36 -0.978 0.782 1.38 1.66 1.81 1.89 1.98 2.05 N72 -0.857 0.244 0.636 0.744 0.82 0.866 0.933 1.07
Table 5 - 3: extracted RG values under Vds=0 (unit: )
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Now I plot the extracted RG figure according to Table 5-3 and show in above.
Observing the curves, we can find the extracted values vary with Vgs. We take the equation mentioned in section 4.1.1:
ch
According to this equation, we can find the real part of Re(Z11-Z12) consists of two parts: a bias-independent resistance and a bias-dependent resistance associated with channel resistance. First we check the third component in the equation.
Observing the extracted Cgg values under Vds=0, which are showed in later Table 5-8,
we can find when Vgs is higher than about 0.7V, the Cgg value approaches to a constant. In addition, the Cgdo value, which contributed by overlap and fringe capacitances, should be about one-third Cgd from experience, and under Vds=0, Cgd is equal to half Cgg, therefore, Cgdo is about one-sixth Cgg. Besides, Cds mainly results from interconnect capacitance and the simulated values have been showed in Table 2-4.
We take NF=72 NMOS as example. Its Cgg value under Vds=0, Vgs=1.2V is 431.1fF (later Table 5-9). The Cgdo value is about one-sixth Cgg and is 71.8fF. Cdsm of NF=72 NMOS is 18fF (former Table 2-4) Therefore, we can figure out that
gdo ch
ds gdo
C 2 C
C 3
C is about 0.29. And then ch
gdo ch
ds
gdo R
C 2 C
C 3 C 3
1 is less than one-sixth Rch
surely. It means that Re(Z11-Z12) is a constant “Rg_int” subtracting a value associated with channel resistance. When Vgs increases, channel resistance decreases. Therefore, the result of a constant subtracting a smaller value is larger than before. It explains the trend of the curves in Fig.5-2 reasonably.
Therefore we can utilize this phenomenon to extract the Poly-silicon resistance which is bias-independent component associated with the materials. We can bias Vgs
carefully little higher than VDD and then the channel resistance reaches an extreme small value which can be neglected. And then Rg_int is equal to Re(Z11-Z12)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 varying with Vgs. First, the RD equation mentioned in section 4.1.1 is:
ch
When Vgs increases, channel resistance decreases. Therefore, the constant, Rd_int adds a smaller value and gets a smaller value than before. Base on the former discussion just elaborated, we can bias Vgs carefully little higher than VDD, and then get the intrinsic Drain resistance value which is just associated with the impedance in diffusion region.
This extraction brings two benefits. First, it can exclude the measured resistance error results from the contact between probe tip and pad. Because the contact condition of each time measurement is different, the extracted resistance is influenced by it each time. However, if we can extract the bias-independent component, it must
include the resistance results from the contact. And when we build a resistance model, we can subtract this component first. And then we can be sure the left resistance is associated with channel. Therefore, second, it makes the model more physical.
Originally, we always get a large values need to be fit. Now we at least can build the resistance model as like “RG=Rg_int+R1(Vgs, )” and “RD=Rd_int+R2(Vgs, )” first. And then we start to model the channel performance as the parameter “R(Vgs, )”.
2. Vds=1.2V, Vgs>Vth (average of 38.2GHz~40GHz)
The RG extraction curves under Vds=0 and Vgs=0.5, 1.2V are showed in Fig.5-4.
According to the extraction method expounded in 4.1.1, this method is reliable when the frequency is infinity. However, our measurement is limited by equipment and just up to 40GHz. But the curve is truly flatter when the frequency is higher. Here I sample the values at highest 10 frequency points which are 38.2 GHz to 40GHz.
0 10G 20G 30G 40G
10 20 30 40 50 60 70 80 90
RG
Frequency
Vgs=0.5V Vgs=1.2V
Vgs=1.2 Vgs=0.5
Figure 5 - 4: extracted RG of NF=18 NMOS under Vds=1.2V, Vgs=0.5 and 1.2V
The extracted RG and RD values under Vgs>Vth and Vds=1.2V are showed in Table 5-6 and Table 5-7.
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 N18 16.498 15.969 15.353 14.825 14.337 13.682 13.38 12.874 N36 11.209 11.156 10.9 10.615 10.323 10.017 9.702 9.366 N72 5.511 6.086 5.94 5.795 5.648 5.501 5.312 5.128
Table 5 - 5: extracted RG values under Vds=1.2V (unit: )
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 30.476 28.296 26.91 26.092 25.515 25.021 24.539 24.024 N36 14.935 14.045 13.547 13.207 12.947 12.708 12.455 12.181 N72 5.934 5.487 5.267 5.117 5 4.891 4.772 4.652
Table 5 - 6: extracted RD values under Vds=1.2V (unit: )
Although the curves really conform to the prediction mentioned in reference paper 4-3 and trend to constants, the substrate effect is still a latent problem. When Vds=0 and Vgs>Vth, the existence of channel resistance causes a small impedance path and then the path through Cjd is ignorable. However, when the transistor is operated at saturation region, the small channel resistance is replaced by a current source and an extreme large resistance. Under this situation, the impedance of the path through Cjd
might not be ignorable.
5.2.2 Source resistance
Following the extraction procedure mentioned in 4.1.2, the extracted Source resistances are showed in Table 5-8. Moreover, Fig.5-5 shows that Rs will causes Id
and gm degradation.
Source resistance NF=18 NF=36 NF=72
Unit: 2.0798712 2.079875 2.30155
Table 5 - 7: extracted RS values from DC measurement (unit: )
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
10.0m 20.0m 30.0m 40.0m 50.0m 60.0m
A or A/V
Vgs
w/o Rs Id w/i Rs Id w/o Rs gm w/i Rs gm
Figure 5 - 5: simulation of Id and gm vs Vgs w/i and w/o Rs
5.3 Intrinsic capacitance
5.3.1 Vds=0, Vgs>Vth (average of 5GHz~15GHz)
The extracted Cgg curves under Vgs=1.0, 1.2V and Vds=0 of NF=72 transistors are showed in Fig.5-6. We observe that when the frequency increases, the curves become unstable. We have discussed in Chapter 4. In the first step of extraction work, we ignore substrate first which includes Cjd and Rbulk. (Because the Ls_ext exists, the Cjs is special to un-neglected. It is discussed in Appendix). Therefore, if the frequency is very high, the Cjd and Rbulk will start to affect the y-parameters or z-parameters.
Besides, the Cgg will be extracted from the equation 4.2 in section 4.2.1. It
is Im(Z Z )
C 1
12 11
gg . This equation has to satisfy an assumption mentioned in Appendix [a.1] that is L2 RchCch 1. And when finger number is larger, Cch is larger. Moreover, if the frequency is too high, the assumption is not established anymore and this equation cannot be used. Therefore, in Fig.5-6, the curve of NF=72 NMOS under high frequency becomes unstable.
0 10G 20G 30G 40G
Therefore, I take the average of
)
at frequency=5GHz~15GHz as the Cgg values. The extracted Cgg values under different Vgs are showed in Table
The Cgs and Cgd are equal to half Cgg and the values are showed in Table 5-9.
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 52.55 54.8 55.75 56.1 56.25 56.2 56.1 55.95 N36 103.3 107.2 108.95 109.65 109.85 109.75 109.55 109.3 N72 204.3 211.9 215.25 216.7 217.1 217 216.45 215.55
Table 5 - 9: extracted Cgd values under Vds=0V (unit: fF)
5.3.2 Vds=1.2V, Vgs>Vth
There are two problems when extracting Cgg under Vds=1.2V and Vgs>Vth which has been mentioned in section 4.2.2 First, the imaginary part of Y11 is decreasing when frequency is increasing because the frequency-dependence of real part of Zns( ).
Fig.5-7 is the extracted Cgg curves of NF=18, 72 transistors under Vgs=Vds=1.2V which are directly extracted from imaginary part of Y11 divided by . We can find that the curves are obviously decreasing when frequency is increasing. As mentioned in section 4.2.2, we can extract Cgg at lower frequency to make this bad effect minimum (Fig.5-8). Second, the imaginary part of Y11 is decreasing when the finger number of transistor is increasing because the more current flow into the node “ns” which is indicated in Fig.4-2, the node voltage is higher and causes the imaginary part of Y11
decreases. Therefore, even I extract Cgg under lower frequency as showed in Fig.5-8, the Cgg value of transistor whose finger number is 72 is not reasonable. It is not about 4 times of the Cgg value of transistor whose finger number is 18. Therefore, as mentioned in 4.2.2, I subtract Rs first from the measured z-parameters under low frequency and then transform it to y-parameters and use these y-parameters to extract
Cgg. Fig.5-9 is the result of revised extraction. We can find the Cgg values are reasonable. The Rs values are from the extraction result elaborated in Table 5-8 in section 5-2-2. The frequency range is 0.4GHz~2.2GHz, the first 10 frequency points except 0.2GHz. Cgd extraction has similar problem. Cgg and Cgd are extracted from equation 4.3 under 0.4GHz to 2.2GHz. The extracted Cgg, Cgd, and Cgs values under different Vgs bias are showed in Table 5-11, Table 5-12 and Table 5-13.
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 94.82 101.9 106.1 108.7 110 111.1 111.7 112.2 N36 182.5 194 201.5 205.8 208.5 210 210.9 211.4 N72 366.4 391.3 409.6 419.5 424.2 425.9 425.9 425.2
Table 5 - 10: extracted Cgg values under Vds=1.2V (unit: fF)
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 29.07 29.15 29.31 29.55 29.89 30.23 30.66 31.13 N36 57.06 57.04 57.38 57.88 58.52 59.29 60.2 61.26
N72 116 116 116.2 117 118.2 119.7 121.7 124.1
Table 5 - 11: extracted Cgd values under Vds=1.2V (unit: fF)
Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
N18 65.75 72.75 76.79 79.15 80.11 80.87 81.04 81.07 N36 125.44 136.96 144.12 147.92 149.58 150.71 150.7 150.14 N72 250.4 275.3 293.4 302.5 306 306.2 304.2 301.1
Table 5 - 12: extracted Cgs values under Vds=1.2V (unit: fF)
0 10G 20G 30G 40G 50.0f
100.0f 150.0f 200.0f 250.0f 300.0f 350.0f
Cgg (F)
Frequency
NF=18 NF=72
Figure 5 - 7: extracted Cgg of NF=18, 72 NMOS under Vds=1.2 and Vgs=1.2V
0.0 500.0M 1.0G 1.5G 2.0G 2.5G 50.0f
100.0f 150.0f 200.0f 250.0f 300.0f 350.0f
Cgg (F)
Frequency
NF=18 NF=72
Figure 5 - 8: extract Cgg at lower frequency (continue Fig.5-27)
0.0 500.0M 1.0G 1.5G 2.0G 2.5G 50.0f
100.0f 150.0f 200.0f 250.0f 300.0f 350.0f 400.0f 450.0f
Cgg (F)
Frequency
NF=18 NF=72
Figure 5 - 9: subtracted Rs effect first and extract Cgg at lower frequency (continue Fig.5-28)
5.4 Substrate Model
The equivalent circuit of NMOS under Vds=Vgs=0 has been showed in Fig.4-9.
Cgg, Cgd0, and Cgb values of different finger number NMOS are extracted according to first two equations in equation 4.4. The curves are flat up to about 20GHz. If the frequency is higher, the y-parameter curve will behave the resonant effect especially when finger number is 72. I follow the former capacitance extraction sampling frequency range which is 0.4GHz to 2.2GHz. The extracted capacitance values are showed in Table 5-13.
Cgg Cgd0 Cgb
N18 73.81 31.05 11.71
N36 141.1 61.26 18.58
N72 281.6 125.2 31.2
Table 5 - 13: extracted Cgg, Cgd0 and Cgb under Vds=Vgs=0
Cjd and Rbulk initial values come from the last two equations in equation 4.4.
Taking NF=36 NMOS as example. Please see Fig.5-10 and Fig.5-11. As I explained in section 4.3, because the retained Ls_ext and Rs, the Rbulk and Cjd extracted curves are not stable with frequency. However, when frequency is not very high, we can regard the impedance of inductance eliminated. Therefore, we can roughly sample the values in red dotted circuit as the initial values of Rbulk and Cjd. Moreover, Cjs is estimated from equation 4.4 but might be tuned smaller.
0 10G 20G 30G 40G
0 50 100 150 200 250
initial case for Rbulk
Frequency
NF=36
Sample Rbulk initial value
Figure 5 - 10: extract Rbulk initial value under Vds=Vgs=0
0 10G 20G 30G 40G
70.0f 80.0f 90.0f 100.0f 110.0f 120.0f 130.0f
initial case for Cjd fF
Frequency
NF=36 Sample the Cjd initial value
Figure 5 - 11: extract Cjd initial value under Vds=Vgs=0
Besides, we refer to the values of Rs and Ls_ext, and estimate the values of pad extrinsic series resistance and inductance connecting to Body equal to 2ohm and 40pH, because the Body connecting metal is little wider then the Source connecting metal.
As I elaborated in section 4.3, the Rg_int, Rd_int, Rs, and Ls_ext are extracted from some methods. Here I omit the process. Now we get all parameters initial values except Cdnw and Rdnw. After fine-tune process which is showed in Fig.4-10, we can get the parameters showed in Table 5-14 and 5-15. Because the substrate effect influences the imaginary part of Y22 most, I fit im(Y22)/ first. Fig.5-12 to 5-14 are the im(Y22)/ curves of measurement and simulation of the equivalent circuit model showed in Fig.4-9 after adding the two new components “Rdnw” and “Cdnw”. The figures include NF=18, 36 and 72 NMOS.
Rg_int( ) Rd_int( ) Rs( ) Ls_ext(pH) Cgs(fF) Cgd(fF) Cgb(fF) Cds(fF)
NF=18 3.18 5.04 2.08 55 31.05 31.05 10.5 4.53
NF=36 2.08 2.4 2.08 55 61.26 61.26 18.58 9.05
NF=72 1.1 1.2 2.31 55 125.2 125.2 31.2 18.07
Table 5 - 14: extracted parameters of Fig.4-9
Cjd(fF) Cjs(fF) Rbulk( ) Cdnw(fF) Rdnw( ) Rb_ext( ) Lb_ext(pH)
NF=18 52 55 230 26 240 2.08 40
NF=36 105 110 120 52 120 2.08 40
NF=72 200 210 70 120 50 2.3 40
Table 5 - 15: extracted parameters of Fig.4-9
0 10G 20G 30G 40G
Chapter 6
Conclusion and Future Work
6.1 RF De-embedding
In Chapter 2, the interconnect capacitances are demonstrated by the help of software. In Chapter 3, the de-embedding methods to remove pad parasitic effects are discussed. The parasitic effect of pad “YP3” (Fig.3-12) is capacitive effect between two signal ports. The effect is mainly contributed by the interconnect capacitance.
Moreover, when device is smaller, the capacitive effect between signal pad and ground pad which is contributed by interconnect capacitance will increase. Traditional open pad for de-embedding just retains metal layers higher than M3 (exclude M3) because the metals lower than M3 is categorized to “intrinsic” device.
To get the more “pure” intrinsic measured data of device, we can try to remove the interconnect capacitances after de-embedding. Nevertheless, although the de-embedding method can remove most pad parasitic effects to get more accurate pure device measured data, it will cost more dummy pads but not only open and short pads [9].
6.2 Parameters Extraction
After the extraction process elaborated in the thesis, we have two aspects of thinking.
One is traditional 2-port RF measurement and the other is 4-port RF measurement.
In our test-key, the Source and Body are not connected together first and connect to ground pad separately. If we connect them first, it returns back to traditional 3-Terminal (3T), 2-port case. And the real part of the impedance seen into node “ns” (Fig.4-2) which is associated with Ls_ext will be simplified to Source resistance “Rs_int”. Because the pad parasitic series inductance “Ls_ext” is removed after de-embedding, the component which causes Re(Zns( )) increases with frequency doesn’t exist. In future work, we can put a test-key under this case to verify.
Besides, there are many published papers [10], [11], [12] using other formulas to extract parameters under 2-port measurement. For example, we can also extract Gate, Drain, and Source resistances from Y-parameters except Z-parameters [10].
Relative to 2-port measurement and parameter extraction, the published papers about 4-port are fewer. But 4-port measurement and extraction is a trend because of the need of 4-T transistors for circuit designers. Even though the system calibration technique and measurement are more complex, more and more engineers devote to this research.
It includes the accurate system calibration and precise measurement. Under 4-port RF measurement, the parameter extraction will be more complex than 2-port measurement. But the built model card will behave more close to reality.
6.3 Substrate Model
In this thesis, I propose two new parameters to model the effect of deep N-well and one resistance to model the effect of p-substrate.
There are several papers about substrate model are published continuously. For example, in the reference paper [10], substrate model is composed of three resistances which are showed in Fig.6-1. Besides, in accordance with the three resistance substrate model, in reference paper [13] and [14], the different authors propose different analysis. I also design a test-key to study this three resistance substrate model. In future, we can analyze the measured result of the special-designed test-key to analyze substrate effect deeper.
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Figure 6 - 1: 3-resistances substrate model
Reference
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