Gate, Drain resistances

1. Vds=0, Vgs>Vth (average of 15GHz~30GHz)

I name the extracted values of Re(Z11-Z12) and Re(Z22-Z12) “RG” and “RD”.

First, we see the extraction curve of R , (Fig.5-1). We can find that the curve is not

flat at lower frequency. It is because the extraction method expounded in 4.1.1 is under the situation that the channel is like a transmission line. If the frequency is not high enough, the RC delay in the channel is not obviously. Besides, although the channel resistance is small, and under this bias condition, we neglect the substrate effect, we have to sample the data carefully especially when extracting RD which will be influenced by Cjd easily. Therefore, I sample the data at 15GHz to 30GHz and take average as the extracted value. We can find the curves of Re(Z22-Z12) become unstable when the frequency is higher than 30GHz.

0 10G 20G 30G 40G

-505 1015 2025 3035 4045 5055 6065 70

V_gs=1.2

V_gs=0.5V V_gs=1.2V

RG

Frequency

V_gs=0.5

Figure 5 - 1: extracted RG of NF=18 NMOS under Vds=0, Vgs=0.5 and 1.2V

The extracted RG and RD values under Vgs>Vth and Vds=0 are showed in Table 5-3 and Table 5-4.

Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

N18 -3.03 0.448 1.76 2.37 2.7 2.92 3.08 3.21

N36 -0.978 0.782 1.38 1.66 1.81 1.89 1.98 2.05 N72 -0.857 0.244 0.636 0.744 0.82 0.866 0.933 1.07

Table 5 - 3: extracted RG values under Vds=0 (unit: )

Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Now I plot the extracted RG figure according to Table 5-3 and show in above.

Observing the curves, we can find the extracted values vary with Vgs. We take the equation mentioned in section 4.1.1:

ch

According to this equation, we can find the real part of Re(Z11-Z12) consists of two parts: a bias-independent resistance and a bias-dependent resistance associated with channel resistance. First we check the third component in the equation.

Observing the extracted Cgg values under Vds=0, which are showed in later Table 5-8,

we can find when Vgs is higher than about 0.7V, the Cgg value approaches to a constant. In addition, the Cgdo value, which contributed by overlap and fringe capacitances, should be about one-third Cgd from experience, and under Vds=0, Cgd is equal to half Cgg, therefore, Cgdo is about one-sixth Cgg. Besides, Cds mainly results from interconnect capacitance and the simulated values have been showed in Table 2-4.

We take NF=72 NMOS as example. Its Cgg value under Vds=0, Vgs=1.2V is 431.1fF (later Table 5-9). The Cgdo value is about one-sixth Cgg and is 71.8fF. Cdsm of NF=72 NMOS is 18fF (former Table 2-4) Therefore, we can figure out that

gdo ch

ds gdo

C 2 C

C 3

C is about 0.29. And then _ch

gdo ch

ds

gdo R

C 2 C

C 3 C 3

1 is less than one-sixth Rch

surely. It means that Re(Z11-Z12) is a constant “Rg_int” subtracting a value associated with channel resistance. When Vgs increases, channel resistance decreases. Therefore, the result of a constant subtracting a smaller value is larger than before. It explains the trend of the curves in Fig.5-2 reasonably.

Therefore we can utilize this phenomenon to extract the Poly-silicon resistance which is bias-independent component associated with the materials. We can bias Vgs

carefully little higher than VDD and then the channel resistance reaches an extreme small value which can be neglected. And then Rg_int is equal to Re(Z11-Z12)

0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 varying with Vgs. First, the RD equation mentioned in section 4.1.1 is:

ch

When Vgs increases, channel resistance decreases. Therefore, the constant, Rd_int adds a smaller value and gets a smaller value than before. Base on the former discussion just elaborated, we can bias Vgs carefully little higher than VDD, and then get the intrinsic Drain resistance value which is just associated with the impedance in diffusion region.

This extraction brings two benefits. First, it can exclude the measured resistance error results from the contact between probe tip and pad. Because the contact condition of each time measurement is different, the extracted resistance is influenced by it each time. However, if we can extract the bias-independent component, it must

include the resistance results from the contact. And when we build a resistance model, we can subtract this component first. And then we can be sure the left resistance is associated with channel. Therefore, second, it makes the model more physical.

Originally, we always get a large values need to be fit. Now we at least can build the resistance model as like “RG=Rg_int+R1(Vgs, )” and “RD=Rd_int+R2(Vgs, )” first. And then we start to model the channel performance as the parameter “R(Vgs, )”.

2. Vds=1.2V, Vgs>Vth (average of 38.2GHz~40GHz)

The RG extraction curves under Vds=0 and Vgs=0.5, 1.2V are showed in Fig.5-4.

According to the extraction method expounded in 4.1.1, this method is reliable when the frequency is infinity. However, our measurement is limited by equipment and just up to 40GHz. But the curve is truly flatter when the frequency is higher. Here I sample the values at highest 10 frequency points which are 38.2 GHz to 40GHz.

0 10G 20G 30G 40G

10 20 30 40 50 60 70 80 90

RG

Frequency

V_gs=0.5V V_gs=1.2V

V_gs=1.2 Vgs=0.5

Figure 5 - 4: extracted RG of NF=18 NMOS under Vds=1.2V, Vgs=0.5 and 1.2V

The extracted RG and RD values under Vgs>Vth and Vds=1.2V are showed in Table 5-6 and Table 5-7.

Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 N18 16.498 15.969 15.353 14.825 14.337 13.682 13.38 12.874 N36 11.209 11.156 10.9 10.615 10.323 10.017 9.702 9.366 N72 5.511 6.086 5.94 5.795 5.648 5.501 5.312 5.128

Table 5 - 5: extracted R_G values under V_ds=1.2V (unit: )

Vgs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

N18 30.476 28.296 26.91 26.092 25.515 25.021 24.539 24.024 N36 14.935 14.045 13.547 13.207 12.947 12.708 12.455 12.181 N72 5.934 5.487 5.267 5.117 5 4.891 4.772 4.652

Table 5 - 6: extracted RD values under Vds=1.2V (unit: )

Although the curves really conform to the prediction mentioned in reference paper 4-3 and trend to constants, the substrate effect is still a latent problem. When Vds=0 and Vgs>Vth, the existence of channel resistance causes a small impedance path and then the path through Cjd is ignorable. However, when the transistor is operated at saturation region, the small channel resistance is replaced by a current source and an extreme large resistance. Under this situation, the impedance of the path through Cjd

might not be ignorable.