Chapter 2 Interconnect Capacitance
2.4 Spacer Fringing Capacitance Analysis
2.4.2 Measurement and simulation analysis
“S” in the Table 2-5 represents the distance from poly edge to active region edge. Because the region under Gate-poly is oxide, the equivalent circuit is quite simple. Therefore we can extract the capacitances from the formulas:
) Y C Im(
C
Cgg gs gd 11
The extracted capacitances are showed in Table 2-5.
S=0.07, NF=36 S=0.14, NF=36 S=0.21, NF=36
Cgg_sp=Cgs_sp+Cgd_sp 0.312986 0.281111 0.285417
Table 2 - 3: the extracted Cgg values of test-key (unit: fF/um)
Besides, we build a device structure of test-key and import the source file to Raphael, and then simulating the sum of capacitance values which are coupled from Gate to Source and Gate to Drain.
Moreover, the extracted capacitances include interconnect capacitance because the open pad used for de-embedding just reserve the metals higher than M3. Therefore, the simulated interconnect capacitances should be added. Here I use the tool:
Calibre-xRC to calculate the interconnect capacitance of the test-key. The simulated result is showed in Table.2-6.
S=0.07 S=0.14 S=0.21
Interconnect Cgg_m 0.059084 0.06018 0.069056
Spacer Cgg_sp 0.243308 0.188227 0.164437
sum 0.302392 0.248407 0.233493
Table 2 - 4: the simulated Cgg values of test-key (unit: fF/um)
Comparing Table 2-5 and Table 2-6, we can find the simulated value and the measured values are close. This fact tells up that the simulation is believable and hence, the effects we analyze by the help of the tools such as interconnect capacitance and spacer capacitance are reliable.
Chapter 3
RF Measurement and De-embedding
3.1 RF Measurement
For the purpose of extracting MOS transistor parameters from measured data, on-chip RF measurement is adopted because of its accuracy. The data we get not only includes device’s performance but also the influence of the pad, coaxial cable and equipment. Before we put the die in the probe station, system calibration needs to be performed first to remove the influence of equipment, signal line and make the reference plane locates at the probe tips. (Fig.3-1)
Figure 3 - 1: illustration of RF measurement for a two-port system
2-port system is adopted. (Please see Fig.3-2) It is because our measurement equipment (which will be mentioned in 3.1.2), system calibration technique and de-embedding method (which will be mentioned in 3.2) are mainly for 2-port measurement. We can still design a 4-port test patter to extract parameters, but the measurement system with special calibration techniques, and the de-embedding method are more complicated and not complete enough.
Figure 3 - 2: illustration of RF measurement for a two-port transistor
Typically speaking, the system calibration for on-wafer measurement is done by using a so-called impedance standard substrate (ISS) that can provide high-accuracy and low-loss standards for two-port calibration procedures such as short-open-load-through (SOLT) and through-reflect-line (TRL). The SOLT calibration has been widely used because it is supported by virtually every VNA. [1]
3.1.1 Two-Port Scattering Parameters
It is more suitable for two-port RF measurement to use scattering parameters
(s-parameters) to replace impedance and admittance parameters (z-, y-parameters).
Because when device is operated at high frequency, it is quite difficult to provide adequate shorts or opens, particularly over a broad frequency range. Furthermore, active high-frequency circuits are frequently rather fussy about the impedance into which they operate, and may oscillate or even expire when terminated in open or short circuit. [2]
Please see the figure showed below, s-parameters defines input and output variables in terms of incident and reflected (scattered) voltage waves, rather than port voltage or current. Furthermore, the source and load termination are Z0.
2
The normalization by the square root of Z0 is a convenience that makes square of the magnitude of the various an and bn equal to the power of the corresponding
incident or reflected wave. s11 is simply the input reflection coefficient, s12 is the reverse transmission, s21 is a sort of gain and s22 is the output reflection coefficient. [2]
3.1.2 RF Measurement Equipment
The figure showed below illustrates our setup of HF measurement system for on-wafer RF measurements. ICCAP is used to send the commands to instruments (Agilent E8364B PNA, and HP4142B) and the probing station is to perform the measurements for a specific DUT and to gather the measured data for extraction. [1]
3.2 Two-Port de-embedding
After system calibration is accomplished, the reference plane is located at the probe tips. However, the measured data still includes the pad effects which consist of capacitive, inductive and resistive effects. Our goal is to get the measured data of
“pure” device. It is necessary to remove the parasitic effect of the pads including the metal line connecting signal pad and device. There are some techniques developed to remove these pad parasitic effect which is so-called de-embedding.
3.2.1 Open pad de-embedding
The most conventional and easiest method for obtaining the “pure” transistor’s measured data is to use an extra “open” pad.
When the transistor device is measured with the GSG pad, the layout is like Fig.3-3, the equivalent circuit is as Fig.3-4 and the open pad’s equivalent circuit is as Fig.3-5 and Fig.3-6.
Figure 3 - 3: the illustration of device with pad (S and B are connected)
Figure 3 - 4: the equivalent circuit of device with pad
Figure 3 - 5: the illustration of open pad layout
Figure 3 - 6: the equivalent circuit of open pad
After getting the measured s-parameters from device with pad and from open pad, we transform them to y-parameters and then we can get the transistor y-parameters by subtracting YP1, YP2 and YP3 from the measured data of transistor with pad. Theoretically, after this step, we get the pure measured data of transistor.
We name the y-parameter of device with pad “Ymeas”, and the y-parameter of
3.2.2 Open, short pads de-embedding
The de-embedding method expounded in 3.2.1 has a defect that it neglects pad parasitic series effects of the connecting metal line. When device is very small, and operating frequency is very high, the resistive and inductive effect caused by the metal line should not be neglected. So it is necessary to use one more extra dummy pad such as “short” pad to remove the series parasitic components.
Under the considering of pad parasitic series effect, the equivalent circuit of device with GSG pad is as Fig.3-7. The short pad’s equivalent circuit is as Fig.3-8, Fig, 3-9.
Figure 3 - 7: the equivalent circuit of device with pad
Figure 3 - 8: the illustration of short pad
Figure 3 - 9: the equivalent circuit of short pad
The first step is to get the YP1~YP3 value by measuring open pad and the method is mentioned in 3.2.1. After removing YP1~YP3, secondly, we have to remove ZL1~ZL3. We measure the s-parameters of short pad and transform it to y-parameter, and then use y-parameter matrix calculation to remove YP1, YP2 and YP3 in short pad.
Finally, we transform all measured data to z-parameters and use z-parameter matrix
calculation to remove ZL1, ZL2 and ZL3 in the measured data of device with pad.
Please see Fig.3-10 and the equations are showed below [3].
11
Figure 3 - 10: the illustration of de-embedding procedure
3.2.3 Revised de-embedding method for our case
The de-embedding method mentioned in 3.2.1 and 3.2.2 is based on an important fact that the transistor is under 2-port GSG pad measurement. So, it is necessary to connect Source and Body together inter device and then connect to ground pad (Fig.3-3). However, 4-terminal (Gate, Drain, Source, and Body) MOS transistor is more practical to circuit designer because it is more flexible. They would
like to connect Body terminals to ground line individually to make sure the pn-junction between p-substrate and n+ Drain in nMOS is under reverse-bias and prevent substrate affecting nMOS operation. And designer might bring into Body effect by connecting Body to other node except Source or ground to make his circuit fit specification.
Therefore, the latest sample layout which foundry provides to customers doesn’t connect Source and Body inter-device. We didn’t change the indigenous layout and connect the Gate, Drain to two individual signal pads and connect Source, Body to ground pads separately. (Fig.3-11)
Figure 3 - 11: the illustration of device with pad (S and B are separated)
Furthermore, 4-terminal transistor under 4-port RF measurement and corresponding system calibration, de-embedding methods are continuous developed, but not matured yet and will be very complicated expectedly.
Here I provide a revised de-embedding procedure which comes from my
practical measurement experience. And it is suitable for 4-terminal transistor but under 2-port GSG pad (Fig.3-11).
The equivalent circuit of measured device with pad is as Fig.3-12. I change the characters of the pad parasitic series components for later explanation. Zg_ext means the parasitic effect of the metal line connecting signal pad and Gate terminal of transistor and so do Zd_ext, Zb_ext, and Zs_ext. If the Source and Body are connected together first and then connect to ground pad, Zs_ext and Zb_ext are parallel and can be represented by ZL3 in Fig.3-7.
Figure 3 - 12: the equivalent circuit of device with pad (S and B are separated)
First, I extract YP1, YP2, and YP3 from measured data of open pad (equation 3.1) and then subtract “just” YP1 and YP2 from measured data of device with pad (Fig.3-13 (a)).
Second, I extract Zg_ext and Zd_ext from measured data of short pad (equation 3.2)
and then subtract them from the data after first step (Fig.3-13(b)).
Third, subtract YP3 from the data after second step. The reason subtracting YP3
at last is the YP3 is almost capacitive and contributed by near metals which are located at the end of connecting metal line of port 1 and port 2. The original equivalent circuit shows that the nodes of YP3 are at the pad which contacts probe tip. It is not reasonable that they should be at the terminators of metal lines. So YP3 should be subtracted at last. (Fig.3-13)
Although the metal lines connecting to Source and Body are retained, it is practicable to put external resistance or inductance to fit the measured curve. If we just use the de-embedding method mentioned in 3.3.2 which is designed under the consideration of Source and Body tied together first, it will generates an irrelevant data because of the incongruous de-embedding steps. And the model-building work cannot go on.
Figure 3 - 13: the revised de-embedding procedure
3.3 Extraction of PAD parasitic resistance and inductance
The ZL1 and ZL2 in Fig.3-9 are regarded the same as Zg_ext and Zd_ext in Fig.3-12.
However, each time you raise your probe and put down again to measure, the parasitic series resistances are different. The short pad de-embedding includes measured errors innately. But de-embedding procedure is still necessary because it at least decreases much pad effects from measured data of DUT. We can just observe the pad parasitic series resistance and inductance by the short pads.
The right above figure in Fig.3-10 shows that the short pad equivalent circuit subtracting YP1, YP2. And then ZL1 and ZL2 can be extracted from the formulas which
Chapter 4
Model Parameters Extraction
The extraction work is divided into two steps. First, extracting parameter values and second, using these values as initial values of each component in model equivalent circuit and fine-tuning them to make the simulated curves of equivalent circuit match the measured curves. In the first step, the substrate effect is neglected to simplify the equivalent circuit and make it easier to extract most parameters. I will extract intrinsic resistances and intrinsic capacitances in Vgs>Vth, Vds=0 or 1.2V and then extract substrate parameters in Vgs=Vds=0. Therefore, before second step, we will have many initial values of parameters including interconnect capacitances which are expounded in Chapter 2. There is one point noticeable: in first step, the path through junction capacitance Cjd is neglected because we ignore substrate effect, but the path through Cjs need to be handle carefully because the inductance Ls_ext makes the real part of the impedance see into node “ns” (Please see Fig.4-2) to ground is serious frequency-dependent [Appendix [a.3]].
4.1 Intrinsic Resistance
In Chapter 3, I explain the little revised de-embedding method I use. And I utilize short pad to extract the extrinsic resistances and inductances which result from the connecting metal line between Gate-port1 and Dran-port2. In this section, I will extract the resistances which belong to “intrinsic” transistor. These resistances are so-called intrinsic resistance. The extrinsic resistances have been removed after
de-embedding.
Basically, the intrinsic resistance is composed of two-parts: one is bias-independent which results from process materials such like Poly-silicon, salicide and the other is bias-dependent which results from channel characteristics.
4.1.1 Gate, Drain resistances extraction
1. Vds=0, Vgs>Vth
Here I bring up a new method to extract the Gate and Drain bias-independent resistances. And then extract the channel resistance under Vds=0, Vgs>Vth. In BSIM model card, channel resistance is used to model non-quasi-static (NQS) effect which is a very important parameter when device is operated at high frequency [4]. When a MOS is operated at Vds=0 and Vgs>Vth, the channel is formed. If the operating frequency is very high, the region under the gate is like a distributed, uniform, resistance-capacitance (RC) transmission line.
Figure 4 - 1: channel RC transmission line
In the Fig.4-1, Zch represents the two-port z-matrix of the channel which is a RC transmission line. The total capacitance under gate is Cch and the total resistance is Rch. We can derive the Zch matrix and the result is showed below [5]:
The assumption can be satisfied when the transistor length is very short and the channel opening is higher than 20% of the total channel height. It means that when Vgs is larger, the channel resistance will be smaller and this matrix is more appropriate
[5].
Figure 4 - 2: the equivalent circuit of transistor with gsg pad
The Fig.4-2 represents the equivalent circuit of the device with the pad. The pad part is marked with orange color. On the one hand, the parasitic series resistances and inductances are named with suffix “ext”, on the other hand, the resistances belong to
device are named with suffix “int” such as Rg_int, Rd_int and Rs_int. Besides the channel transmission line, the capacitances coupled between Gate-Source, Gate-Drain, and Drain-Source are named “Cgso”, “Cgdo” and “Cds”. The suffix “o” means overlap.
Because here we define channel capacitance Cch which is always categorized to Cgd
and Cgs, the surplus Cgs and Cgd mainly come from overlap capacitances which are coupling through the overlap thin oxide. Therefore, for clear identification, I name the Gate-Drain and Gate-Source coupled capacitance “Cgdo” and “Cgso”. The junction capacitances between Drain-Substrate and Source-Substrate are represented by Cjd
and Cjs. And the substrate is represented by a resistance “Rbulk”.
After de-embedding (expounded in Chapter 3), the equivalent circuit is represented by Fig.4-3. As mentioned in Chapter 3, the parasitic series resistances and inductances connecting Source-Ground and Body-Ground are retained.
Figure 4 - 3: the equivalent circuit after de-embedding
Figure 4 - 4: the equivalent circuit of mos under Vgs>Vth and Vds=0
As previously mention, the path through Cjd is neglected temporarily but the impedance seen into “ns” to ground is not. This impedance is represented by Zns. According to the analysis [Appendix], the existence of Ls_ext will cause the real part of Zns
serious frequency-dependent. The frequency-dependent components consist of Ls_ext, Rs_ext and Cjs. Besides, the imaginary part of Zns is approximate equal to Ls. Therefore, the equivalent circuit becomes as Fig.4-4 and the z-parameter is showed below which has been modified for our case: [5]
)
According to this matrix, I get an inspiration that we can eliminate the complex component Zns( )by Z11-Z12 and Z22-Z12. Because Vds=0, Cgso=Cgdo, the formulas become:
ch
The two equations demonstrate a good thinking for us. Now taking Re(Z22-Z12) as example. According to the formulas, Re(Z22-Z12) can be divided into two parts: one is Drain resistance (Rd_int) which is gate-bias-independent and the other is half channel resistance which is gate-bias-dependent.
Re(Z11-Z12) is similar to Re(Z22-Z12) except another additional frequency
dependent component ch
gdo constant values, because the bias-dependent component (channel resistance) is reduced to minimum value even approaches to zero under high Vgs. Under this condition, the extracted Re(Z11-Z12) and Re(Z22-Z12) should only be Vgs-bias independent components which result from materials. Therefore, we can extract the bias-independent resistance under high Vgs. But we must be careful that do not give too high voltage in Gate otherwise the device will be damaged.
2. V =1.2V, V >V
Figure 4 - 5: the equivalent circuit of mos under Vgs>Vth and Vds=1.2V
When the device is operated at saturation region (Vds=1.2V, Vgs>Vth), the equivalent circuit is Fig.4-5, and here we ignore the path through the junction capacitance Cjd temporarily. Zns( ) means the impedance seen into node “ns” to ground. Here the resistances are added suffix “sat” to distinguish from the resistance extracted under Vds=0 and Vgs<Vth (Fig.4-3), The components surrounded by dotted box are intrinsic components and can be represented by Yi parameters.
)
And the z-parameters of the full equivalent circuit are [6]:
21i
Here, the equivalent circuit and the z-parameters have been modified little for our case. And then the Gate and Drain resistance extraction equations can be derived:
2
4.1.2 Source Resistance
Because of the existence of Ls_ext which causes some frequency dependent component in measured z-parameters, Source resistance is hard to be extracted from RF measured data. I extract source resistance from DC measurement.
Source resistance will cause gm degradation. According to fundamental electronics, we can derive this formula:
)
Source resistance includes the pad parasitic series resistance. (Rs=Rs_int+Rs_ext in Fig.4-2)
4.2 Intrinsic Capacitance
4.2.1 Vds=0, Vgs>Vth
When Vds=0, Vgs>Vth, the equivalent circuit is like Fig.4-3. And the Z11-Z12 has been derived in section 4.1 which is:
)
According the equation, the imaginary part of Z11 is
) connecting Drain and Source. Therefore, Cch can be incorporated to Drain and Source.
Here I define the Cgs and Cgd as:
Under this bias situation, the transistor is operated at saturation region, and its equivalent circuit is showed in Fig.4-5. Cgg and Cgd are extracted from the formulas:
)
However, these extraction formulas are on a premise that after de-embedding,
the source resistance has been removed completely. In our case, there are two considerations. First: the Source parasitic series inductance is retained and make real part of Zns( ) [appendix] increases with frequency. Second: although we can extract the capacitance at lower frequency to reduce the frequency-dependent effect of real part of Zns( ), the real part of Zns( ), which is approximate to Source resistance at lower frequency, is not zero. When finger number of transistor increases, the gm value will increase and make the current flow through node “ns” increases. And then, the extracted Cgg and Cgd values are inaccurate.
So before extracting the capacitance value, I subtract the Source resistance first to make Vns closer to zero and extract at lower frequency for fear of the frequency-dependent effect of Re(Zns( )):
)
When transistor is operated at saturation region, Cgg is roughly equal to Cgs+Cgd, therefore,Cgs Cgg Cgd
4.3 Substrate Model
Substrate model is very important for RF model. When the device is operated at high frequency, the impedance of the junction capacitance becomes very small.
Therefore, substrate resistance will affect the small-signal output characteristics of the transistor because the small-signal in substrate will go through the junction capacitance to Drain. How to model the substrate effect accurately is an important issue. Here I adopt the model equivalent circuit showed in Fig.4-6.