Substrate Model

When transistor is operated at saturation region, Cgg is roughly equal to Cgs+Cgd, therefore,C_gs C_gg C_gd

4.3 Substrate Model

Substrate model is very important for RF model. When the device is operated at high frequency, the impedance of the junction capacitance becomes very small.

Therefore, substrate resistance will affect the small-signal output characteristics of the transistor because the small-signal in substrate will go through the junction capacitance to Drain. How to model the substrate effect accurately is an important issue. Here I adopt the model equivalent circuit showed in Fig.4-6.

Figure 4 - 6: the equivalent circuit of mos under Vgs=Vds=0

When the transistor is operated at Vgs<Vth and Vds=0, the equivalent circuit is like Fig.4-6. The substrate is represented by Rbulk. Cjd, and Cjs. Cjd and Cjs are junction capacitances and Cgd0, Cgs0 represent gate-to-drain and gate-to-source capacitance.

The suffix “0” means they are under zero Vgs bias. Cgb represents the sum of intrinsic and extrinsic gate-to-body capacitances. Because the device is operated at Vgs<Vth, most intrinsic components of the transistor are negligible. The Gate, Drain, and Source resistance are neglected here because the impedance of them is much smaller than the impedance of junction capacitance and substrate resistance [7].

After deriving the y-parameters of the equivalent circuit, we can get the

However, this extraction method doesn’t match our case because our test-key retains the pad parasitic series resistances and inductances in Source and Body

terminals. The existence of inductance will seriously affect the y-parameters. The extracted parameter curve is not stable with frequency. Nevertheless, this method still supports initial values of Cjd, Cjd and Rbulk for us. I extract the initial values under low frequency and then do some fine-tune work to make the simulated y-parameters curves of equivalent circuit fit the y-parameter curve of measured data.

According the NMOS layout, we can figure out the junction area between Drain or Source diffusion region and Substrate. And then we can derive one capacitance from another. According to the layout, the two-side diffusion regions are Source.

Besides, the areas of the two-side diffusions are little larger than others. The Cjs can be calculated by the equation (0.73 and 0.42 are the edge length of the Drain region and two-side Source region. Please see the figure showed in the left side of next calculated result because one side of the diffusion region is oxide except substrate for the two-side diffusion region. Please see dotted circuit in left Figure. Therefore, this equation provides the initial value of Cjs

from Cjd but we have to decrease little to fine-tune the curve.

Besides, the equivalent circuit in Fig.4-6 doesn’t include Cds which appears in other equivalent circuit. I think the Cds only comes from the interconnect capacitance.

Hence I use the value simulated by Calibre-xRC to represent Cds value. It has been demonstrated in Table 2-4 in Chapter 2.

During my fine-tune process, I find that if I add two additional components to the equivalent circuit of Fig.4-6, the simulated curves will fit measured curves better.

These two components are one capacitance and one resistance in series. Moreover, this series resistance and capacitance are parallel with the substrate resistance (Rbulk of Fig.4-6).

I conjecture that these two components come from the Deep N-Well process which is for RF design to prevent noise going through substrate. When a circuit designer arranges his circuit layout, he can put N-well layer surrounding NMOS and then put a Deep N-well layer in rectangular shape which covers the inner edge of N-well “Ring”. And then, the N-well and deep N-well will be like a bowl and the p-substrate will be protected in it. The pick-up of the N-well is usually bias to the highest voltage to make the junction between p-substrate and n-well reverse-bias. This structure is designed to prevent outside noise into the p-substrate and affecting the performance of NMOS. The instruction of this structure is showed in Fig.4-7.

Figure 4 - 7: illustration of Deep N-well in sectional drawing

Therefore, the additional capacitance results from the junction capacitance between N-well (including Deep N-well and sideward N-well) and p-substrate. I name it “Cdnw“. The additional resistance results from the impedance of the small-signal path in Deep N-well. I name it “Rdnw”. Please see Fig.4-8 as the more clear illustration.

Figure 4 - 8: the equivalent circuit which is added Cdnw and Rdnw

Although I do some fine-tune work, I am not aimless. There are two basic principles: first is getting the value under low frequency to minimum the retained inductive effect; second is following the simplified equivalent circuit for Y22 which is showed in Fig.4-10.

I explain my substrate model extraction steps for summarization:

(1) Operating the transistor at Vgs=Vds=0 and the equivalent circuit is like Fig.4-9. (Rs_int and Rs_ext are summed up to Rs which extracted in section 4.1.2; Rb_ext, Ls_ext and Lb_ext results from our test-key situation which is mentioned in chapter 3; Moreover, Cdnw and Rdnw are added to the circuit.) (2) Extracting Cgs0 and Cgd0 and Cgb from the measured data according to

equation 4.4. Because there is no current flowing into the node “ns”, the

results of revised extraction mentioned in section 4.2 is almost the same as un-revised. However we still extract capacitance from revised extraction method because the initial values of Rbulk and Cjd are extracted at low frequency too.

(3) Rg_int and Rd_int are bias-independent because the channel doesn’t exist.

Their values are extracted from Re(Z11-Z12) and Re(Z22-Z12) under Vds=0 and Vgs is large enough. (Please see the explanation in section 4.1.1.)

(4) According to equation 4.4 and 4.5, and calculating the Rsub, Cjd and Cjs

values. They will vary with frequency. Observing the curves, and take the values under lower frequency (about lower 3 GHz) as initial values for fine-tuning.

(5) Extracting Ls_ext value according to equation 4.6. (This extraction will be explained in next 4.4.) Lb_ext is assumed equal to Ls_ext.

(6) The Cds value comes from simulated interconnect Cds value which is discussed in chapter 2.

(7) After steps (1) to (6), we now have all initial values of parameters in Fig.4-9 except Rdnw and Cdnw. Next, we build a circuit like Fig.4-9 in software: ADS and then simulating its y-parameters. After the calculating and fine-tuning parameters, we can get these parameters final. The calculating equation is showed in Fig.4-10. Basically, the parameters which don’t belong to substrate are not tuned.

Figure 4 - 9: the equivalent circuit of NMOS under Vgs=Vds=0V

Figure 4 - 10: the R , C fine-tuning extraction process