Thesis Organization - 應用於1.5伏特3~10-GHz超寬頻頻率合成器

CHAPTER 1 INTRODUCTION

1.2 Thesis Organization

In order to achieve low voltage, full bands problem, a new frequency synthesizer architecture is used. Chapter 2 describes the detailed specification of IEEE 802.15.3a, design considerations of the frequency synthesizer, then the basic theory of the PLL and the proposed 3~10 GHz frequency synthesizers are introduced. In Chapter 3 shows the circuit realizations and the simulation results of this design. In Chapter 4 shows the measurement results of this design. Finally, conclusion and future work are presented in chapter 5.

Chapter 2

A 1.5-V 3.1~10.6 GHz CMOS Frequency Synthesizer

So far, with the IEEE 802.15.3a PHY standardization activity staggering, an independent effort to draw the UWB regulation policy has been accelerated when various UWB interference tests have been performed to assess its potential harmful impacts on other victim receivers operating nearby UWB devices. For this purpose major groups have participated in the tests. This research has been conducted in order to provide specification on UWB, the underlying next generation wireless network technology, Business Model and to support UWB technology itself by extending its MAC and standard contribution. UWB Forum is expected to recommend a policy by collecting and analyzing the latest UWB technology trends, and thus promote the technical advances in domestic UWB industry. However the system design considerations, theoretical analysis, as well as architecture of the proposed Frequency Synthesizer are discussed and presented in chapter 2.

2.1 Multi-Band OFDM Physical Layer Proposal for IEEE 802.15.3a

The purpose of this task group is to provide a specification for a low complexity, low cost, low-power consumption and high data rate wireless connectivity among devices within or entering the Personal Operating Space. The data rate must be high enough (greater than 55 Mbps) to satisfy a set of consumer multimedia industry needs for WPAN (Wireless Personal Area Networks) communications. There are two types of UWB technology: “DS-CDMA” and “OFDM-UWB”. Motorola and OFDM-UWB

by Multi-Band OFDM Alliance Members including 170 member companies support impulse-UWB, among others. Roughly it can be said that Impulse technology is better for locating, because of the better accuracy, and OFDM can rather be used for data communications because of better multiple access possibilities and better interference robustness. The transmitter of the proposed MB-H-UWB system is shown in Fig. 2.1, the transmitted simultaneously in 13 sub-bands to realize frequency diversity. Then, The FCC requires that UWB devices occupy more than 528 MHz of bandwidth in the 3.1~10.6-GHz band. The band center frequencies are given as:

b b

Band center frequency=2904 528 n (MHz) n+ × , =1...14 (2-1)

Where n_b represents band numbers. Band #1~Band #3 are used for Mode 1 application (mandatory mode), while Band #1~Band #3 and Band #6~Band #9 are used for Mode 2 application (optional mode). The remaining channels are reserved for future use. The UWB system provides a wireless PAN with data payload communication capabilities of 55, 80, 110, 160, 200, 320, and 480 Mb/s. It incorporates orthogonal frequency division multiplexing (OFDM) modulation using quadrate phase shift keying (QPSK). According to the spectrum mask in Fig. 2.2 and Fig. 2.3 the power spectral density (PSD) measured in 1-MHz bandwidth must not exceed the specified 41.25 dBm, which is low enough not to cause interference to other services operating under different rules, but sharing the same bandwidth.

Cellular phones, for example, transmit up to 30 dBm, which is equivalent to 10 higher PSD than UWB transmitters (TX) are permitted. The next chapter focuses on the most important design blocks of the synthesizer.

Fig. 2.1 Frequency plan of MB-OFDM UWB systems

1.6 1.9 2.4

Bluetooth, 802.11b WLAN Cordless Phones Microwave Ovens

PCS

802.11a WLAN Cordless Phones

-41 dBm/Mhz “FCC Part 15 Limit”

Frequency (Ghz) Emitted

Signal Power

3.1 10.6

Note: not to scale

UWB Spectrum

U-NII band

ISM band

GPS

Fig. 2.2 Power spectrum for UWB systems

Fig. 2.3 UWB spectral masks for indoor and outdoor communication systems.

2.2 Role of Frequency Synthesizer and Operational Principle

In a MB-OFDM UWB system, the very wide frequency band is divided into third-teen groups. Then, frequency synthesizers designed at 10GHz such a high frequency are not popular yet, and a frequency synthesizer that can operates from 3.1GHz~10.6GHz needs not only more control signals than usual but also raising the circuit implementation complexity. Besides, a designing work of a frequency synthesizer that covers all band groups is undergoing. In this work, we will prove that the all band is possibly realizable by using the proposed PLL architecture. The block diagram of the proposed Frequency synthesizer is shown in Fig. 2.4, which consists of a PLL Basic (include VCO, VCO buffer, divider, PFD, CP, LF), I/Q quadrature single side-band (SSB) mixers, band-selector and poly-phase filter. The local oscillator (LO)

frequency signal (10.032GHz). The full spectrum is partitioned into four groups and every group except for the fourth one has 3 sub-bands. VCO generates the center frequency of 10032MHz in the fourth group and the reference clock realizes the band spacing frequency of 528MHz and the group spacing frequencies of 5016MHz, 3168MHz, 1584MHz and 1056MHz. The second mixer (Mixer2) by down-converting the group spacing frequencies realizes the 8 sub-bands (3432MHz, 3960MHz, 4488MHz, 5808MHz, 6336MHz, 6864MHz, 7392MHz, 7920MHz) in the first;

second, and third groups are obtained. The fourth group is obtained from the first mixer (mixer1) by down-converting the VCO frequency with the group spacing frequency of 528MHz, 1056MHz and 1584MHz. This frequency generation scheme makes the first-order unwanted sidebands caused by mixing fall outside the 5.544GHz, 6.072GHz and 6.6GHz spectrum so that a lower spur level is achieved. To generate all the required quadrature signals for the SSB mixers, 2-stage poly-phase filters are adopted in this PLL. Then, second harmonics are obtained from the drains of the tail current sources in the NMOS differential buffers. Using harmonics saves chip area and power consumption. In PLL, the clock frequency of 1056MHz and 3168MHz must be generated from a divide-by-3 circuit. The divide-by-2 circuit generated 528MHz, 1056MHz and 5016MHz clock frequency. By using this poly-phase filter and a SSB mixer with switched-capacitor LC tanks, a sideband rejection over 30dB is achieved for every group.

SSB

Fig. 2.4 The proposed 3.1~10.6 GHz frequency synthesizer for UWB applications.

Chapter 3

Design Of The Circuits

3.1

DESIGN CONSIDERATION

In the previous chapter, we proposed wideband PLL architecture to implement a high performance frequency synthesizer with noisy on-chip components. In this chapter, we also discussed the optimization of the loop bandwidth. We pointed out that the optimization of the loop bandwidth depends on the noise spectrum of each individual noise source. And we will discuss the low-noise design of each block in a PLL. The most important block is the integrated VCO. Even though the wideband loop can suppress the noise from the VCO, the suppression may not be enough because the integrated VCO is noisy, and the loop bandwidth cannot go arbitrarily high. A low-noise VCO is crucial in achieving a high performance frequency synthesizer. The phase/frequency detector, loop filter, frequency divider, poly-phase filter and SSB mixer are also important in realizing a high performance frequency synthesizer. The noise from the PFD and frequency divider is multiplied by the divider ratio at the output of the PLL. When a wideband PLL is used, the divider ratio may be reduced. However, because the loop bandwidth is very wide, noise is not suppressed until the frequency is above the loop bandwidth, which is usually above the frequency of interest. The noise from loop filter also has a peak gain depending on the VCO gain and loop bandwidth. Careful design of the loop filter is required to maintain good spectral purity at frequencies around the loop bandwidth. We will discuss how to design all functional blocks later. In this thesis, we focus on design a full bands frequency synthesizer circuit with perfect charge pump to suppress

spurious tone, and quadrature phase output for image-rejected mixer. And we will use SpectreRF to simulate the physical circuit of integer-N frequency synthesizer. A complete 3.1~10.6 GHz frequency synthesizer would be integrated with these building blocks and the simulation results are presented.

3.2

CIRCUIT REALIZATION

Fig. 3.1 shows the architecture of integer-N frequency synthesizer in this thesis.

We will discuss each block in the next section.

SSB

Fig. 3.1 The architecture of integer-N frequency synthesizer in this thesis

528M

3.2.1

Low Phase Noise VCO

As we know, the LC VCO usually uses the cross couple pair as the negative resister.

The VCO can roughly divide into two kinds. They are N-MOS (P-MOS) only cross-coupled VCO and complementary cross-coupled VCO. It has been mentioned in [2] that the complementary cross-coupled VCO has the better phase noise than the N-MOS or P-MOS only cross-coupled VCO.

3.2.2.1 Trade-off between Kvco and tuning range

In this design, there is another trade-off become more critical. Because the VDD becomes lower, the output voltage range of the charge pump is suppressed. So, the KVCO must be increase to maintain the same tuning range. But if the KVCO is larger, the VCO is more sensitive to the noise that comes from the control voltage.

An ideal VCO’s mathematic expression is

) tion of time. Assume the

(28) Put it into (27) and assume

ωout =ωo +Kvco∫Vcontdt+φo

In fact the V_cont is a func V_conthas a small sinusoidal noise above its DC level.

ω , then the VCO’s mathematic expression will be rewritten as follow.

)]

So, consists of three components, those tones at are

When the spur appears in the local frequency of RF receiver, it wills decade the SNR

) out (t

V ωo ±ωm called spur.

after demodula

all as possible, the VCO output will has mu aller spur level.

VCO circuit is shown in Fig. 3.2 and Table 3.1 show VCO Dates. The operating frequency is decided by resonate frequency of the LC tank. But because the

ductor and capacitor are not ideal, they have parasitic resistance. Without the

negat te, because of the left half plane poles.

So w

Fig. 3.2 VCO circuit tion.

As it is seen in (29), the sidebands’ amplitude relates to the value ofK_vco. So, if we

can let the K_vco as sm ch sm

3.2.2.2 Band-switching VCO The

ive resistance, the circuit will not oscilla

e add the parallel negative resistance to insure the VCO can oscillate. In Fig. 3.2 the cross-coupled PMOS and NMOS are two negative resistances, spiral inductor shown in Fig. 3.3 realized the inductor and the equivalent model is shown in Fig. 3.4 and the two MOS varactors are used here to make oscillating frequency be tunable shown in Fig. 3.5.

Table 3.1 Detail parameters of the VCO.

M_1~2 8 um / 0.18 um m=10 M3~4 20 um / 0.18 um m=10

M5 20 um / 0.18 um m=20 L₁ w=30 um r =65 um nr= 1 Varactor l=0.5 um w=2.5 um br=10 g=1

Fig. 3.3 Layout of spiral inductor

Fig. 3.4 Equivalent circuit of the spiral inductor

p1 p2

Ls Rs

Cox1 Cox2

Csub Rsub Csub Rsub

Fig. 3.5 MOS varactor layout structure

The ideal 4-bits VCO output frequency vs. the control voltage is shown in Fig. 3.6 the frequency range of VCO is split into four bands. By this way, the KVCO can be lower to about 1/4 of the original KVCO, and the spur level will be decade.

Fig.3.3 and Fig. 3.4 show the layout and equivalent model of the spiral inductor.

We can see the inductor value is decided by the Ls, and Rs is the parasitic resistance that is canceled by the negative resistance. The one-port S-parameter simulation result is shown in Fig. 3.7. The simulated inductance of the inductor is decreased with increasing frequency and the inductance is about 284.664 pH and Q is above 16 when the frequency is larger than 10GHz.

Fig. 3.6 The ideal 4-bits VCO output frequency v.s. control voltage.

Fig. 3.7 Inductance and quality factor (

LC-VCO, the accumulation type has been a popular choice for VCO varactors. The cr

node of the VCO (LO_P~LO_N), for which the output signal quality would be less degraded by the substrate noise and the frequency tuning range could sustain for less parasitic capacitance seen there. With the aid of these features mentioned above, a VCO with wide frequency tuning range can be realized. The simulated C-V characteristic at 10 GHz is shown in Fig. 3.8 and the varactor has a Cmax /Cmin ratio of about 4.2.

Q : ~16

Q) of the proposed inductor.

As for the MOS varactors used in the

oss-section view of an n-type AMOS varactor is shown in Fig. 3.5. Adjusting the voltage across its G and D/S terminals alters the capacitance and the DN-well is used to reduce the parasitic capacitance and noise from substrate. While the connection of the varactor between its control voltage and VCO output nodes, LO_P and LO_N, is important: the gate terminal of the varactor is better connected to the output

Fig. 3.8 Varactor C-V curve

3.2.2

Frequency Divider

The most delicate piece of the divider is the first divide-by-two stage and divide-by-three stage and challenging compare to other building blocks in the frequency synthesizer. First, the divider operates at the highest frequency and it must still functions properly under the process and temperature variation. Furthermore, it must generate quadrature outputs. At last, in our architecture, the output load of the first divide-by-2 circuit contains not only the next stage divider and wiring capacitance but also two buffers for Band-selectors. This means the load capacitance will be very large, nearly 200fF in our design. The divide-by-two stage and

divide-by-three stage separately work at 5.016GHz and 3.168GHz. Given the high frequency and the necessity to have a differential structure, very few approaches work for us. First, we simulated many different structures of dividers. To avoid polluting the substrate, the differential structure has been chosen over the single-ended one although the latter possesses all the other advantages. The need of a differential clock is not a problem since we already have a differential signal coming out of the VCO.

The differential dividers are realized with current-mode logic (CML) flip-flops. Fig.

3.9 shows a typical CML flip-flop. It consists of a master and an identical slave latch that are clocked on opposite clock phases. In the Fig. 3.10 The latch consists of resistance loads (R1-R2), gain stage (M91-M92), positive-feedback transistors (M93- M94) for latching, clocked differential pair (M95-M96) and current source (M97).

Transistor M97 provides the latch with a constant current and minimizes the noise injection into the power supp ucture does not provide full ing at its output. Due to the number of stacked transistors, the NMOS tend to suffer f the body effect and that degrades the speed of the structure since the devices are in resistance is larger. In order to have the FF work at more

ly and ground lines. This str sw

the triode region and thus their

than 5.016GHz, we had to remove the current source transistor (M97). This new FF works at a higher speed but consumes also more current. It is also more prone to process variations since the swing is only dictated by the transistor sizes. The right size ratio has to be found between the NMOS and the PMOS devices to balance the rise and fall times as much as possible. For the CML structure, the use of doughnut may help at certain nodes of the structure but it will increase the source capacitance, which might be a problem with the stacked structure. Due to the timing of divide-by-3 is critical, the cells of AND0 and AND1 as shown in Fig. 3.10 has to integrate into cells DFF_AN0 and DFF_AN1 to reduce the propagating delay. In a typical PLL type

frequency. The logic block diagram of the divider is shown in Fig. 3.9 then the upper block diagram is a divide-by-2 circuit with frequency up to 5016MHz. The below block diagram is a divide-by-3 circuit with frequency up to 3168MHz. The first divide-by-two consumes about 16.37mA; the amplitudes (peak) are 0.76V, then the first divide-by-three circuit consumes about 7.077mA; the amplitudes (peak) are 1.27V.

(a)

(b)

Fig. 3.9 (a) Logic block diagram of the Divider_by_two_stage (b) Divider_by_three_stage

(a)

(b)

Fig. 3.10 (a) D Flip-Flop Stage (b) D Flip-Flop Stage with builds in AND gate

V bias

C L K + C L K

-D + D

-R 1

O ut+ O

ut-V D D

R 2

M 91 M 92 M 93 M 94

M 95 M 96

M 97

3.2.3

Phase Frequency Detector

A conventional three-state phase detector has been used in this design. The three-state phase detector is widely because it is simple, has a linear range of ±2π radians, and can act as phase and frequency detector. A state diagram for the circuit is shown in Fig. 3.11 (a). Base on the state diagram it can be implement as Fig. 3.11 (b).

(a)

D C K Q

"1 "

Q C K

"1 "

Q_A

Q_B R e s e t

(b)

A B Q_A Q_B

0 0 1 0 1 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2

State:

(c)

Fig. 3.11 (a) PFD block diagram (b) PFD state diagram (c) PFD timing diagram

The timing diagram of three-state PD has been illustrated in Fig. 3.11 (c). Let’s combine PD and charge pump, Fig. 3.12, and deriving its transfer curve as shown in Fig. 3.13. The action of a three-state PD as a frequency detector is now clear.

Fig. 3.12 Block diagram of charge pump and PFD

For f^V﹥f^R, θe decreases with time, and Ip remains negative. For f^V< f^R, θe increase with time, and Ip remains positive. This is a great aid in acquiring lock when the two frequencies are initially different [20].

Fig. 3.13 PFD transfer curve when (a) f^R>f^V(b) f^R>f^V

In Fig. 3.11 (b), static logic blocks such as D-type flip-flop (DFF's) and NAND gates are used. Note that the D-input of the two DFF's are always at high logic-level.

Hence simplified static DFF's that hides the D-input can be found constructed by only four NOR gates or four NAND gates [21]. Fig. 3.14 is the PFD circuit in our design.

Fig. 3.14 Phase frequency detector

When this type of phase detector incorporated with charge pump circuit, it has a drawback that exist a dead zone, as shown in Fig. 3.15. If the reset signal is not delayed sufficiently. That will cause the output of charge pump dies not change for small phase error thus the dead zone translates to jitter in PLL and must be voided. In Fig. 3.14, the delay chain is increased delay of reset signal for eliminating dead zone.

Fig. 3.15 Dead zone in PFD

3.2.4

Perfect Current-Matched Charge Pump

In this design the current-steering charge pump is used. But the current-steering charge pump still suffers from the current mismatch issue. So, the current-match technique is used in this design.

3.2.1.1 Current-match charge pump

Because of the effect of channel length modulation, in the conventional current-steering charge pump circuit Iup and Idown cannot mach at whole Vc voltage, even if M10 and M11 are sizing as the ratio of their mobility ratio and same over-drive voltage. At every reference clock edges, the I and I will both turn on

for a

(a)

very short time to cancel the dead zone effect of PFD. At this moment, if the Iup

and Idown are not match each other, the mismatch current will become noise to next stage (LPF). This noise will increase the spur level of VCO output spectrum. Fig. 3.16 shows the current-match charge pump circuit. The current-match charge pump has a function, which can make the up and down currents match each other.

(b)

Fig. 3.16 (a) Sinking/Source Current in CP (b) Current-Switching CP Circuit

Fig. 3.17 shows the half circuit of Fig. 3.16 and it can be equivalent to unit gain buffer. We can view the error-amp as the first stage, the M17 is the second stage amplify and the M18 in triode region serious with M19 in diode connecting. The third stage is common source amplify M13 with the output load rO12//rO13. Those stages amplify the difference of Vc and Vtrace. And the negative feed back to Vtrace. We can iew these three stages as an op-amp as Fig. 3.17(b) shows. This is a voltage follow buffer and it means the Vtrace will tracing Vc when Vc varies it value. So, we can

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