S IMULATION R ESULTS - A 1.5-V 3~10 -GHz CMOS Frequency Synthesizer

CHAPTER 2 A 1.5-V 3~10 -GHz CMOS Frequency Synthesizer

3.3 S IMULATION R ESULTS

Fig. 3.27 Charging simulation of charge pump (a) reference clock. (b) Divider output. (c) the control voltage of VCO. (d) Iup and Idown of the charge pump.

In the Fig. 3.27, the charge pump is in charging mode. In Fig. 3.27 (a) and (b), we can find that the phase of the reference clock goes beyond the divider output and the frequency is higher than the divider output. So, the charge pump charges between the

clock falling edges of r. So, the control

voltage is getting higher.

the reference clock and output of divide

ig. 3.28 Discharging simulation of charge pump (a) reference clock. (b) Divid

F er

output. (c) the control voltage of VCO. (d) Iup and Idown of charge pump

edges of the reference clock and divider output. So, the In the Fig. 3.28, the charge pump is in discharging mode. In Fig. 3.28 (a) and (b), we can find that the phase of the reference clock goes behind the divider output and the frequency is lower than the divider output. So, the charge pump discharges between the clock falling

t current-match structure (a) The Iup and I n at Vc=0.3V (b) The Iup and Idown at

Fig. 3.29 Simulation results of the current-steering charge pump withou

dow

Vc=0.75V (c) The Iup and Idown at Vc=1.3V (d) The mismatch current v.s. Vcontrol

Fig. 3.30 Simulation results of the new current-match charge pump (a) The Iup and Idown at Vc=0.3V (b) The Iup and Idown at Vc=0.75V (c) The Iup and Idown at Vc=1.3V (d)

The mismatch current v.s. Vcontrol.

Fig. 3.31 The mismatch current simulations of charge pump with process variation, and compare the results with the charge pump without feedback loop.

The current-steering charge pump without feedback loop is simulated in Fig. 3.29 (a) to (c) shows Iup and Idown at different Vc and we can find that the Iup and Idown just match at Vc=0.75V. In Fig. 3.29 (d) shows the mismatch current at different Vc. The maxim difference between Iup and Idown is about 20% of the charge pump current.

The current-match charge pump which used in this design is simulated in Fig. 3.30 (a) to (c) shows Iup and Idown at different Vc and we can find that when the Vc varies, Iup and Idown still match to each other. In Fig. 3.29 (d) shows the mismatch current at dif

Fig. 3.31 shows the pro -match charge pump. We

can find that even if the variation up to 10%, the mismatch current is smaller than witch without feed back loop.

ferent Vc and the maxim difference between Iup and Idown is about 1.5% of the charge pump current.

cess variation impact of the current

(a)

(b)

)

(d)

Fig. 3.32 The simulation results of the band-switching VCO (a) The output waveform of the VCO (b) The phase noise simulation results by Spectre-RF (c) The tuning ranges of the sixteen bands simulation (d) Spurious tones simulation.

VCO Output Frequency ( GHz )

Control Voltage ( V )

0000

The simulation results of the VCO are shown in Fig. 3.32. The differential output waveforms of VCO are shown in (a) and the peak-to-peak amplitude is 1.55V. The phase noise of VCO is simulated by Spectre-RF and is shown in (b). In (b) we can find that the phase noise at offsets frequencies 1-MHz is –111.6dBc. This performance is suitable for UWB application. The tuning

As mentioned in 3.2.2.2, the 4-bits band-switching VCO uses mimcap as the bank and split the tuning range into 16 bands as show in (c). When the control word of bank is 0000, the bank has the maximum capacitance. So, the VCO has the minimum frequency band. On the contrary, when the control word is 1111, the VCO changes the frequency band to the maximum frequency band. Beside, when the control word

VCO changes to the middle band. In (e) is the simulation of spurious tones about 51dBc@528MHz

range of the 4-bits VCO is shown in (c).

changes to 0111 or 1000, the frequency band of

– offset.

Fig. 3.33 The close loop simulation of the PLL (a) The control voltage of VCO (b) The reference clock and the output waveform of counter

The close loop simulation of the frequency is shown in Fig. 3.33. The Vc which controls VCO is shown in (a) and we can find that it is locked within 1 usec. Fig 29 (b) shows the reference clock and the output waveform of counter. We can find that the edges of reference clock and output of counter match to each other. This means that the frequency synthesizer is locked.

(a)

(b)

(c)

Fig. 3.34 Simulation results of the Divider (a) Divide-by-2 Stage for 5016MHz (b) Divide-by-3 Stage for 3168MHz (c) Divide-by-2 Stage for 1584MHz

(a)

(b)

Fig. 3.35 Simulation results of the Band-Selector (a) Output Amplitude of the Band-Selector1 (b) Output Amplitude of the Band-Selector2

The simulation results of Divider and Band-Selector are shown in Fig. 3.34 and Fig.

3.35. In Fig. 3.34 the divider is dividing 2 and 3. Then, the minimum peak-to-peak amplitude is 760mV for a 5016MHz sinusoidal output. In the Fig. 3.35, the Band-Selector1 frequency control in turn 1584MHz、3168MHz、5016MHz, the Band-Selector2 frequency control in turn 528MHz、1056MHz、1584MHz. Then, The minimum peak-to-peak amplitude is 725mV for a 5016MHz sinusoidal output.

8448 8976 9504

3696 4224 4752 5280 5808 6336 6864 7392 7920 8448 -2.0

(c)

Fig. 3.36 The simulation results of the Mixer (a) Mixer1,3 Conversion Gain (b) Mixer2 Conversion Gain (c) Output waveforms for a 3.432GHz sinusoidal output.

The simulation results of mixer are shown in Fig. 3.36. As shown in (a) (b) the voltage conversion gain of the all mixers are above 0dBm for UWB application. In Fig. 3.36(c), the minimum peak-to-peak amplitude is 770mV for a 3.432GHz sinusoidal output.

(a)

(b)

(c)

Fig. 3.37 The simulation results of the spurious and switching time (a) In-band spurs response at 3.432 GHz (b) Out-of-band spurs response at 3.432 GHz (c) Switching time between adjacent bands.

The simulation results of the spurious and switching time are shown in Fig. 3.37.

As shown in (a) and (b), the additional in-band spurs are generated at 6.864GHz with spurious response of –35.2 dBc, and out-of-band spurs are generated at 14.784 GHz with spurious response of –42.8 dBc respectively. In (c) the bands are switched periodically and the synthesizer output is monitored. The longest switching time is approximately equal to 911ps.

Table 3.3 The summary of the post-simulation

Post-simulation

Supply voltage 1.5 V

Frequency range 3.432~10.032 GHz

Reference clock 528 MHz

KVCO (VCO gain) 160MHz/V

Phase noise (using SpectreRF) -112 dBc/Hz @1MHz offset

Charge pump current 100uA

Loop bandwith 5500 kHz

Close loop PM 65^o

PLL lock time 500 ns

Switching time 0.911ns

In-band spur Out-of-band spur

-35.2dBc -42.8dBc

Mixer conversion gain >0dBm

Chip area 1900 X 1900 um^2

Power consuming 50.07~147.35 mW

Technology TSMC 0.18um CMOS

Chapter 4

Experiment Results

The chip, UWB frequency synthesizer for UWB applications is designed and fabricated in TSMC 0.18-μm CMOS process. In this chapter, the chip layout, test environment, and experiment results are presented. Measured performance is compared with post-simulation results and discussion is made for further study.

4.1 Layout Description

The chip is designed and fabricated by TSMC 0.18μm 1P6M CMOS technology.

The process is implemented to fulfill the applications for mixed signal/RF, such as inductor with low receptivity and good conductivity and lower capacitance to substrate. Besides, deep n-well topology is employed to surround the N-MOS device, which allows the connection of source and body terminals to avoid body effect.

Dummy gates and dummy resistors are equipped at the margin of every MOS device to cope with process variation. The MOS varactors are separated into two groups, one with deep n-well while the other without. With the aid of deep n-well, parasitic capacitance and noise coupling from substrate can be reduced. Meanwhile, the MIM capacitor in this technology is somehow special, with or without under ground metal shielding is provided: the former has high immunity to substrate noise and the latter presents less parasitic capacitance.

In the experimental chip, all of the function blocks including PLL, Mixer, Band-selector, and Poly Phase Filter circuits are integrated on the same chip. The overall layout is shown in Fig. 4.1. We present the measured results, the spurious

350MHz which be compared with simulation. The phase noise is -106 dBc/Hz @ 1MHz offset is achieved. The power consumption is 55.1~161.62 mW. The overall area is 1900μm×1900μm.

Fig. 4.1 The frequency synthesizer layout view.

4.2 Measurement Results of the Frequency Synthesizer

Fig. 4.2 Measurement setup of the frequency synthesizer

In Fig. 4.2 we show the measurement setup diagram of frequency synthesizer.

And the input reference signal is provided by AWG. At the output terminals, a BALUN converts differential output to single output and feeds this output to spectrum analyzer and microwave oscilloscope. At the output terminals, a BALUN converts differential outputs to single output and feeds this output to spectrum analyzer. We can measure the spurious tone, phase noise and lock time on spectrum analyzer. And measure the switching time on microwave oscilloscope.

As shown in Fig. 4.3, the chip is bonded on a testing module. On this testing module. At the center of the testing module, a SMD packaged BALUN “BL2012”

made by Advanced Ceramic X corporation converts differential output to single output and connects to spectrum analyzer by a SMA at lower side. All DC bias terminals are connected to a bias board by pin headers. All pin headers at outer side are grounded to provide some shielding ability.

Mixer2 output VCO

output

Mixer1 output

Divider output Reference

clock

Fig. 4.3 Testing module of frequency synthesizer

4.2.1

Measurement Results of the Band-switching VCO

The simulation and measurement of the band -switching VCO are shown in Fig. 4.4 and Fig. 4.5. The measurement result shows that the frequency range shift down about 350 MHz, but the tuning range is similar than simulation and the VCO frequency meet requirement. Initially, the 16 bands are designed to cover the unexpected process variation and the reduction in the tuning range. Therefore, some bands are indeed redundant as shown in the measurement results. The KVCO is calculated for every 0.1 V step of the control voltage and the KVCO of the tuning range is 160 MHz/V. The summary of VCO measurement and simulation results is shown in Table. 4.1.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

VCO Output Frequency ( GHz )

Control Voltage ( V )

0000

Fig. 4.4 The tuning ranges of simulation result.

4.5 The tuning ranges of measurement result.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

VCO Output Frequency ( GHz )

Control Voltage ( V )

0000

Table 4.1 VCO summaries

Post-simulation Measurement

VDD _VCO (V) 1.5 V 1.5 V

Frequency Range (GHx) 9.6~10.6 9.27~10.25

160 160

VCO Gain (MHz/V)

Phase Noise@1MHz (dBc/Hz) -111.6 -106

Current Consumption (mA) 10 11.4

.2.2

Phase Noise and Lock-Time Measurement Results ons

4

In Fig. 4.6 show the performance of phase noise when the measurement conditi are VCO frequency at 10.032GHz, reference frequency is 528MHz and loop bandwidth is 5500 kHz. In chapter 3, we mention that the phase noise should benefit from wider loop bandwidth of frequency synthesizer. Indeed, the phase noise of 5500kHz loop bandwidth is lower in this measurement, and it will be improved by paralleling larger capacitance to supply node. While paralleled capacitor is increased from 0.1uF to 22.1uF then the phase noise is decreased about 10dB. Thus, we must care the supply quality to get better performance of phase noise. The measurement results show that the phase noise performance is -106dBc/Hz at 1 MHz offset. In Fig.

4.7 shows the settling time measurement results, the settling time is about 600 ns.

Thus, the settling time is a little large than simulation result.

Fig. 4.6 Phase noise measurement result, -106.48 dBc/Hz at 1MHz offset

ig. 4.7 Lock time measurement result F

4.2.3

Spurious-Tones and Switching-Time Measurement

There are 2 types of spurs in this synthesizer. One type of spur is caused by the Results

frequency mixing with 528MHz in mixer1. Hence, the spurs in the fourth group will decide those in other groups. Fig. 4.11 shows the sideband rejection at 8976MHz.

Mixer1 provides 34dB suppression of the unwanted sidebands. The other type of spur is due to cascading mixers. Although fifth-order unwanted sidebands have been prevented by the frequency generation scheme in Fig. 4.12 higher-order spurious tones must be taken into consideration when the groups are down-converted by mixer1 and mixer2. The worst case occurs in the first group in Fig. 4.8 is –30.6dBc.

The 3rd harmonics on the RF and LO ports of mixer2 will generate spurs in the adjacent group. The frequencies of he spurious tones are given, with the center frequency of 3432MHz in the first group, the RF frequency is 5016MHz and the LO frequency is 8448MHz, which introduces spurs at 6600MHz and 11616MHz.This effect can be observed by monitoring the whole UWB spectrum and noting that the sideband rejection is over 32 dB because the 2-stage SSB mixer was used. Other spurious measurement results in Fig. 4.9 and Fig. 4.10 are –46dBc and –32.6dBc. The band switching behavior is shown in Fig. 4.13 and the frequency switching time is about 3.75ns, a value much less than the 9.5-ns guard interval denned in UWB. The switching time are influenced by three sources: ① mixer turn on time, ② Poly-phase filter switch time and ③ band-selector switch time. The best switching time is probably 3.75ns, but the worst switching time is probably 15.1ns. The reason of the difference of the switching time is that the function generators used to switch bands are asynchronous, so in the different switching situation, the switching times are also different.

Fig. 4.8 Measured SSB mixer2’s spurs in the first group (<-30.6dBc)

Fig. 4.9 Measured Divider’s spurs in the second group (<-47dBc)

Fig. 4.10 Measured SSB mixer2’s spurs in the third group (<-32dBc)

1 Measured SSB mixer1’s spurs in the fourth group (<-34dBc) Fig. 4.1

Fig. 4.12 Measured VCO’s spurs in the fifth group (<-45dBc)

Fig. 4.13 Band-switching behavior (From group 3 to group 1)

3.75ns

4.3 Summary of Measurement Results

Table. 4.2 and Table. 4.3 summarize the chip performance of frequency synthesizer. And the tables summarize all measurement results compared with the post-simulation outcome and other architecture.

Table 4.2 Summary of the performance of the frequency synthesizer

Post-simulation Measurement

VCO 1.5 1.5

MIXER 1.5 1.5

VDD (V)

DIVIDER 1.5 1.5

Channel spacing (MHz) 528 528

Lock time (ns) 500 600

Switching time (ns) 0.911 3.75

VCO gain (MHz/V) 160 160

Frequency band (GHz) 3.1 ~10.6 3.1~10.6

Tuning range (GHz) 9.6~10.6 9.27~10.25

Loop bandwidth (kHz) 5500 5500

Phase noise@1MHz (dBc/Hz)

-111.6 -106

In-Band spur (dBc) -35.2 -30.6

Out-of-band spur (dBc) -42.8 -40

Total power(mW) 50.07~147.35 55.1~161.62

Table 4.3 Performance comparison with other UWB frequency synthesizer

Chapter 5 Conclusion and Future Work

5.1 Conclusions

A 1.5-V frequency synthesizer with integrated PLL, mixer, band-selector, and poly phase filter for UWB applications has been designed, fabricated and tested in a 0.18-µm CMOS technology. The architecture of the frequency synthesizer is simple and suitable for low power and high data-rate UWB applications. Though seven inductors are used in this design and the frequency synthesizer occupies an area of 1900µm×1900µm, this is mainly dominated by the output pad and a large region on the chip is filled with dummy metal, poly and oxide required to raise the yield rate;

subsequently, base-band circuits can be further combined and drawn in place of the region of dummy layers.

The frequency synthesizer is tested under 1.5-V supply, except the supply voltage of VCO frequency being adjusted lower due to the oscillating frequency drift, The measurement result shows that the frequency range shift down about 350 MHz, but the tuning range is similar than simulation and the VCO frequency meet requirement. This work is measured and has the following performances. The in-band spurious signals of Group #1~ Group #5 are measured after adjust the bias voltages.

The worst case occurs in the first group, the measurement result about -30.6dB. Then out-band spurious measurement result about -40dB.The phase noise is -106dBc/Hz

@1MHz offset, locking time is 600ns and switching time is 3.75ns(From Group 5 to Group 1). The total power consumption is 55.1~161.62mW. The power consumption mostly increases in mixer to compensate the loss of the parasitic resisters and caps.

5.2 Future work

The proposed frequency synthesizer for UWB applications could be fabricated again with the cut MIM-caps in VCO by adjusting the center frequency. This would help provide the required carriers for entire UWB bands. Furthermore, for more thorough and complete frequency synthesizer design, the MUX output test buffer can be included, to avoid signal become smaller and current consumption more large. The large current consumed also appears in other functional block of the UWB frequency synthesizer, the summary of current consumed as shown in Table. 4.2 For lower battery operation, this frequency synthesizer must reduce its current consumed. It also appears the poor performance of spurious tone, which is –30.6 dBc@ 3432MHz. The reasonable value is smaller.

Finally, a full understanding of UWB system and a more careful consideration are essential to design and implement a frequency synthesizer for UWB applications.

There is still large improvement available in this design.

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在文檔中應用於1.5伏特3~10-GHz超寬頻頻率合成器 (頁 53-0)