Perfect Current-Matched Charge Pump

In this design the current-steering charge pump is used. But the current-steering charge pump still suffers from the current mismatch issue. So, the current-match technique is used in this design.

3.2.1.1 Current-match charge pump

Because of the effect of channel length modulation, in the conventional current-steering charge pump circuit Iup and Idown cannot mach at whole Vc voltage, even if M10 and M11 are sizing as the ratio of their mobility ratio and same over-drive voltage. At every reference clock edges, the I and I will both turn on

for a

(a)

very short time to cancel the dead zone effect of PFD. At this moment, if the Iup

and Idown are not match each other, the mismatch current will become noise to next stage (LPF). This noise will increase the spur level of VCO output spectrum. Fig. 3.16 shows the current-match charge pump circuit. The current-match charge pump has a function, which can make the up and down currents match each other.

(b)

Fig. 3.16 (a) Sinking/Source Current in CP (b) Current-Switching CP Circuit

Fig. 3.17 shows the half circuit of Fig. 3.16 and it can be equivalent to unit gain buffer. We can view the error-amp as the first stage, the M17 is the second stage amplify and the M18 in triode region serious with M19 in diode connecting. The third stage is common source amplify M13 with the output load rO12//rO13. Those stages amplify the difference of Vc and Vtrace. And the negative feed back to Vtrace. We can iew these three stages as an op-amp as Fig. 3.17(b) shows. This is a voltage follow buffer and it means the Vtrace will tracing Vc when Vc varies it value. So, we can calculate the gain of op-amp in Fig. 3.17(b) as follow.

v

(a)

(b)

Fig. 3.17 (a)The feedback loop of the current-match charge pump shows in fig 3-1,

Assume the gain of the first stage error-amp is Aerror. Than the next stage a PMOS common source stage, and the gain is as follow

19 equivalent resistor of M19 in diode connecting.

The third stage is also a common source stage and its gain is as follow The overall gain of the feedback loop is

)

Then assume the difference between Vc and Vtrace is Verror

)

And the channel-length modulation coefficient isλ≅0.2. So, if we assume the maximum (Vc-1/2VDD) is 0.3V. According to the square law of MOS

The mismatch current _{up down}

open

So, if the Aopen is large than 22.27 dB, the current mismatch will less than 1%.

In simulation, when Vc is equal to 0.8 V and Aopen is 30 dB, the current mismatch is about 1.06%.

3.2.1.2 The Input rail-to-rail Op-amp Used in the Current- match charge pump

The error amplifier is shown in Fig. 3.18. To make sure the MOS away from weak inversion, the gate drive voltage, Vgs-Vt, always to be 150mV~250mV, we can obtain gate drive voltage by SpectreRF simulation. If assume gate drive voltage is

plifier is among

ability for rail-to-rail input operating.

200mV and VDD is 1.5V, thus Fig. 3.18 will operate normally at Vc=0.2V~1.3V. The operated voltage of Vc means that the input voltage of error am

0.2V~1.3V, close to ground and supply voltage, thus the error amplifier must have the

Fig. 3.18 Operation amplifier for rail to rail input

3

The loop filter is an important block in a synthesizer because it determines most of

the system speci oise performance, spur level and locking

tim onvert a discrete-time current signal to a

continuous dc-like signal to control the voltage-controlled oscillator. Besides, it filters

function:

Where

Fig. 3.1 (a) 2^nd-order Fig. 3.19(b) 3^rd-order fications such as phase n

e. It is a low pass filter that will c

out all high frequency noise in the close-loop circuit. Conventional 2^nd-order loop

filter is shown in Fig. 3.19(a) by making circuit analysis; we can get its transfer

As we can see, 2^nd-order loop filter has two poles and one zero. If we incorporate it

n ms a 3^rd-order close-loop system. For the purpose of getting

bett

simulation is made by SpectreRF. The macro model is in Fig. 3.20. The

circuit blocks are idealized with voltage control voltage sources and voltage control

current sources.

arameters, gain of the voltage-controlled oscillator, Kvco=160MHz/V.

harge pump current, Icp=100uA. Counts of the divider, N=18.

into a sy thesizer, it for

er noise performance, one may adopt a 3^rd-order loop filter in Fig. 3.19(b).

However, it is a little bit hard, complicated to get the value of the components and the

additional resistance, R4, will induce extra thermal noise. Most important of all, we

are also limited to design the loop filter with the small area constraint for on-chip loop

filter in addition to other specifications.

To verify the loop filter and decide the close-loop characteristics of the synthesizer,

behavioral

Given p

C

Fig. 3.20 Behavioral simulation setup

Then we can get Cz =3pF, Rz =43.15kΩ, Cp=0.156pF, Phase Margin=65˚. The

simulation result is in Fig. 21.

Fig. 3.21 Behavioral simulated results crossover frequency = 5.5MHz Phase Margin = 65 ˚

3.2.6

Single Sideband Mixer

The SSB Mixer (image-reject Mixer) in this architecture was designed, the center operating frequency is chosen at 3432 ~9504MHz. The mixer translates the RF signal at the frequency band from 528 MHz-5.016 GHz to the base band signal. Among the proposed active mixers, the Gilbert-cell mixer has been widely used so far, and the double-balanced mixer topology has been preferred since it can suppress (LO) leakage signals at the output. Fig. 3.22 is the conventional double-balanced CMOS Gilbert Cell mixer. The Tran conductance stage consists of M115 and M116, and current-commutating stage comprises M11~M114. R1 ~R2 is the load resistor. M115 and M116 always operate in the saturation Region. LO power must be carefully is approximated by a s

mixer can be determined by the following expression:

Voltage gain equation:

chosen such that M111-M114 periodically turn on. Assume LO

inusoidal wave and gm1 = gm2 = gm, then the voltage gain (Av) of the Gilbert Cell

( )

Where gm is the transconductance, RL is the load resistor.

From (5), conversion gain is increased with higher load resistors, but the supply voltage is kept constant. The simultaneous achievement on these requirements is a very challenging task in the mixer design. Especially, the high linearity requirement is the most difficult one to achieve since the mixer is required to operate at a very low supply voltage and low power consumption. Higher gain and better linearity can be achieved by increasing the bias current through the Tranconductance stage. In overall ption mixer design, higher gain, higher linearity, lower noise and low power consum

are requi arameters are not easy to achieve simultaneously.

be achieved by increasing the drive current throu

y-phase filter is shown in Fig.

3.25 type of phase shifters to generate amplitude-balanced signals and then subsequently correct the phase error prior to the output combining operation. Note that it is more difficult to correct errors in amplitude domain than in

phas (from LO port) but

reserve linear input-output relationship for phase. If difference combining is red. However, these p

Higher gain and better linearity can

gh the transconductance stage, but power consumption will be increased.

Furthermore the larger current through the switching quads causes voltage headroom problems especially if resistive loads are used. The larger amount of current through the switching quads mandates the larger LO drive voltage, which is troublesome in the CMOS technology, since it is not easy to get the large enough voltage swing at high LO frequency. Fig. 3.23 shows the block diagram of a single-single sideband mixer, which consists of two-stage passive poly-phase filter, two DSB mixers, and an output combiner. In the ideal case, the SSB mixer only generates either upper (W1+W2) or lower (W1-W2) sideband component. However, both sidebands are present due to non-quadrate phase (non-zero θ1, and θ2) or amplitude imbalance (between A1 and B1, A2 and B2) introduced by the 90-degree Phase Shifters to eliminate such a design issue. A two-stage passive pol

. We may employ this

e domain, since mixers introduce amplitude nonlinearity p

performed at the SSB mixer output as shown in Fig. 3.24. It can be shown through simple trigonometric identities that the lower sideband (difference frequency) is rejected provided that the two. Two-stage passive poly-phase filter produce balanced amplitudes (A1=B1 and A2=B2) and identical phase shifts, i.e., θ1=θ2. As a result, an absolute accuracy of 90-degree phase is not needed for each phase shifter, as long as they produce identical phase shift. After passing through the 90-degree delay circuit, the desired signals in the I and Q channels are in phase but the image signals are out

of phase. A combiner, shown in Fig. 3.24, adds the signals from the I and Q channels together to cancel the image signal. M105 and M108 are added to control the bias current to adjust the amplitude balance, and the control signal comes from the off-chip control circuit.

Fig. 3.22 Double-balanced Gilbert-type mixer topology

Fig. 3.23 Single-sideband mixer topology

Fig. 3.24 Schematic of the combiner

3.2.7

Poly-Phase Filter

A poly-phase filter offers an accurate phase shift and amplitude balance in a fairly wide band. The overall image-rejection ratio (IRR) is strongly affected by the characteristics of this block. Therefore, Careful designing is essential. In this design, using one-stage poly-phase filter results in large RC variation. However, using three-stage poly-phase filter results in small output signals. Therefore, a two-stage poly-phase filter is used in this design to achieve moderate RC variation and level of output signals. To reduce the RC variation, MIM-capacitors and poly resistors are used in this design. Moreover, the interlocking method is adopted in the layout and some dummy devices are placed on two edges of the ploy-phase filter to reduce the

RC variation further. nd after the filter to

e signals. A two-stage poly-phase filter is depicted in Fig. 3.25. The stages are inherently suitable for cascading. Along with the number of stages the image-rejection ratio offered by the filter increases but at the same time the signal attenuation and the physical die size are increased, too. If the center frequencies at each stage are equal, the IRR value is high but only at a limited band. If the center frequencies are selected properly for each stage, larger bandwidth with sufficient IRR values is achieved. In our case an 10.032GHz bandwidth is required. For us, two stages were required for achieving enough image rejection. The RC values of the two-stage poly-phase filter is depicted in Table 3.2 The two-stage RC poly-phase filter rejects the image of the first mixer by about 35 dB. For this image rejection, the phase accuracy of the quadrature LO should almost be commensurate. The outermost s (center frequencies) are shifted further away from the center of the band for

ensuring that despit is always achieved. Also, a

proper selection of the resistance and capacitance values is required for achieving a Finally, two buffers are inserts before a

maintain th

peak

e the process spread a high IRR value

high immunity to process spread. Finally, to avoid any confusion, it is worth emphasizing that a poly-phase fi

(MHz)

lter does not separate the signal and image. Instead, in the other output port the signal appears in a 90-degree phase shift. This port is terminated with appropriate impedance in our designs. The turn-on resistors of MOS switches have been considered in the post-simulation, so R used in the simulation includes these resistors.

Table 3.2 RC values of the two-stage poly-phase filter

Frequency C (fF) R (Ω)

Fig. 3.25 A two-stage poly-phase filter

10032 100 158.6

OUT_Q-3.2.8

Band-Selector

A selector must provide fast switching and symmetry with respect to its three inputs. A conventional current-steering selector may suffer from undesired modulation, since the unselected signal in the disabled pair would still couple to the output through the parasitic capacitance. This circuit is shown in Fig. 3.26, where three dummy pairs, M47–M48; M49–M50 and M51–M52, are introduced to eliminate the unwanted coupling to the first order while consuming no extra power. Then the control bit can control frequency selector. When one bit is work, the other bits are disabling. It cans effective control current consumption And reduce noise couple, then the Band-Selector1 frequency control in turn 1584MHz、3168MHz、5016MHz, the Band-Selector2 frequency control in turn 528MHz、1056MHz、1584MHz.

. 3.26 Band-Selecto ematic

Fig r Sch

3.3

SIMULATION RESULTS

Fig. 3.27 Charging simulation of charge pump (a) reference clock. (b) Divider output. (c) the control voltage of VCO. (d) Iup and Idown of the charge pump.

In the Fig. 3.27, the charge pump is in charging mode. In Fig. 3.27 (a) and (b), we can find that the phase of the reference clock goes beyond the divider output and the frequency is higher than the divider output. So, the charge pump charges between the

clock falling edges of r. So, the control

voltage is getting higher.

the reference clock and output of divide

ig. 3.28 Discharging simulation of charge pump (a) reference clock. (b) Divid

F er

output. (c) the control voltage of VCO. (d) Iup and Idown of charge pump

edges of the reference clock and divider output. So, the In the Fig. 3.28, the charge pump is in discharging mode. In Fig. 3.28 (a) and (b), we can find that the phase of the reference clock goes behind the divider output and the frequency is lower than the divider output. So, the charge pump discharges between the clock falling

t current-match structure (a) The Iup and I n at Vc=0.3V (b) The Iup and Idown at

Fig. 3.29 Simulation results of the current-steering charge pump withou

dow

Vc=0.75V (c) The Iup and Idown at Vc=1.3V (d) The mismatch current v.s. Vcontrol

Fig. 3.30 Simulation results of the new current-match charge pump (a) The Iup and Idown at Vc=0.3V (b) The Iup and Idown at Vc=0.75V (c) The Iup and Idown at Vc=1.3V (d)

The mismatch current v.s. Vcontrol.

Fig. 3.31 The mismatch current simulations of charge pump with process variation, and compare the results with the charge pump without feedback loop.

The current-steering charge pump without feedback loop is simulated in Fig. 3.29 (a) to (c) shows Iup and Idown at different Vc and we can find that the Iup and Idown just match at Vc=0.75V. In Fig. 3.29 (d) shows the mismatch current at different Vc. The maxim difference between Iup and Idown is about 20% of the charge pump current.

The current-match charge pump which used in this design is simulated in Fig. 3.30 (a) to (c) shows Iup and Idown at different Vc and we can find that when the Vc varies, Iup and Idown still match to each other. In Fig. 3.29 (d) shows the mismatch current at dif

Fig. 3.31 shows the pro -match charge pump. We

can find that even if the variation up to 10%, the mismatch current is smaller than witch without feed back loop.

ferent Vc and the maxim difference between Iup and Idown is about 1.5% of the charge pump current.

cess variation impact of the current

(a)

(b)

)

(d)

Fig. 3.32 The simulation results of the band-switching VCO (a) The output waveform of the VCO (b) The phase noise simulation results by Spectre-RF (c) The tuning ranges of the sixteen bands simulation (d) Spurious tones simulation.

(c

VCO Output Frequency ( GHz )

Control Voltage ( V )

0000

The simulation results of the VCO are shown in Fig. 3.32. The differential output waveforms of VCO are shown in (a) and the peak-to-peak amplitude is 1.55V. The phase noise of VCO is simulated by Spectre-RF and is shown in (b). In (b) we can find that the phase noise at offsets frequencies 1-MHz is –111.6dBc. This performance is suitable for UWB application. The tuning

As mentioned in 3.2.2.2, the 4-bits band-switching VCO uses mimcap as the bank and split the tuning range into 16 bands as show in (c). When the control word of bank is 0000, the bank has the maximum capacitance. So, the VCO has the minimum frequency band. On the contrary, when the control word is 1111, the VCO changes the frequency band to the maximum frequency band. Beside, when the control word

VCO changes to the middle band. In (e) is the simulation of spurious tones about 51dBc@528MHz

range of the 4-bits VCO is shown in (c).

changes to 0111 or 1000, the frequency band of

– offset.

Fig. 3.33 The close loop simulation of the PLL (a) The control voltage of VCO (b) The reference clock and the output waveform of counter

The close loop simulation of the frequency is shown in Fig. 3.33. The Vc which controls VCO is shown in (a) and we can find that it is locked within 1 usec. Fig 29 (b) shows the reference clock and the output waveform of counter. We can find that the edges of reference clock and output of counter match to each other. This means that the frequency synthesizer is locked.

(a)

(b)

(c)

Fig. 3.34 Simulation results of the Divider (a) Divide-by-2 Stage for 5016MHz (b) Divide-by-3 Stage for 3168MHz (c) Divide-by-2 Stage for 1584MHz

(a)

(b)

Fig. 3.35 Simulation results of the Band-Selector (a) Output Amplitude of the Band-Selector1 (b) Output Amplitude of the Band-Selector2

The simulation results of Divider and Band-Selector are shown in Fig. 3.34 and Fig.

3.35. In Fig. 3.34 the divider is dividing 2 and 3. Then, the minimum peak-to-peak amplitude is 760mV for a 5016MHz sinusoidal output. In the Fig. 3.35, the Band-Selector1 frequency control in turn 1584MHz、3168MHz、5016MHz, the Band-Selector2 frequency control in turn 528MHz、1056MHz、1584MHz. Then, The minimum peak-to-peak amplitude is 725mV for a 5016MHz sinusoidal output.

8448 8976 9504

3696 4224 4752 5280 5808 6336 6864 7392 7920 8448 -2.0

(c)

Fig. 3.36 The simulation results of the Mixer (a) Mixer1,3 Conversion Gain (b) Mixer2 Conversion Gain (c) Output waveforms for a 3.432GHz sinusoidal output.

The simulation results of mixer are shown in Fig. 3.36. As shown in (a) (b) the voltage conversion gain of the all mixers are above 0dBm for UWB application. In Fig. 3.36(c), the minimum peak-to-peak amplitude is 770mV for a 3.432GHz sinusoidal output.

(a)

(b)

(c)

Fig. 3.37 The simulation results of the spurious and switching time (a) In-band spurs response at 3.432 GHz (b) Out-of-band spurs response at 3.432 GHz (c) Switching time between adjacent bands.

The simulation results of the spurious and switching time are shown in Fig. 3.37.

As shown in (a) and (b), the additional in-band spurs are generated at 6.864GHz with spurious response of –35.2 dBc, and out-of-band spurs are generated at 14.784 GHz with spurious response of –42.8 dBc respectively. In (c) the bands are switched periodically and the synthesizer output is monitored. The longest switching time is approximately equal to 911ps.

Table 3.3 The summary of the post-simulation

Post-simulation

Supply voltage 1.5 V

Frequency range 3.432~10.032 GHz

Reference clock 528 MHz

KVCO (VCO gain) 160MHz/V

Phase noise (using SpectreRF) -112 dBc/Hz @1MHz offset

Charge pump current 100uA

Loop bandwith 5500 kHz

Close loop PM 65^o

PLL lock time 500 ns

Switching time 0.911ns

In-band spur Out-of-band spur

-35.2dBc -42.8dBc

Mixer conversion gain >0dBm

Chip area 1900 X 1900 um^2

Power consuming 50.07~147.35 mW

Technology TSMC 0.18um CMOS

Chapter 4

Experiment Results

The chip, UWB frequency synthesizer for UWB applications is designed and fabricated in TSMC 0.18-μm CMOS process. In this chapter, the chip layout, test environment, and experiment results are presented. Measured performance is compared with post-simulation results and discussion is made for further study.

4.1 Layout Description

The chip is designed and fabricated by TSMC 0.18μm 1P6M CMOS technology.

The process is implemented to fulfill the applications for mixed signal/RF, such as inductor with low receptivity and good conductivity and lower capacitance to substrate. Besides, deep n-well topology is employed to surround the N-MOS device, which allows the connection of source and body terminals to avoid body effect.

Dummy gates and dummy resistors are equipped at the margin of every MOS device

Dummy gates and dummy resistors are equipped at the margin of every MOS device

在文檔中 應用於1.5伏特3~10-GHz超寬頻頻率合成器 (頁 38-0)