CHAPTER 4 EXPERIMENTAL RESULTS
4.2 Measurement Results of the Frequency Synthesizer
4.2.1 Measurement Results of the Band-switching VCO
Fig. 4.3 Testing module of frequency synthesizer
4.2.1
Measurement Results of the Band-switching VCOThe simulation and measurement of the band -switching VCO are shown in Fig. 4.4 and Fig. 4.5. The measurement result shows that the frequency range shift down about 350 MHz, but the tuning range is similar than simulation and the VCO frequency meet requirement. Initially, the 16 bands are designed to cover the unexpected process variation and the reduction in the tuning range. Therefore, some bands are indeed redundant as shown in the measurement results. The KVCO is calculated for every 0.1 V step of the control voltage and the KVCO of the tuning range is 160 MHz/V. The summary of VCO measurement and simulation results is shown in Table. 4.1.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
VCO Output Frequency ( GHz )
Control Voltage ( V )
0000
Fig. 4.4 The tuning ranges of simulation result.
4.5 The tuning ranges of measurement result.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
VCO Output Frequency ( GHz )
Control Voltage ( V )
0000
Table 4.1 VCO summaries
Post-simulation Measurement
VDD _VCO (V) 1.5 V 1.5 V
Frequency Range (GHx) 9.6~10.6 9.27~10.25
160 160
VCO Gain (MHz/V)
Phase Noise@1MHz (dBc/Hz) -111.6 -106
Current Consumption (mA) 10 11.4
.2.2
Phase Noise and Lock-Time Measurement Results ons4
In Fig. 4.6 show the performance of phase noise when the measurement conditi are VCO frequency at 10.032GHz, reference frequency is 528MHz and loop bandwidth is 5500 kHz. In chapter 3, we mention that the phase noise should benefit from wider loop bandwidth of frequency synthesizer. Indeed, the phase noise of 5500kHz loop bandwidth is lower in this measurement, and it will be improved by paralleling larger capacitance to supply node. While paralleled capacitor is increased from 0.1uF to 22.1uF then the phase noise is decreased about 10dB. Thus, we must care the supply quality to get better performance of phase noise. The measurement results show that the phase noise performance is -106dBc/Hz at 1 MHz offset. In Fig.
4.7 shows the settling time measurement results, the settling time is about 600 ns.
Thus, the settling time is a little large than simulation result.
Fig. 4.6 Phase noise measurement result, -106.48 dBc/Hz at 1MHz offset
ig. 4.7 Lock time measurement result F
4.2.3
Spurious-Tones and Switching-Time MeasurementThere are 2 types of spurs in this synthesizer. One type of spur is caused by the Results
frequency mixing with 528MHz in mixer1. Hence, the spurs in the fourth group will decide those in other groups. Fig. 4.11 shows the sideband rejection at 8976MHz.
Mixer1 provides 34dB suppression of the unwanted sidebands. The other type of spur is due to cascading mixers. Although fifth-order unwanted sidebands have been prevented by the frequency generation scheme in Fig. 4.12 higher-order spurious tones must be taken into consideration when the groups are down-converted by mixer1 and mixer2. The worst case occurs in the first group in Fig. 4.8 is –30.6dBc.
The 3rd harmonics on the RF and LO ports of mixer2 will generate spurs in the adjacent group. The frequencies of he spurious tones are given, with the center frequency of 3432MHz in the first group, the RF frequency is 5016MHz and the LO frequency is 8448MHz, which introduces spurs at 6600MHz and 11616MHz.This effect can be observed by monitoring the whole UWB spectrum and noting that the sideband rejection is over 32 dB because the 2-stage SSB mixer was used. Other spurious measurement results in Fig. 4.9 and Fig. 4.10 are –46dBc and –32.6dBc. The band switching behavior is shown in Fig. 4.13 and the frequency switching time is about 3.75ns, a value much less than the 9.5-ns guard interval denned in UWB. The switching time are influenced by three sources: ① mixer turn on time, ② Poly-phase filter switch time and ③ band-selector switch time. The best switching time is probably 3.75ns, but the worst switching time is probably 15.1ns. The reason of the difference of the switching time is that the function generators used to switch bands are asynchronous, so in the different switching situation, the switching times are also different.
Fig. 4.8 Measured SSB mixer2’s spurs in the first group (<-30.6dBc)
Fig. 4.9 Measured Divider’s spurs in the second group (<-47dBc)
Fig. 4.10 Measured SSB mixer2’s spurs in the third group (<-32dBc)
1 Measured SSB mixer1’s spurs in the fourth group (<-34dBc) Fig. 4.1
Fig. 4.12 Measured VCO’s spurs in the fifth group (<-45dBc)
Fig. 4.13 Band-switching behavior (From group 3 to group 1)
3.75ns
4.3 Summary of Measurement Results
Table. 4.2 and Table. 4.3 summarize the chip performance of frequency synthesizer. And the tables summarize all measurement results compared with the post-simulation outcome and other architecture.
Table 4.2 Summary of the performance of the frequency synthesizer
Post-simulation Measurement
VCO 1.5 1.5
MIXER 1.5 1.5
VDD (V)
DIVIDER 1.5 1.5
Channel spacing (MHz) 528 528
Lock time (ns) 500 600
Switching time (ns) 0.911 3.75
VCO gain (MHz/V) 160 160
Frequency band (GHz) 3.1 ~10.6 3.1~10.6
Tuning range (GHz) 9.6~10.6 9.27~10.25
Loop bandwidth (kHz) 5500 5500
Phase noise@1MHz (dBc/Hz)
-111.6 -106
In-Band spur (dBc) -35.2 -30.6
Out-of-band spur (dBc) -42.8 -40
Total power(mW) 50.07~147.35 55.1~161.62
Table 4.3 Performance comparison with other UWB frequency synthesizer
Chapter 5 Conclusion and Future Work
5.1 Conclusions
A 1.5-V frequency synthesizer with integrated PLL, mixer, band-selector, and poly phase filter for UWB applications has been designed, fabricated and tested in a 0.18-µm CMOS technology. The architecture of the frequency synthesizer is simple and suitable for low power and high data-rate UWB applications. Though seven inductors are used in this design and the frequency synthesizer occupies an area of 1900µm×1900µm, this is mainly dominated by the output pad and a large region on the chip is filled with dummy metal, poly and oxide required to raise the yield rate;
subsequently, base-band circuits can be further combined and drawn in place of the region of dummy layers.
The frequency synthesizer is tested under 1.5-V supply, except the supply voltage of VCO frequency being adjusted lower due to the oscillating frequency drift, The measurement result shows that the frequency range shift down about 350 MHz, but the tuning range is similar than simulation and the VCO frequency meet requirement. This work is measured and has the following performances. The in-band spurious signals of Group #1~ Group #5 are measured after adjust the bias voltages.
The worst case occurs in the first group, the measurement result about -30.6dB. Then out-band spurious measurement result about -40dB.The phase noise is -106dBc/Hz
@1MHz offset, locking time is 600ns and switching time is 3.75ns(From Group 5 to Group 1). The total power consumption is 55.1~161.62mW. The power consumption mostly increases in mixer to compensate the loss of the parasitic resisters and caps.
5.2 Future work
The proposed frequency synthesizer for UWB applications could be fabricated again with the cut MIM-caps in VCO by adjusting the center frequency. This would help provide the required carriers for entire UWB bands. Furthermore, for more thorough and complete frequency synthesizer design, the MUX output test buffer can be included, to avoid signal become smaller and current consumption more large. The large current consumed also appears in other functional block of the UWB frequency synthesizer, the summary of current consumed as shown in Table. 4.2 For lower battery operation, this frequency synthesizer must reduce its current consumed. It also appears the poor performance of spurious tone, which is –30.6 dBc@ 3432MHz. The reasonable value is smaller.
Finally, a full understanding of UWB system and a more careful consideration are essential to design and implement a frequency synthesizer for UWB applications.
There is still large improvement available in this design.
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簡歷
郭豐維於一九七五年十月二十三日出生於高雄市，性別男。西元一九九八年畢 業於國立雲林科技大學，獲得工學士學位。西元 2007 年畢業於國立交通大學電 機學院，獲得電機學院碩士。
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