Future Works

The proposed frequency synthesizer for UWB applications could be fabricated again with the cut MIM-caps in VCO by adjusting the center frequency. This would help provide the required carriers for entire UWB bands. Furthermore, for more thorough and complete frequency synthesizer design, the MUX output test buffer can be included, to avoid signal become smaller and current consumption more large. The large current consumed also appears in other functional block of the UWB frequency synthesizer, the summary of current consumed as shown in Table. 4.2 For lower battery operation, this frequency synthesizer must reduce its current consumed. It also appears the poor performance of spurious tone, which is –30.6 dBc@ 3432MHz. The reasonable value is smaller.

Finally, a full understanding of UWB system and a more careful consideration are essential to design and implement a frequency synthesizer for UWB applications.

There is still large improvement available in this design.

References

[1] Derek K.Shaeffer and Thomas H. Lee, The Design and Implementation of Low-Power CMOS Radio Receiver, Kluwer Academic Publishers.

[2] Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi, and Seong Su Park, “A 6.3–9-GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications,” IEEE Journal of Solid-State Circuits, Vol. 40 No.8, pp.1671-1679, August 2005

[3] J. Lee and D.-W. Chiu, “A 7-Band 3–8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 m CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 204–205

[4] B. Razavi et al., “A 0.13 m CMOS UWB transceiver,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 216–217.

[5] Donhee Ham, Ali Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs, ” IEEE Journal of Solid-State Circuits, Vol. 36 No.6, pp.896-909, June 2001.

[6] Behzad Razavi, RF Microelectronics. Prentice Hall.

[7] Joy Laskar, Babak Matinpour, Sudipto Chakraborty, Modern Receiver Front-ends: Systems, Circuits, and integration, Wiley.

[8] Ian Oppermann, Matti Hamalainen and Kari Iinati, UWB theory and Applications, Wiley.

[9] Physical Layer Submission to 802.15 Task Group 3a:Multi-band Orthogonal Frequency Division Multiplexing, IEEE P802.15-03/268r2.Per

[10] S. Roy, J. R. Foerster, V. S. Somayazulu, and D. G. Leeper, ”Ultraw- ideband radio design: The promise of high-speed, short-range wireless connectivity,”

Proc. IEEE, vol. 92, no. 2, pp. 295-311, Feb. 2004.

[11] Pengbei Zhang and Mohammed Ismail, ”A New RF Front-End and Frequency Synthesizer Architecture for 3.1-10.6 GHz MB-OFDM UWB Receivers,” IEEE.

Circuits and System., pp. 1119-1122, Aug. 2005.

[12] Ramesh Harjani, Jackson Harvey and Robert sainati, “ANALOG/RF

PHYSICAL LAYER ISSUES FOR UWB SYSTEMS,” VLSID 2004.

[13] B. Razavi, F.-R. Yang, K.-Yu. Li, R.-H. Yan, H.-C. Kang, C.-C. Hsu and C.-C.

Lee, "A UWB CMOS Transceiver," IEEE J.Solid-State Circuits, vol. 40, no.12,pp.2555-2562.

[14] Bo Shi and Michael, Yan Wah Chia “A 3.1-10.6 GHz RF Front-End for MultiBand UWB Wireless Receiver,” in RFICS, pp. 343-346, 2005.

[15] Yen-Horng Chen, Chih-Wei Wang, Ching-Feng Lee, Tzu-Yi Yang, Choh-Fan Liao, Gin-Kou Ma, Shen-Iuan Liu, “A 0.18 µm CMOS Receiver for 3.1 to 10.6 GHz MB-OFDM UWB Communication systems,” in RFICS, pp. 343-346, 2006.

[16] Andrea Bevilacqua and Ali M. Nijnejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6 GHz Wireless Receivers,” IEEE J.Solid-State Circuits, vol. 39, no.12, pp.2259-2268, Dec. 2004.

[17] Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5-GHz UWB System,” IEEE J.Solid-State Circuits, vol. 40, no.2, pp.544-547, Feb.

2005.

[18] J. Lee and J. D. Cressler, “A 3-10 GHz SiGe resistive feedback low noise amplifier for UWB applications,” in IEEE RFIC Symp., pp. 545-548, long Beach, June 2005.

[19] R. C. Liu, C. S. Lin, K. L. Deng, and H. Wang, “A 0.5-14-GHz 10.6-dB CMOS cascade distributed amplifier,” IEEE VLSI Circuit Symo., pp.139-140, 2003.

[20] W. Zhuo, X. Li, S. Shekhar, S. H. Embabi, J. Pineda de Gy vez, D. J. Allstot, and E. Sanchez-Sinencio, “A Capacitor Cross-Coupled Common-Gate Low-Noise Amplifier,” IEEE Trans. Circuits Syst., vol. 52, no. 12, pp. 875-879.

[21] Xiaoyong Li, Sudip Shekhar, and David J. Allstot, “Gm-Boosted Common-Gate LNA and Differential Colpitts VCO/QVCO in 0.18-µm CMOS,” IEEE J.Solid-State Circuits, vol. 40, no.12, pp.2609-2619, Dec. 2005.

[22] Chung-Yu Wu and Hong-Shin Kao, “A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator

Circuits and Systems, vol. 49, Issue 2., pp.123-134, Feb. 2002.

[23] Chien-Chih Ho, Chin-Wei Kuo, and Yi-Jen Chan, and Wan-Yih Lien, and J.-C Guo, “0.13-µm RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts,” IEEE Transactions on Circuits and Systems, vol. 51, No. 12, pp.2181-2185, Dec. 2004.

[24] Neric H. W. Fong, Jean-Oliver Plouchart, Noah Zamder, Duixian Liu, Lawrence F. Wagner, Calvin Plett, and N. Garry Tarr, “A 1-V 3.8-5.7-GHz Wide-Band VCO With Differentially Tuned Accumulation MOS Varactors for Common-Mode Noise Rejection in CMOS SOI Technology,” IEEE Transactions on Microwave and Techniques, vol. 51, No. 8, pp.1952-1959, Aug.

2003.

[25] N. Fong, J.-O. Plouchart, N. Zamdmer, D. Liu, L. Wanger, C. Plett, and G. Tarr,

“A Low-Voltage Multi-GHz VCO with 58% Tuning Range in SOI CMOS,” in IEEE Custom Intergrated Circuits Conf., pp. 423-426,2002.

[26] Ullas Singh, Michael M. Green, “High-Frequency CML Clock Dividers in 0.13-µm CMOS Operating Up to 38 GHz,” IEEE J.Solid-State Circuits, vol. 40, no.8, pp. 1658-1661, Aug. 2005.

[27] B.Razavi et al., “Design of high-speed, low-power frequency divider in 0.25 µm CMOS,” IEEE J.Solid-State Circuits, vol. 30, pp. 101-108, Feb. 1995.

[28] Ullas Singh, and Michael Green, “DYNAMICS AND HIGH-FREQUENCY CMOS DIVIDERS,” ISCAS 2002, vol. 5, pp. V-421-V-424, May 2002.

[29] L. A. MacEachern and T. Manku, “A charge-injection method for Gilbert cell biasing,” in Proc. IEEE Canadian Conf. Electric Computer Eng., vol. 1, May 1998, pp. 365-368.

[30] Hooman Darabi and Asad A. Abidi, “Noise in RF-CMOS Mixers: A Simple Physical Model,” IEEE Transactions on Solid-State Circuits, vol. 35, No. 1, pp.15-25, Jan. 2000.

[31] J. Bergervoet, et al., “An Interference Robust Receuve Chain for UWB Radio in SiGe BiCMOS,” ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2005.

[32] UWB Forum: http://www.uwbforum.org

[33] E. Kivisaai,“UWB communication–a standard war,＂2004.

[34] A. Batra, J. Balakrishnan, and A. Dabak, “Multi-band OFDM: a new approach for uwb,” ISCAS 2004, pp. 365—368, 2004.

簡歷

郭豐維於一九七五年十月二十三日出生於高雄市，性別男。西元一九九八年畢 業於國立雲林科技大學，獲得工學士學位。西元 2007 年畢業於國立交通大學電 機學院，獲得電機學院碩士。

主修科目：

類比積體電路(一) 吳介琮教授

數位積體電路 張錫嘉教授

射頻辨識 RFID 技術與系統整合應用 廖德誠教授

射頻積體電路 郭建男教授

積體電路之靜電防護設計特論 柯明道教授

有線傳輸通信積體電路設計 蔡嘉明教授

鎖相迴路與頻率合成 高曜煌教授

個人通訊 林一平教授