Summary of Measurement Results

Table. 4.2 and Table. 4.3 summarize the chip performance of frequency synthesizer. And the tables summarize all measurement results compared with the post-simulation outcome and other architecture.

Table 4.2 Summary of the performance of the frequency synthesizer

Post-simulation Measurement

VCO 1.5 1.5

MIXER 1.5 1.5

VDD (V)

DIVIDER 1.5 1.5

Channel spacing (MHz) 528 528

Lock time (ns) 500 600

Switching time (ns) 0.911 3.75

VCO gain (MHz/V) 160 160

Frequency band (GHz) 3.1 ~10.6 3.1~10.6

Tuning range (GHz) 9.6~10.6 9.27~10.25

Loop bandwidth (kHz) 5500 5500

Phase noise@1MHz (dBc/Hz)

-111.6 -106

In-Band spur (dBc) -35.2 -30.6

Out-of-band spur (dBc) -42.8 -40

Total power(mW) 50.07~147.35 55.1~161.62

Table 4.3 Performance comparison with other UWB frequency synthesizer

Chapter 5 Conclusion and Future Work

5.1 Conclusions

A 1.5-V frequency synthesizer with integrated PLL, mixer, band-selector, and poly phase filter for UWB applications has been designed, fabricated and tested in a 0.18-µm CMOS technology. The architecture of the frequency synthesizer is simple and suitable for low power and high data-rate UWB applications. Though seven inductors are used in this design and the frequency synthesizer occupies an area of 1900µm×1900µm, this is mainly dominated by the output pad and a large region on the chip is filled with dummy metal, poly and oxide required to raise the yield rate;

subsequently, base-band circuits can be further combined and drawn in place of the region of dummy layers.

The frequency synthesizer is tested under 1.5-V supply, except the supply voltage of VCO frequency being adjusted lower due to the oscillating frequency drift, The measurement result shows that the frequency range shift down about 350 MHz, but the tuning range is similar than simulation and the VCO frequency meet requirement. This work is measured and has the following performances. The in-band spurious signals of Group #1~ Group #5 are measured after adjust the bias voltages.

The worst case occurs in the first group, the measurement result about -30.6dB. Then out-band spurious measurement result about -40dB.The phase noise is -106dBc/Hz

@1MHz offset, locking time is 600ns and switching time is 3.75ns(From Group 5 to Group 1). The total power consumption is 55.1~161.62mW. The power consumption mostly increases in mixer to compensate the loss of the parasitic resisters and caps.

5.2 Future work

The proposed frequency synthesizer for UWB applications could be fabricated again with the cut MIM-caps in VCO by adjusting the center frequency. This would help provide the required carriers for entire UWB bands. Furthermore, for more thorough and complete frequency synthesizer design, the MUX output test buffer can be included, to avoid signal become smaller and current consumption more large. The large current consumed also appears in other functional block of the UWB frequency synthesizer, the summary of current consumed as shown in Table. 4.2 For lower battery operation, this frequency synthesizer must reduce its current consumed. It also appears the poor performance of spurious tone, which is –30.6 dBc@ 3432MHz. The reasonable value is smaller.

Finally, a full understanding of UWB system and a more careful consideration are essential to design and implement a frequency synthesizer for UWB applications.

There is still large improvement available in this design.

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簡歷

郭豐維於一九七五年十月二十三日出生於高雄市，性別男。西元一九九八年畢 業於國立雲林科技大學，獲得工學士學位。西元 2007 年畢業於國立交通大學電 機學院，獲得電機學院碩士。

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