Chapter 1 Introduction
1.4 Thesis Organization
Chapter 2 presents a novel frequency tripler circuit which can be applied in 60-GHz receiver front-end. The detail design considerations are also introduced here with its simulation results. In Chapter 3, the receiver architecture and its building blocks are presented.
It includes a LNA, a down-conversion mixer and output buffers. The basic theory and simulation results of each building block are also illustrated here. Chapter 4 contains experimental results and discussions. Finally, conclusions and future work are presented in Chapter 5.
Chapter 2
A High-Frequency Frequency Multiplier
A novel configuration of balanced frequency tripler using standard 0.13-um CMOS technology is proposed. In this chapter, the circuit design consideration and theoretical analysis of frequency tripler are introduced together with the simulation results. The simulation results show that the circuit has great potential to apply in the high-frequency system such as 60-GHz receiver front-end.
2.1 Design of the Frequency Tripler
A frequency tripler based on FET type is very attractive for being integrated with other elements of a monolithic transceiver. In this design, by importing only 20-GHz input signal, the frequency tripler can successfully generate sufficient amplitude of the differential 60-GHz signal to be as LO signal of the mixer.
2.1.1 Operational Principle
The analysis of the frequency multiplier is usually a combination of gate bias and fundamental RF input levels for optimum generation of a desired harmonic signal [24]. To decide the bias point of the FET device, the drain current dependence model illustrated by Fudem and Niehenke is introduced here [25].
The optimal bias point is opted midway between pinch-off and the onset of forward condition which is consistent with a Class-A amplifier. When operating on this bias point, a large amplitude AC signal is required to over-drive the device both into pinch-off and forward conduction every cycle. The resulting drain current waveform is then severally clipped at both
ends. This clipped waveform successfully results the harmonics. If the ac signal becomes larger, the output waveform can be approximately considered as square-wave results. The Fourier transformation associated with a perfect square-wave is given by:
n even order term which we do not desired can be eliminated. For a square wave, if n=3 for the tripler design, the output amplitude of I3 can be generated approximately 0.212Ipeak. This mode of operation obtains superior third-order conversion than biasing the device near the pinch-off which is more commonly used.
Besides biasing between pinch-off and the onset of forward condition, there is still another bias point that can obtain the same optimal value of I3. This solution can be obtained by generating rectangular output waveform with a duty cycle of 1/6 rather than square one.
Unlike the square-wave considered previously, although rectangular-wave does obtain the same conversion of the odd order harmonic, it also contains significant even order harmonics, especially second order harmonic which we do not desire.
The most significant benefit of choosing a 1/6 duty cycle in bias point design is the DC power reduction. In this mode, the device always operating in the cut-off region and rarely consumes DC power until AC signal is supplied. Furthermore, the fundamental content under this operation is less than that of square-wave, thus the fundamental rejection can be improved.
Nevertheless, there are several serious drawbacks in this approach: poor even order harmonic rejection, high AC drive level of the fundamental input, and the breakdown issue due to large drive power.
2.1.2 Design Considerations
There are several limitations that need to be considered when implementing the frequency tripler which applies in 60-GHz receiver front-end. Especially, the design is implemented by using 0.13-um CMOS technology with 1.2-V supply voltage.
From the analysis that mentioned above, two optimal bias conditions are proposed. One is biasing in the middle between cut-off and forward conduction region, which generate square wave in the output. The other operation point is biasing at well below the cut-off region and generate 1/6 duty cycle rectangular wave with large AC signal. If we want to generate a 60-GHz LO signal, we must implement a 20-GHz frequency synthesizer or VCO to provide the sufficient input AC signal level for the tripler circuit. However, in 0.13-um CMOS technology, it is hard to generate such a large output swing signal due to low supply voltage. Beside, the FET device model of the CMOS process is not quite accurate when square-wave. Therefore, the undesired even order harmonics are no longer be zero, especially the second order harmonic is the extreme one. In the design of the frequency multiplier, harmonic rejection is also an import demand. The most popular method to filter out these undesired outputs is using the inductor peaking approach. By choosing appropriate value of LC tank, the band pass filter characteristic can be obtained. Another popular way is using the transmission lines with length of particular wavelength ratio to filter out the undesired signal.
However, this method requires large chip area to implement the transmission lines.
2.1.3 Circuit Realization
The circuit scheme of the proposed two-stage CMOS frequency tripler is shown in Figure 2.1. It consists of a tripler core circuit and an output buffer stage with a fully differential configuration. The tripler function is made by MOS M1 and M2. As the fundamental signal (20 GHz) is applied to the gate terminals of M1 and M2, the third order harmonic signal (60 GHz) can be generated due to the output waveform distortion that mentioned in previous subsection. The inductors L1 and L2 are used to resonant with the parasitic capacitance at the third harmonic frequency of the input signal and the desired output signal can be extracted. Moreover, due to the band pass characteristic of the LC tank, the undesired harmonic signals will be filtered to some extent.
Figure 2.1 The circuit scheme of the proposed CMOS frequency tripler
The M3 and M4 perform as CS amplifiers and the load inductors L3 and L4 are also resonated at the third harmonic frequency. By using additional gain stage, not only can the desired signal be enhanced further but also the other undesired harmonics can be suppressed.
A resistance R2 is used to select the dc operation point of the mixer LO-port and can save a dc bias pin. In additional, to provide the stable dc bias, a bypass capacitance C5 is also added.
Because the even harmonic signals at the output nodes are common-mode characteristic, appropriate value of R5 can be designed to eliminate the undesired even order harmonic signals. The simulation result of the 2nd and 4th harmonic rejection improvement due to R5 is shown in Figure 2.2
To further improve the performances, the source inductor LS is applied to enhance the even order harmonics at the source terminal of M1,2 to mix with the input fundamental signal.
Thus, the third harmonic signals at the output nodes can be enhanced, as shown in Figure 2.3.
When even-order harmonics are involved, the LS can be seen as source degeneration inductor and a cause of even order signal gain reduction, as illustrated in Figure 2.4. Further improvement of the harmonic rejection ratio (HRR) is expected which shows in Figure 2.5.
Although larger inductance value gets better performance, but it is not easy to implement such a large inductor and it requires large area. So we choose the appropriate value of source inductor here. The detail device parameters of proposed frequency tripler are list in Table 2.1.
Table 2.1 Detail parameters of proposed frequency tripler
M1,2 18 um / 0.13 um R1,2 5 kohm
Figure 2.2 Simulation results of even-order HRR due to R5
Figure 2.3 The simulation results of odd-order harmonic output powers versus Ls
Figure 2.4 The simulation results of even-order harmonic output powers versus Ls
Figure 2.5 The simulation results of even-order HRR due to Ls
2.1.4 Simulation Results of Frequency Tripler
The performance of the proposed frequency tripler is simulated under the input power of 4 dBm. To count the loading effect of the mixer, the circuit is integrated with the mixer and obtains the inter-stage performances. Figure 2.6 shows the simulated relative output power of the frequency tripler between 56~65 GHz. In Figure 2.7, the HRR over the 57~64 GHz are calculated. It shows that the HRR can achieve better than 24 dB in each case. Since the output impedance is not 50-ohm, the simulation results taken as affirming the relative harmonic amplitude. The accurate output swing waveform at 60-GHz can be obtain by using transient analysis, as shown in Figure 2.8 to Figure 2.10. As can be shown, the output swing of the frequency tripler is between 125 mV and 270 mV. At last, the third-harmonic output power versus input power of the fundamental signal is illustrated in Figure 2.11. Obviously, the third-harmonic output power achieves saturate when input power is larger than 4 dB. Hence, we choose the 20-GHz input signal as 4 dBm here which is available to be generated by using 20-GHz PLL or VCO under 0.13-um CMOS process.
To obtain the phase noise contribution due to the proposed circuit, an additional 20-GHz VCO has been designed and connected to the proposed frequency tripler. Figure 2.12 shows the simulated phase noise performance of the 20-GHz VCO and the output signal of the frequency tripler circuit when VCO is connected as the fundamental input signal. As can be seen, the phase noise increases 11.8 dBc/Hz at 1 MHz offset before and after the frequency tripler circuit. Ideally, tripling the signal will cause the 9.54 dBc/Hz phase noise enhancement due to frequency transition. Hence, the phase noise contribution due to the proposed circuit itself is about 11.8 – 9.54 = 2.26 dBc/Hz.
Figure 2.6 The simulation results of the relative output power
Figure 2.7 The harmonic rejection ratio to different harmonic
Figure 2.8 The simulation results of the output waveform at 57 GHz
Figure 2.9 The simulation results of the output waveform at 60 GHz
Figure 2.10 The simulation results of the output waveform at 64 GHz
Figure 2.11 The output power versus fundament frequency input power at 20-GHz input
Figure 2.12 The phase noise contribution due to the frequency tripler
2.2 Comparison with Previous Works
In the following, the simulation results are compared with the previous works. The main results of the frequency multiplier are including input power level, output swing, HRR and power consumption. So far, from the author’s knowledge, there is still not any frequency tripler circuit implemented using CMOS technology. We can only compare with the published works which are fabricated using pHEMT or SiGe technology. The simulation results summary of the proposed CMOS frequency tripler and the comparison with previous works are shown in Table 2.2 and Table 2.3, respectively.
As can be see, although we use the CMOS technology, the proposed frequency tripler performs the high output swing and the excellent harmonic rejection ability. A larger HRR can diminish the harmonic effects that influence the mixer performance. Since the 20-GHz VCO is available to reach the 4-dBm output power with 1.2-V power supply, this input power is quite make sense while simulating. From simulation results, the output voltage swing of the frequency tripler is larger than 125 mV and is enough to turn on and turn off the MOS device in the mixer stage. To deserve to be mentioned, the power consumption is much smaller than others and has great potential to implement the low power front-end circuits.
Table 2.2 Post simulation summary of the proposed frequency tripler
Technology 0.13-um CMOS 1P8M
Table 2.3 Comparison with published frequency multiplier
This work [9] [11] [26]
Technology (um) 0.13 CMOS 0.15 pHEMT 0.15 pHEMT 0.25 pHEMT*
Sub-harmonic Number 3 3 3 3
Center Frequency (GHz) 60 36 76.5 76.5
Input Power (dBm) 4 9 8.5 17
Output Power (dBm) **270 mV -0.4 4.2 0
Conversion Loss (dB) 4.8 9.4 4.3 17
HRR 1st (dB) 31 22 16 24
HRR 2nd (dB) 31 22.1 32 19
HRR 4th (dB) 47 N/A 13 N/A
Power Consumption (mW) 8.5 39.2 N/A 50
Supply Voltage 1.2 V 1.5 V 2.5 V 2 V
* Dual recess process
** only output swing can be obtained
Chapter 3
RF Front-End Circuits
First of all, proposed receiver architecture is introduced together with its building blocks.
In addition to the frequency tripler, the receiver requires a low noise amplifier and a down-conversion mixer. The frequency tripler is implemented by that mentioned in Chapter 2 and the other building blocks will be designed and simulated in the following subsections.
Subsequently, a complete 60 GHz direct-conversion receiver which is integrated by these building blocks is simulated and the simulation results are presented.
3.1 Receiver Architecture and Design Considerations
Receiver Architecture
Figure 3.1 shows the block diagram of the proposed receiver. The circuit consists of a LNA, down-conversion mixers, output buffers and a frequency tripler. First of all, the RF input signal is amplified by a LNA which has low noise and sufficient gain to enhance the signal to noise ratio (SNR). The down-conversion mixer following LNA provides extra gain and down convert the RF signal to IF by mixing with proper LO signals. To obtain the desired LO signal, the 20-GHz differential input signal is supplied and through a frequency tripler on chip, the signal is multiplied to 60 GHz. Because of the poor properties of active and passive device characteristics at high frequency, this approach can design the high performance frequency synthesizer at relative low frequency. In other words, by supplying LO signals using low frequency PLL can promote the circuit to have better phase noise performance and reduce the power consumption of high frequency pre-scalar. To obtain the output performance of the receiver, the output buffer is exploited here for measurement consideration.
Figure 3.1 The proposed 60-GHz direct-conversion receiver architecture
Receiver Specifications
So far, there is still not a standard specification for 60 GHz band wireless communication system. From the system requirement, we could specify the receiver issues as follows:
The FCC made the 59~64 GHz unlicensed band available for use at first and extended it to 57~64 GHz subsequently. Both of the bands are widely designed and well applied in different countries. The 3-dB bandwidth covers from 57 to 64 GHz band are a better solution to conform each specification. For the sensitivity which can be calculated from IEEE 802.16 [6], the noise figure requirement of the receiver could be obtained. We note that the sensitivity is about -65 dBm and the channel bandwidth of 2 GHz drives to a noise figure of 12 dB.
Design Consideration of Transmission Lines
Since the fT of nMOS is about 80 GHz in 0.13-um CMOS technology, the circuits would suffer from poor performances unless passive resonant devices are utilized in the design. Even though spiral inductors have better quality factors over tens of gigahertz, the large device occupied area will cause circuit integration even more difficult. In addition, the substrate eddy current at millimeter-wave will degrade the overall performance of the receiver. The receiver at the 60 GHz band usually claims for wide bandwidth in virtue of system requirement.
Although high Q inductors get up to high gain performance, the bandwidth requirement may
not be achieved at the same time. More significantly, since silicon substrate is neither a perfect conductor nor good insulator, it would cause some current flow through the substrate.
Magnetic coupling to the substrate significantly influences the inductance value at these frequencies and requires detailed knowledge of the substrate profile to develop an accuracy simulation models.
In contrast to spiral inductors, transmission lines (Tlines) substantially confine the electric/magnetic fields and hence better lend themselves to model. Coplanar lines in CMOS technology have already been characterized for frequency up to 50 GHz [5]. However, this structure still occupies large area and is not easy to integration a system. In this work, incorporates microstrip structures as they interact negligibly with the substrate and can be modeled more accurately. Meander configuration is applied to the circuit in order to mitigate the integration perplexity and exorbitant area usage, shown in Figure 3.2. The signal line is implemented by metal 8 while metal 1 under the signal line is used for being as ground plane.
The ground plane can fully confine the electric and magnetic fields and eliminate the substrate induced losses. Comparing to coplanar architecture, this configuration saves the Tlines area even more and could alleviate routing difficulties when integrate the circuits.
By using the electromagnetic field simulator HFSS, the s-parameter around 60GHz could be simulated to compute the equivalent inductance value LS and interior resistance RS. The meander space S may be decided by layout and magnetic coupling considerations. Although small S can reduce the geometrical length, the mutual coupling between lines will become larger. In order to make sure how spacing S effect the performance, a simple structure is established as shown in Figure 3.3. Figure 3.4 plots the line characteristics as S varies from 5 um to 35 um. As expected, LS and Q increase to some extent when S becomes larger. As this value increase to about treble the line width (about 15 um), the Quality factor reach to relatively constant and would not strongly influence the performance. This value is also acceptable for space consideration with other Tlines.
For a given meander length S=15 um, there are two parameters that may affect the inductance value (LS) and quality factor (Q): total Tline length L and the width W. Figure 3.5 plots the equivalent inductance and quality factor as W varies from 3 um to 12 um while maintaining fixed total length at 400 um. It can clearly be seen that LS decreases and Q increases as the width becomes larger. This is due to the fact that inductance is mainly determined by the outer magnetic flux generating from the conductor. Consequently, the self inductance increases when the width diminishes. Moreover, the resistance is inverse proportional to the width and quality factor can be improved as width become larger. Even though wider width can obtain better quality factor, it requires longer length to get the desired inductance and cause more parasitic capacitance. From the simulation results, the characteristic diminishing returns as W exceeds 5 um. Thus this value of W is chosen in this work. We can obtain the desired inductance by selecting the appropriate value of length.
Figure 3.2 Geometrical lengths shortening by using Meander configuration
Figure 3.3 The test pattern of meander configuration
Figure 3.4 Inductance and quality factor variation as a function of S
Figure 3.5 Inductance and quality factor variation as a function of S
3.2 Low Noise Amplifier Design
Low noise amplifier (LNA) is one of the key blocks in the RF transceiver because it is the first stage in the receiver chain. Thus, its performance would have great impact on the entire system. The main functions of LNA are amplifying RF signal receiving from the antenna, proving input impedance matching and contributing noise as few as possible.
Additionally, to apply to 57 to 64 GHz wideband wireless communication, LNA faces some news challenges: the performances require broadband gain, wideband input matching and minimized noise figure must be satisfied simultaneously under acceptable linearity, power consumption and cost.
So far, most of the reported millimeter wave integrated circuit (MMIC) LNAs cover this band are implemented by using HEMT or SiGe process to achieve high ft, high gain and low noise performance [1]-[3]. Since CMOS technology has the function of low cost and high integration, several CMOS LNAs above 50 GHz were also reported [4]-[5]. So far, both of them use three-stage cascode amplifiers. However, the cascode structure requires higher supply voltage and consumes much more power. Moreover, since the input common-source device in the first cascode stage cannot provide enough gain, the noise from common-gate
So far, most of the reported millimeter wave integrated circuit (MMIC) LNAs cover this band are implemented by using HEMT or SiGe process to achieve high ft, high gain and low noise performance [1]-[3]. Since CMOS technology has the function of low cost and high integration, several CMOS LNAs above 50 GHz were also reported [4]-[5]. So far, both of them use three-stage cascode amplifiers. However, the cascode structure requires higher supply voltage and consumes much more power. Moreover, since the input common-source device in the first cascode stage cannot provide enough gain, the noise from common-gate