Receiver Architecture and Design Considerations

Receiver Architecture

Figure 3.1 shows the block diagram of the proposed receiver. The circuit consists of a LNA, down-conversion mixers, output buffers and a frequency tripler. First of all, the RF input signal is amplified by a LNA which has low noise and sufficient gain to enhance the signal to noise ratio (SNR). The down-conversion mixer following LNA provides extra gain and down convert the RF signal to IF by mixing with proper LO signals. To obtain the desired LO signal, the 20-GHz differential input signal is supplied and through a frequency tripler on chip, the signal is multiplied to 60 GHz. Because of the poor properties of active and passive device characteristics at high frequency, this approach can design the high performance frequency synthesizer at relative low frequency. In other words, by supplying LO signals using low frequency PLL can promote the circuit to have better phase noise performance and reduce the power consumption of high frequency pre-scalar. To obtain the output performance of the receiver, the output buffer is exploited here for measurement consideration.

Figure 3.1 The proposed 60-GHz direct-conversion receiver architecture

Receiver Specifications

So far, there is still not a standard specification for 60 GHz band wireless communication system. From the system requirement, we could specify the receiver issues as follows:

The FCC made the 59~64 GHz unlicensed band available for use at first and extended it to 57~64 GHz subsequently. Both of the bands are widely designed and well applied in different countries. The 3-dB bandwidth covers from 57 to 64 GHz band are a better solution to conform each specification. For the sensitivity which can be calculated from IEEE 802.16 [6], the noise figure requirement of the receiver could be obtained. We note that the sensitivity is about -65 dBm and the channel bandwidth of 2 GHz drives to a noise figure of 12 dB.

Design Consideration of Transmission Lines

Since the fT of nMOS is about 80 GHz in 0.13-um CMOS technology, the circuits would suffer from poor performances unless passive resonant devices are utilized in the design. Even though spiral inductors have better quality factors over tens of gigahertz, the large device occupied area will cause circuit integration even more difficult. In addition, the substrate eddy current at millimeter-wave will degrade the overall performance of the receiver. The receiver at the 60 GHz band usually claims for wide bandwidth in virtue of system requirement.

Although high Q inductors get up to high gain performance, the bandwidth requirement may

not be achieved at the same time. More significantly, since silicon substrate is neither a perfect conductor nor good insulator, it would cause some current flow through the substrate.

Magnetic coupling to the substrate significantly influences the inductance value at these frequencies and requires detailed knowledge of the substrate profile to develop an accuracy simulation models.

In contrast to spiral inductors, transmission lines (Tlines) substantially confine the electric/magnetic fields and hence better lend themselves to model. Coplanar lines in CMOS technology have already been characterized for frequency up to 50 GHz [5]. However, this structure still occupies large area and is not easy to integration a system. In this work, incorporates microstrip structures as they interact negligibly with the substrate and can be modeled more accurately. Meander configuration is applied to the circuit in order to mitigate the integration perplexity and exorbitant area usage, shown in Figure 3.2. The signal line is implemented by metal 8 while metal 1 under the signal line is used for being as ground plane.

The ground plane can fully confine the electric and magnetic fields and eliminate the substrate induced losses. Comparing to coplanar architecture, this configuration saves the Tlines area even more and could alleviate routing difficulties when integrate the circuits.

By using the electromagnetic field simulator HFSS, the s-parameter around 60GHz could be simulated to compute the equivalent inductance value L_S and interior resistance R_S. The meander space S may be decided by layout and magnetic coupling considerations. Although small S can reduce the geometrical length, the mutual coupling between lines will become larger. In order to make sure how spacing S effect the performance, a simple structure is established as shown in Figure 3.3. Figure 3.4 plots the line characteristics as S varies from 5 um to 35 um. As expected, LS and Q increase to some extent when S becomes larger. As this value increase to about treble the line width (about 15 um), the Quality factor reach to relatively constant and would not strongly influence the performance. This value is also acceptable for space consideration with other Tlines.

For a given meander length S=15 um, there are two parameters that may affect the inductance value (L_S) and quality factor (Q): total Tline length L and the width W. Figure 3.5 plots the equivalent inductance and quality factor as W varies from 3 um to 12 um while maintaining fixed total length at 400 um. It can clearly be seen that L_S decreases and Q increases as the width becomes larger. This is due to the fact that inductance is mainly determined by the outer magnetic flux generating from the conductor. Consequently, the self inductance increases when the width diminishes. Moreover, the resistance is inverse proportional to the width and quality factor can be improved as width become larger. Even though wider width can obtain better quality factor, it requires longer length to get the desired inductance and cause more parasitic capacitance. From the simulation results, the characteristic diminishing returns as W exceeds 5 um. Thus this value of W is chosen in this work. We can obtain the desired inductance by selecting the appropriate value of length.

Figure 3.2 Geometrical lengths shortening by using Meander configuration

Figure 3.3 The test pattern of meander configuration

Figure 3.4 Inductance and quality factor variation as a function of S

Figure 3.5 Inductance and quality factor variation as a function of S