Chapter 5 Conclusions and Future Work
5.2 Future work
The proposed direct-conversion receiver for 60-GHz ISM applications could be fabricated again with the modification of schematic error and taken the interconnection effects into account. To realize the complete homodyne receiver circuits, the I/O mixer and I/Q VCO can be implemented together with the LNA and frequency tripler circuits. Finally, the 20-GHz frequency synthesizer may also be included to provide a stable local frequency and form the more complete system.
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Appendix
Re-designing the receiver circuit
Besides compensating the layout error and take the parasitic capacitance of the interconnection lines into account, we also modified the circuit to improve the performances of the receiver.
At first, in order to reduce the DC bias pins, the scheme of the output buffer is modified to the open drain structure and the supply voltage can be provided off-chip. Moreover, we also make the supply voltage of the LNA, mixer and frequency tripler together which provide the same voltage level in the circuit. Hence, the DC pads can be reduced from 6-pin to 3-pin and can scale down the entire chip area greatly.
Second, the conversion gain of the mixer is designed as large as possible to improve the gain performance. Since the larger gain may limit the linearity performance, but from the experiment, the measurement gain will be larger than expected and we can pre-design the larger gain to compensate this mismatch.
In previous work, the gate bias of the frequency tripler core circuit and frequency tripler output buffer are co-designed to be 0.65 V, but we cannot just change the gate bias of the core circuit to observe the maximum frequency transition. Hence, in this case, the gate bias of the frequency tripler core circuit is also implemented off-chip and we can change the bias point individually to get the best receiver performance.
Moreover, ground planes of all the transmission lines are implemented by using only M1 as ground plane improve the quality factors. Comparing to use the M1,M2 or M1,M2,M3 as the ground planes, the circuit can get the better noise performance and larger gain. The layout view of the re-designed receiver is shown in (a) and the re-designed receiver performances are shown in the (b) to (d). The total power consumption of the proposed receiver circuit is 14.2 mW. Finally, the comparison of the previous works are illustrated in Table a.
(a) The layout view of the re-designed receiver
(b) Simulated conversion gain and noise figure of the re-designed receiver
(c) Simulated P1dB of the re-designed receiver
(d) Simulated R11 of the re-designed receiver
Table a Performance comparison with other 60-GHz receiver
Architecture Homodyne Homodyne Homodyne Homodyne Heterodyne Heterodyne Frequency (GHz) 50.5 ~ 58.5 56.3 ~65.5 55.5 ~65 57.5~64 49.5~ 57~63
IF Amplifier No No No Yes Yes Yes
Technology 0.13 um
† Including tripler =receiver core + tripler (20 GHz VCO can be implemented by 8mW)
† † Modified simulation result
*Including IF amplifier ** Including 40-GHz VCO and divider ***Including 29-GHz VCO and doubler
By re-designing the circuit, the receiver can achieve the noise figure of 7.6 dB, a power gain of 29.2 dB and P1dB of -25.8 dBm. It only consumes 14.2-mW power and the total chip area can be reduced to 0.63 mm2. This is suitable for low-power and low noise 60-GHz system applications.
簡歷
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