Simulation Results of Receiver Front-end

The entire receiver consists of the foregoing circuit blocks: LNA, down-conversion mixer, frequency tripler and output buffers. Moreover, this design is aimed at on-wafer measurement; the bonding wire effects is out of concern and parasitic capacitance resulting form input GSG pad (60*60 um² with pitch of 100 um) is taken into concern that is simulated to be around 20 fF within the operating frequency; the input and output impedance is matched to 50 ohm for measurement consideration. To avoid the voltage signal division caused by blocking capacitance and for supply pins consideration, the gate bias of the differential pair in mixer is realized by dc current following through the preceding stage in tripler resistance instead of re-biasing which uses dc-blocking capacitance and additional bias pin.

The simulation results are expressed as IF signal at 50 MHz and frequency between 57 GHz to 64 GHz which we are interested in. Figure 3.31 plots the simulated power gain and Figure 3.32 plots simulated noise figure of entire receiver front-end. The power gain is higher than 22.5 dB with a peak gain of 24.4 dB at 61 GHz and the noise figure varies from 7.8 dB to 8.2 dB where the minimum noise could also be achieved at 61 GHz. The linearity P_1dB is illustrated in Figure 3.33 across the unlicensed band. The linearity performance of P1dB is between -21.4 dBm to -22.8 dBm according to gain variation. The linearity of the entire

receiver is limited by mixer circuit because the LNA already provides some gain and enhances the input signal of the mixer.

The input LO power of frequency tripler would extremely influence the entire performance. As the input power level of fundamental LO signal increase, the frequency tripler could result to higher output power and lead the switching pair in mixer operates more resemble to ideal switch. Figure 3.34 and Figure 3.35 are plots of the simulated output power and noise figure versus fundamental LO input power from -10 dBm to 10 dBm at 60 GHz.

The figure shows that from -10 to 2 dBm, the conversion gain increases with increasing of input power and tends to be saturated as the power level above 4 dBm. Finally, the output transition waveform is shown in Figure 3.36, and Table 3.7 and Table 3.8 list the summary of the post-simulation results with process and temperature variations. At last, performances are comparing with recently published papers which are listed in Table 3.9.

Figure 3.31 Simulated conversion gain of the direct-conversion receiver

Figure 3.32 Simulated noise performance of the direct-conversion receiver

Figure 3.33 Simulated linearity and P1dB of the direct-conversion receiver

Figure 3.34 Simulated output power as a function of LO input power at 60GHz

Figure 3.35 Simulated noise figure as a function of LO input power at 60GHz

Figure 3.36 Differential IF output waveform

Table 3.7 Post simulation summary of the receiver front-end with corner

Post-Simulation FF TT SS

Frequency [GHz] 56~65 56.3~65.5 56.9~65.3

Rx Gain [dB] 25.6 24.4 22.9

NF [dB] 7.5 7.7 8.3

P1dB [dBm] -23.9 -22.8 -20.9

LNA Gain [dB] 12.5 12 10.1

LNA NF [dB] 4.1 4.4 5.3

LNA Power [mW] 7.2 4.8 3

Mixer Gain [dB] 10.8 12 12.6

Mixer NF [dB] 8.4 8.8 10.6

Mixer Power [mW] 1.2 0.95 0.8

Rx Power [mW] 20.6 14.4 10.3

S11 [dB] < -15 < -15 <-15

Supply Voltage [V] 1.2 1.2 1.2

Table 3.8 Post simulation summary of the receiver front-end with temperature variation

Table 3.9 Post simulation summary and compassion of the receiver front-end

Reference [4] [6] This work

Chapter 4

Experiment Results

The proposed direct-conversion receiver for 60-GHz application and a 70-GHz LNA is designed and fabricated using TSMC 0.13-um CMOS process. This chapter presenting the chip layout, test environment, and experiment results. Measured performance is compared with post-simulation results and discussion which is made for further study.

4.1 Layout Description

This receiver chip is fabricated using TSMC 0.13-um CMOS 1P8M copper process with eight metal layers, in which ultra thick metals, seventh and eighth layers, are implemented for mixed signal / RF applications. By using this technology, an inductor with high quality factor and lower parasitic capacitance can be implemented. Besides, all NMOS devices are arranged with deep n-well device which allows the connection of source and body terminals to avoid body effect. Dummy gates and dummy resistors are equipped at the margin of every MOS device to cope with process variation. The MIM capacitor in this technology provides two kinds of arrangements: with or without under ground metal shielding. The former has high immunity to substrate noise and the latter presents less parasitic capacitance. Meanwhile, the spaces between the transmission lines are more than three times that of the line-width with other transmission lines to prevent mutual inductance. Moreover, we comprise ground plane metal to avoid the substrate induced loss.

The chip is designed for on-wafer probing measurements. Hence all the pad pitches must be designed to compete with the RF and DC probes. Moreover, the pad sizes are designed as small as possible to reduce the parasitic capacitance that may degrade the performance. The LNA and receiver layouts are shown in Figure 4.1 and Figure 4.2, respectively.

In LNA layout, due to the small core circuit of the LNA, the chip area is limited by the DC pads and RF I/O pads. This cause the signal line much longer than required and the performance may a little bit degrade. To realize the more accurate inductance model of the transmission lines in simulation, the EM simulation of the each micro-strip transmission lines and interconnections between stages are simulated by using EM simulator, Ansoft HFSS.

Moreover, to stabilize the DC supply to the circuit, large amount of the bypass capacitances are also implemented by using the metal sandwich capacitance (M1M3M5M7 for ground and M₂M₄M₆M₈ for DC bias). By applying metal sandwich capacitance, we can implement the bypass capacitance large than 10 pF on chip. The resulting chip size is 0.67x0.57 mm², Inclusive of all I/O pads and dummy metal.

In receiver design, symmetric layout is important to keep balanced of differential mixer LO input and IF output signals to reduce the mismatch. Because this chip requires six power supplies to supply the LNA, mixer and frequency tripler circuits, the 6P DC probe with 150-um pitch must be applied here. This limits the chip length because large space between six pads must be required. Furthermore, since both of the LO input and IF output are the differential, the GSGSG probes is also applied here and it also requires 150-um pitch between each pads. The chip width is limited by GSGSG pads and the area is much larger than core circuit. In order to make the signal path as short as possible to reduce the parasitic capacitance and induced inductance, the RF GSG pad and LO GSGSG pad are placed inside the whole chip instead of its fringe. This makes the signal path length reduction of at least 400 um and can reduce the non-ideal interconnection effects. The entire chip area is 1.2 mm².

Besides the DC bypass capacitance, the receiver circuit also requires some bypass capacitance to provide the ac ground node to the circuit. However, this capacitance is much more critical than DC bypass capacitance because it will dominate the circuit performance.

Hence, we draw the bypass capacitance as large as possible to more close to ac ground point.

From simulation results, each of them can achieve larger than 5 pF.

Figure 4.1 The 70-GHz LNA layout view.

Figure 4.2 The 60-GHz receiver layout view.

4.2 Measurement Consideration and Setup

The proposed 70-GHz LNA and 60-GHz receiver chips have been fabricated and measured to verify the circuit performance. Some of the circuit parameters are measured at our laboratory and the others are measured at National Nano Device Laboratories (NDL) or National Chip Implement Center (CIC) due to instrument requirements. In the following, we introduce the measurement consideration and setup of the two chips respectively.

4.3.1 Measurement of 70-GHz Low Noise Amplifier

The LNA chip is bared die and measured directly on-wafer. The chip microphotograph is shown in Figure 4.3 and the measuring environments are shown in Figure 4.4 and Figure 4.5.

The S-parameters of the circuit can be measured at NDL using HP 8510XF network analyzer to obtain the I/O return losses, power gain and reverse isolation characteristics. Since the minimum input power of the network analyzer is -15 dBm and excess the simulated 1-dB compression point of the LNA, the measured power gain may be underestimated. So, the power gain is re-measured to obtain the accurate value before gain compression.

The circuit power gain is re-measured by using the signal generator of HP E8257D cascading with V-band source module to up-convert the input signal to the desired frequency.

The output signal is down-converted and observed the output spectrum by using HP 8563E spectrum analyzer. The RF I/O pads are directly probed with CASCADE ACP-50-GSG-100 probes. All of the DC supplies are implemented on chip and DC pads are probed using 150-pitch PGP DC probes. In addition, by using the attenuator, we can vary the power of input signal and observe the input 1dB compression point. To compensate the signal power loss in the input and output path in the frequency of interest must be measured firstly. After compensate the power loss caused by cables and probes, the actual power gain of the LNA can be calculated.

So far, there are two approaches to measure the noise figure and can give nearly the same noise figure results [4]. One is applying a noise source and obtaining by a noise analyzer. But a high frequency noise source and noise analyzer is required in this case. The second approach is obtaining the difference between the input and output SNRs (all in dB).

Nevertheless, this method only can apply in a high gain circuit otherwise the output SNR will be affected by instrument. Moreover, the noise contribution due to V-band source module and down-conversion mixer is another concern. Since the power gain of the LNA is not high enough, the SNR ratio method may not a good choice.

So far, we do not have enough instruments to exact measure the noise figure and the IIP3 performance. Besides the noise figure instruments, the IIP3 measurement requires two V-band source modules and two attenuators to generate the desired input power. These instruments are under setup in our laboratory and can be measured in the future. All of instrument setup block diagrams are depicted in Figure 4.6 ~ Figure 4.8.

Figure 4.3 Chip microphotograph of the LNA

Figure 4.4 Measuring environment at laboratory

Figure 4.5 Measuring environment at NDL

Figure 4.6 Instrument setup for LNA S-parameter analysis

Figure 4.7 Instrument setup for LNA spectrum analysis

Figure 4.8 Instrument setup for LNA noise analysis

4.3.2 Measurement of 60-GHz Receiver

The fabricated chip is measured on-wafer using high frequency probes. The chip microphotograph is shown in Figure 4.9 and the measuring environment is the same as previous The S-parameters of receiver can be measured at NDL using HP 8510XF network analyzer. Due to the down-conversion mechanism of the receiver chip, the input and output signals frequency are not the same and we can only obtain the input return loss here.

To get the power gain of the receiver, we can observe the output power from the spectrum analyzer. The input is also generated by signal generator cascading with V-band source module to up-convert the input signal to the desired frequency. In the receiver circuit, the down-conversion mixer is implemented on chip and the output signal can be directly observed by spectrum analyzer without off-chip down converter. The input RF signal is directly conveyed with CASCADE ACP-50-GSG-100 probe to input GSG pad. Because the input LO and output IF are differential signals, these signals must be taken from two GSGSG pads which are conveyed with CASCADE -GSGSG-150 probes. The LO signals are generated by signal generator cascading with a transformer to translate the single-end LO signal to differential. Finally the differential output signal is connect to power combiner to combine the differential signal to single-end and observed by spectrum analyzer.

There are six DC powers that must be supplied to the receiver circuit which are probed using 150-pitch 6P DC probe and the additional off-chip dc bias is not required. To measure the linearity property of the receiver, we can vary the input power and observe the output spectrum. The power loss induced from the cable and probes must be compensated at desired frequency to acquire the practical gain of the circuit. Figure 4.10 to Figure 4.13 depict the measurement block diagrams.

Figure 4.9 Chip microphotograph of the receiver

Figure 4.10 Instrument setup for Rx S-parameter analysis

Figure 4.11 Instrument setup for Rx spectrum analysis

Figure 4.12 Instrument setup for Rx noise analysis

Figure 4.13 Instrument setup for Rx waveform analysis

4.3 Experiment Results

Circuits are fabricated using CMOS 0.13-um 1P8M CMOS technology with ultra thick metal measuring 3.3 um. The chip is measured using on-wafer probing. Here we show the measurement results of LNA and receiver circuit respectively.

4.3.1 Experiment Results of 70-GHz LNA

In the first, the s-parameters of the LNA are measured while the input power is set constant at -15 dBm. The gate voltage at the input stage of MOS is biased at 0.7 V due to optimal noise and gain considerations. The circuit is supplied at a 0.8-V supply voltage with the dc power consumption of 5.4 mW and the chip area is only 0.38 mm² including all the test pads and dummy metals. The measured gain is plotted against frequency are presented in Figure 4.14. The measurement shows that a maximum gain of 9.1 dB at 68.5 GHz and 3-dB bandwidth covers from 65.1 GHz to 72.3 GHz. The input and output return losses are shown in Figure 4.15 and Figure 4.16, respectively. Under the operating frequency, input and output return losses are 12 dB and 14 dB, respectively.

Figure 4.18 illustrates the linearity performance, P_1dB, of the proposed LNA. With a 0.8-V supply voltage, the input-referred 1 dB compression point (P1dB-in) is -17 dBm at the center frequency. This result ensures that input power of S21 gain measurement is larger than P1dB point and the power gain is limited by circuit linearity. Figure 4.19 shows the re-measurement results under input power of -40 dBm at out laboratory and comparison with simulation result. It performs that the circuit has a gain of 10.9 dB at 67.8 GHz with a 3-dB bandwidth of 7 GHz from 65 to 72 GHz. So far, we still cannot measure the noise figure performance and the measurement result of the noise figure is not shown here. The noise figure measurement is waiting for the instruments and will be measured in the future. Table 4.1 lists the summary of the LNA measurement and comparison with post-simulation results.

Figure 4.14 Measured S21 for the proposed LNA

Figure 4.15 Measured S11 for the proposed LNA

Figure 4.16 Measured S12 for the proposed LNA

Figure 4.17 Measured S22 for the proposed LNA

Figure 4.18 Measured 1-dB compression point for the proposed LNA

Figure 4.19 Measured simulated power gain for the proposed LNA

Table 4.1 Summary of the 70-GHz LNA

Comparing with post-simulation results, the fabricated chip possibly fell on the corner between SS and TT corners. It is accordance with the DC power consumption under the same DC bias condition. The proposed circuit consumes 5.4 mW and is between TT and SS corners that are simulated. The frequency shift of the proposed circuit is around 1 GHz and is less than 1.5 % when normalized with center frequency. This may come from the process variation of the transmission line that may not be predicted under simulation. Although we are not measured the noise figure performance, owing to the input/output return loss and power gain performance of the measurement result is close to the simulation results, the noise figure performance around 5 dB can be expected. The actual value of the noise figure can be measured after the high-frequency measurement instruments arrive.

4.3.2 Experiment Results of 60-GHz Receiver

The chip is designed and fabricated using 0.13-um CMOS technology with a total die area of 1.2mm² including all test pads and dummy metal. The circuit is biased at a 1.2-V supply voltage with current consumption of 3, 0.5, and 6 mA for the LNA, mixer, and frequency tripler respectively. The circuit dc power consumption is about 11.4 mW excepting the buffer power consumption.

In the first, the input return loss (S11) of the receiver is shown in Figure 4.20. The measured S11 is below than -10 dB for frequency larger than 60 GHz. When measure the other parameter of receiver such as conversion gain and IF-bandwidth, the LO and RF power levels are set constant at 6 dBm and -40 dBm, respectively. Figure 4.21 shows the measured conversion gain of the receiver and the IF frequency is chosen as 50 MHz. To observe the conversion gain of the different RF frequency, the LO frequency is chosen as:

LO = (RF−IF) / 3. The measurement shows that 11-dB maximum conversion gain with 3-dB bandwidth covering from 50.5 to 58.5 GHz.

To evaluate the large-signal behavior of the receiver, the P1dB_in is measured as shown in Figure 4.22. The measured P_{1dB_in} is estimated as the receiver gain drops 1 dB and is occurred when input power reaches -12 dBm. Due to the measurement instrument limitations, the LO and IF port input return loss and the noise figure performance cannot be measured in this circuit. However, the LO signal is supplied by signal generator and the LO power can be enhanced by tuning the signal generator. Since IF output frequency is 50 MHz or 100 MHz, the output impedance matching can easily be achieved by using the resistance and is not critical at such a low frequency. Table 6.2 summaries the measured results of the overall receiver circuit.

Figure 4.20 Measured S11 for the proposed receiver

Figure 4.21 Measured conversion gain for the proposed receiver

Figure 4.22 Measured P1dB for the proposed receiver

Table 4.2 Summary of the RUT

Post-simulation Measurement

Technology TSMC 0.13-um 1P8M

Frequency band 56 ~65 GHz 56.3 ~65.5 GHz 56.9 ~ 65.3 GHz 50.5 ~ 58.5 GHz

Corner FF TT SS none

VDD 1.2 V

Gate Bias 0.65 V / 0.65 V (LNA/Tripler)

S11 (< -9.5 dB ) > 58.5 GHz > 58.6 GHz > 58.7 GHz > 60 GHz

LO Power (dBm) 4 4 4 6

Gain (dB) 25.6 24.4 21.8 13.9

P1dB (dBm) -23.9 -22.8 -20.9 -12

NF (dB) 7.5 7.7 8.3 *

Power (mW) 20.6 14.4 10.3 11.4

4.4 Discussions and Comparisons

From the comparison shown in Table 1, the peak gain frequency of 67.8 GHz is in good agreement with the design value of 69 GHz. The gain mismatch between simulation and measurement results may come from the EM simulation inaccuracy. In the other words, the quality factor of the micro-strip transmission line is not good enough as expected.

All of the T-lines characteristics are simulated using an EM simulator, Ansoft HFSS.

Comparing with another EM simulator, Sonnet, the quality factor of the HFSS is much better than the sonnet. This may be caused from the dissimilar of mathematical calculation or the difference of simulation settings. Another factor that may effect the simulation is the inaccurate active device modeling at high frequency beyond 30 GHz. Since the circuit is operating under 70-GHz band, the active device performance may somehow different from the simulation. Table 4.3 summarizes the previously reported CMOS LNAs operated above 50 GHz and compared with the proposed LNA circuit. The proposed LNA exhibits lower NF and small power consumption as comparing with other works.

Table 4.3 Comparison of previously reported LNAs for frequency above 50 GHz

Table 4.3 Comparison of previously reported LNAs for frequency above 50 GHz