Design Consideration of Mixer

The proposed mixer is realized by a single-balanced mixer here. Differential output is preferred for higher conversion gain which is twice of single end and more immunity to RF-IF feed-through. Otherwise, any strong interferers at RF port will undergo inter-modulation. For the same power consumption, the input referred noise of the single balanced mixer is less than that of double-balanced architecture. A main drawback is high LO to IF feed-through, which may desensitize the subsequent stage. To analysis the mixer performances, two of the most importance parameters, linearity and conversion gain is discussed here in the following subsections.

Linearity

As same as amplifiers, 1-dB compression point defines the upper limit of a mixer’s dynamic range. The compression in a mixer can occur due to two reasons: the limitation of voltage headroom or due to odd order nonlinearity. Though the third order intercept point (IIP₃) measures only the third order nonlinearity, high order harmonic nonlinearity should be considered where higher input power is available. A balanced structure could normally suppresses even order distortion and enhance LO to RF isolation. However, the benefits of balanced structure would be degraded due to device mismatch in the RF path. For direct conversion application, even order distortions also need to be considered because even order harmonic of LO signal would also be translated to DC level due to even order of RF signal.

Thus, we applied the circuit to translate the RF signal to very low IF signal such as 50 MHz to avoid this kind of distortion. Besides reducing the harmonic effect, the over-all linearity of the mixer can be improved by providing enough headroom.

The available headroom in most cases is limited by VDD, especially in deep-submicron technology with low supply voltage which would greatly restrict the output voltage swing.

The available voltage headroom is mainly depended on bias conditions and choice of load

resistance. Thus the available headroom can be expressed as V_headroom =V -V_{DD DSmin}-V_x, where VX is the voltage drop of current source and V_DSmin =V -V_{GS TH} ∝ I_D for a long channel and approaching to V_DSmin =V -V_{GS TH}∝I_D for short channel due to velocity saturation. By appropriate selecting the DC bias condition, the entire linearity performance can be improved.

Taking away the gm stage in proposed mixer, the linearity limitation cause by g_m stage would no more need to be concerned. This approach can eliminate the trade off between linearity and noise figure and may have better linearity comparing to Gilbert cell mixer

Conversion Gain

To simplify the analysis, we could consider the differential pair in the mixer stage as ideal MOS switches which translate the signal to IF and degrade the amplitude to2

π . From the mixer architecture of Figure 3.23, the input signal amplified by LNA would see the input impedance of 1

s m

g
R which RS means the equipment resistance that inductor resonates with parasitic capacitances of MOS. The small signal current that flows to the load impedance can

be expressed as _d 1

where gm is the trans-conductance of differential pair and RL is the output resistance of mixer load. Considering finite output resistance of the MOS in the switching core, the load resistance would change toR_L =r_o
R_Load. Hence, we could increase the RL and MOS size of differential pair to enhance the conversion gain. In contrast to the gain enhancement while increasing RL, the linearity would be obviously reduced due to the headroom reduction caused by I_SR_L and they would be trade-off. Hence we should determinate the appropriate value of R_L, gm and bias current to achieve the required performance.

Since the differential pair is taken as ideal switch, the LO signal must be an ideal square

wave that could perfectly switch the MOS to turn-on and turn-off. However, the LO signal is a sine-wave not a perfect square wave, thus we need to increase the amplitude to make the MOS to perform better.

Noise Figure

Noise analysis of the mixer is much more complicated due to frequency translation. The noise in the mixer is generated due to the switching quad and load resistance. The noise in the proposed mixer is dominated due to the thermal noise of switching quad and load resistance.

The high frequency noise contributed from the current source M_b2 would be filtered out by the bypass capacitance Cb1 and would not affect the mixer noise performance. Comparing to conventional Gilbert cell mixer, which is contributed from trans-conductance stage, switching quad and load resistance, this architecture eliminates the noise contribution from trans-conductance stage and greatly reduce the entire noise figure. While the mixing operation takes place, noise associated with the RF band is down converted to the IF band along with the signal, and flicker noise is up converted to the LO band. Since for 60GHz application, we expected to down convert to 50 MHz band, noise contribution due to flicker noise is neglected here.

The noise in the IF frequency at load of mixer would translate to RF frequency by mixing with LO signal. The load of mixer chooses to be resistance instead of PMOS load here to avoid the flicker noise contributed from MOSFET.

The MOSFET in the switching pair contribute noise only when they are in the “on” state.

Where γn is channel noise factor for NMOS device and IS means the bias current for switching

core and VLO is the LO swing that supplies to gate. Though this simple expression is

independent of the device width, in reality the noise due to this switching core increases with the increase of the device size [41]. As the LO generates several higher harmonics along with the fundamental frequency, those higher harmonics down-convert noise in the incoming input signal to IF band as shown in Figure 3.24. Thus the total output noise voltage of the mixer can be expressed as:

where noise due to the load resistance is:

2 8

n ,L L

V = KTR

Since the total mixer output noise is obtained, he noise figure can further be acquired by

2

Generally speaking, noise figure would be larger than this if flicker noise and substrate noise are considered.

Figure 3.24 Frequency translation of white noise from mixer input MOS