Chapter 4 Experiment Results
4.4 Discussions and Comparisons
From the comparison shown in Table 1, the peak gain frequency of 67.8 GHz is in good agreement with the design value of 69 GHz. The gain mismatch between simulation and measurement results may come from the EM simulation inaccuracy. In the other words, the quality factor of the micro-strip transmission line is not good enough as expected.
All of the T-lines characteristics are simulated using an EM simulator, Ansoft HFSS.
Comparing with another EM simulator, Sonnet, the quality factor of the HFSS is much better than the sonnet. This may be caused from the dissimilar of mathematical calculation or the difference of simulation settings. Another factor that may effect the simulation is the inaccurate active device modeling at high frequency beyond 30 GHz. Since the circuit is operating under 70-GHz band, the active device performance may somehow different from the simulation. Table 4.3 summarizes the previously reported CMOS LNAs operated above 50 GHz and compared with the proposed LNA circuit. The proposed LNA exhibits lower NF and small power consumption as comparing with other works.
Table 4.3 Comparison of previously reported LNAs for frequency above 50 GHz
Reference [7]
From the comparison between simulation and measurement results which is illustrated in Table 2, there are large amount differences between them. Main differences are the power gain mismatch and the frequency shift. Since the power consumption of each stage is reasonable as comparing with simulation, each building block can be taken as working normally. Moreover, when obtaining the output spectrum from baseband to RF frequency, there is not any unexpected signal tone and shows the circuit blocks are not oscillating. From the output signal spectrum, it also shows the tripler circuit exactly performs the right function to down convert the RF frequency to the baseband using LO frequency of only 1/3 RF frequency.
By carefully checking the layout of the circuit, we find out the most critically error is caused by the schematic wrong in the LNA, as shown in Figure 4.23. This cause the MOS M3 on the cascode stage becomes diode connect and hence, the second stage of the LNA almost provide 0-dB gain here and greatly reduce the entire gain. The modified simulation result of the power gain is shown in Figure 4.24.
Since the schematic error can be checked from the LVS (layout versus schematic), but this inductor is implemented using Tline. To LVS, the Tline is nothing more than a metal and cannot find if the layout is wrong. To overcome this problem, we can choose a given device model such as resistance to replace with the Tlines to check the LVS. After that, we can put the Tlines back to the circuit and remove the given device. Finally, check the LVS one more time. By using this method, we can ensure the circuit layout is completely match to the schematic when using the Tlines.
Figure 4.23 The schematic error of the LNA circuit in receiver
Figure 4.24 The modified simulation result and comparsion with measurement results
Second, the frequency shift of the conversion gain is discussed. The most probably reason is the inductance value mismatch with the layout. Observing the layout of the transmission line, we find that the short length of interconnect between two MOS is disregarded in simulation, as shown in Figure 4.25. Since the circuit is operating under high frequency and the resonating inductance is relatively small, a small amount of inductance will cause the large frequency shift. For example, the resonate inductances at 60-GHz is around 200 pH and if the interconnect has the inductance of 5 pH, the frequency shift will go to about 1.5 GHz. After compensate the interconnection inductance into the circuit, the receiver is re-simulated and comparing with measurement results. The modified simulation result of the power gain is shown in Figure 4.26. As can be seen, the center frequency of the receiver is down to 57 GHz and is closer to the measurement result. Table 4.4 shows the comparison summary of post-simulation, modified-simulation, and measurement results.
Figure 4.25 The transimission line layout of the receiver
Figure 4.26 The modified post-simulation results of conversion gain
Table 4.4 Comparison of measurement and modified simulation results
Post-simulation Modified-Simulation Measurement Frequency band 56.9 ~ 65.3 GHz 53.3 ~ 61.2 GHz 50.5 ~ 58.5 GHz
Corner SS SS none
VDD 1.2 V
Gate Bias 0.65 V / 0.65 V (LNA/Tripler)
S11 (< -9.5 dB ) > 58.7 GHz > 55.6 GHz > 60 GHz
LO Power (dBm) 4 4 6
Gain (dB) 21.8 16.8 13.9
P1dB (dBm) -20.9 -16.5 -12
NF (dB) 8.3 9.3 *
Power (mW) 10.3 10.3 11.4
The gain mismatch between the simulation and measurement may also come from the considerations and fine tune the circuit layout and EM simulation, the proposed receiver can work as well as expected.
Finally, Table 4.5 presents the comparison of this work and other published 60-GHz receivers. This work has superior advantage of low noise and low power consumption. More importantly, by applying the frequency tripler, only 20-GHz frequency synthesizer is required in this architecture and is suitable for 60-GHz applications.
Table 4.5 Performance comparison with other 60-GHz receiver
This work
Architecture Homodyne Homodyne Homodyne Heterodyne Heterodyne Frequency (GHz) 50.5 ~ 58.5 56.3 ~65.5 57.5~64 49.5~ 57~63
†including tripler =receiver core + tripler (20GHz VCO can be implemented by 8mW) †† simulation result *including IF amplifier ** including 40-GHz VCO and divider ***including 29 GHz VCO and doubler
Chapter 5 Conclusions and Future Work
5.1 Conclusions
Two V-band circuits: 70-GHz LNA and 60-GHz direct-conversion receiver which consists a LNA, a down-conversion mixer and frequency tripler have been designed, fabricated and tested in a 0.13-um CMOS technology.
In the proposed LNA, three-stage common-source topology is used instead of cascode configuration to improve the noise performance. Therefore, supply voltage can be reduced to 0.8 V for low voltage and low power design. The measured LNA gain is 10.9 dB and the simulated noise figure is 5.1 dB at 67.8 GHz while the input and output return losses are lower than -12 dB at center frequency. Furthermore, the 3-dB bandwidth covers from 65 GHz to 72 GHz which is suitable for wideband applications. Finally, this circuit can be operated on a low voltage of 0.8-V and only consumes 5.4 mW with a chip size of 0.38mm2. According to the comparisons in Table 4.3, the proposed LNA shows low noise, low power and low supply voltage while achieving reasonable power gain and wideband input and output matching. It is proved that the proposed LNA is feasible to use it in building fully integrated receiver at frequency of above 50 GHz.
A 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is also proposed. The receiver consists of a two-stage LNA, a single-balanced active mixer, a frequency tripler, and output buffers. By using a frequency tripler, the operating frequency of the frequency synthesizer can be reduced from 60 GHz to 20 GHz, so the implementation of the frequency synthesizer also becomes much easier. According to the measurement results,
the receiver has power gain of 13.9 dB with 3-dB bandwidth covering from 50.5 to 58.5 GHz.
The input-referred 1-dB compression point is about -12 dBm and the input return loss of -5dB at center frequency of 54.5 GHz. The simulated noise figure (NF) is about 9.2 dB. The entire circuit consumes 15.1 mW from 1.2-V power supply.
Finally, the main cause of the malfunction of the receiver has been found and verified lying in the schematic of LNA and interconnection between MOS to MOS. According to the comparisons in Table 4.5 Performance comparison with other 60-GHz receiver, the post-simulation of the receiver shows better performance on operating frequency of 57 ~64 GHz band, low noise figure and low power consumption as compared to other state-of-the-art works. It shows that the proposed receiver is very suitable to be applied in 60 GHz ISM band and has the great potential to be integrated with PLLs and baseband circuits. Furthermore, we believe the proposed method can also be applied to the other high frequency receiver circuit such as 77 GHz radar or even more high frequency systems.
5.2 Future work
The proposed direct-conversion receiver for 60-GHz ISM applications could be fabricated again with the modification of schematic error and taken the interconnection effects into account. To realize the complete homodyne receiver circuits, the I/O mixer and I/Q VCO can be implemented together with the LNA and frequency tripler circuits. Finally, the 20-GHz frequency synthesizer may also be included to provide a stable local frequency and form the more complete system.
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Appendix
Re-designing the receiver circuit
Besides compensating the layout error and take the parasitic capacitance of the interconnection lines into account, we also modified the circuit to improve the performances of the receiver.
At first, in order to reduce the DC bias pins, the scheme of the output buffer is modified to the open drain structure and the supply voltage can be provided off-chip. Moreover, we also make the supply voltage of the LNA, mixer and frequency tripler together which provide the same voltage level in the circuit. Hence, the DC pads can be reduced from 6-pin to 3-pin and can scale down the entire chip area greatly.
Second, the conversion gain of the mixer is designed as large as possible to improve the gain performance. Since the larger gain may limit the linearity performance, but from the experiment, the measurement gain will be larger than expected and we can pre-design the larger gain to compensate this mismatch.
In previous work, the gate bias of the frequency tripler core circuit and frequency tripler output buffer are co-designed to be 0.65 V, but we cannot just change the gate bias of the core circuit to observe the maximum frequency transition. Hence, in this case, the gate bias of the frequency tripler core circuit is also implemented off-chip and we can change the bias point individually to get the best receiver performance.
Moreover, ground planes of all the transmission lines are implemented by using only M1 as ground plane improve the quality factors. Comparing to use the M1,M2 or M1,M2,M3 as the ground planes, the circuit can get the better noise performance and larger gain. The layout view of the re-designed receiver is shown in (a) and the re-designed receiver performances are shown in the (b) to (d). The total power consumption of the proposed receiver circuit is 14.2 mW. Finally, the comparison of the previous works are illustrated in Table a.
(a) The layout view of the re-designed receiver
(b) Simulated conversion gain and noise figure of the re-designed receiver
(c) Simulated P1dB of the re-designed receiver
(d) Simulated R11 of the re-designed receiver
Table a Performance comparison with other 60-GHz receiver
Architecture Homodyne Homodyne Homodyne Homodyne Heterodyne Heterodyne Frequency (GHz) 50.5 ~ 58.5 56.3 ~65.5 55.5 ~65 57.5~64 49.5~ 57~63
IF Amplifier No No No Yes Yes Yes
Technology 0.13 um
† Including tripler =receiver core + tripler (20 GHz VCO can be implemented by 8mW)
† † Modified simulation result
*Including IF amplifier ** Including 40-GHz VCO and divider ***Including 29-GHz VCO and doubler
By re-designing the circuit, the receiver can achieve the noise figure of 7.6 dB, a power gain of 29.2 dB and P1dB of -25.8 dBm. It only consumes 14.2-mW power and the total chip area can be reduced to 0.63 mm2. This is suitable for low-power and low noise 60-GHz system applications.
簡歷
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