國 立 交 通 大 學
電子工程學系 電子研究所碩士班
碩
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60-GHz 互補式金氧半
互補式金氧半
互補式金氧半
互補式金氧半導體前端接收器
導體前端接收器
導體前端接收器
導體前端接收器
之設計與分析
之設計與分析
之設計與分析
之設計與分析
The Design and Analysis of 60-GHz CMOS
Receiver Front-end
研 究 生：陳柏宏
指導教授：吳重雨 博士
中
中
中
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華
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民
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60-
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-GHz
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GHz 互補式金氧半導體前端接收器
互補式金氧半導體前端接收器
互補式金氧半導體前端接收器
互補式金氧半導體前端接收器
之設計與分析
之設計與分析
之設計與分析
之設計與分析
The Design and Analysis of 60-GHz CMOS
Receiver Front-end
研究生: 陳柏宏
Student: Po-Hung Chen
指導教授: 吳重雨 博士
Advisor: Dr. Chung-Yu Wu
國 立 交 通 大
國 立 交 通 大
國 立 交 通 大
國 立 交 通 大 學
學
學
學
電 子 工 程 學
電 子 工 程 學
電 子 工 程 學
電 子 工 程 學 系
系
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系
碩 士 論
碩 士 論
碩 士 論
碩 士 論 文
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A ThesisSubmitted to Department of Electronics Engineering & Institute of Electronics National Chiao Tung University
in partial Fulfillment of the Requirements for the Degree of
Master In
Electronics Engineering
July 2007
HsinChu, Taiwan, Republic of China 中 華 民 國 九 十 六 年 七 月
60-GHz 互補式金氧半
互補式金氧半
互補式金氧半
互補式金氧半導體前端接收器
導體前端接收器
導體前端接收器
導體前端接收器
之設計與分析
之設計與分析
之設計與分析
之設計與分析
研究生
研究生
研究生
研究生:
:
: 陳柏宏
:
陳柏宏
陳柏宏
陳柏宏
指導教授
指導教授:
指導教授
指導教授
:
:
: 吳重雨
吳重雨
吳重雨
吳重雨
博士
博士
博士
博士
國立交通大學
國立交通大學
國立交通大學
國立交通大學
電子工程學系
電子工程學系
電子工程學系
電子工程學系
電子研究所碩士班
電子研究所碩士班
電子研究所碩士班
電子研究所碩士班
摘要
摘要
摘要
摘要
具有高操作頻率且高傳輸速率的通訊系統已被視為次世代通訊系統的主軸 具有高操作頻率且高傳輸速率的通訊系統已被視為次世代通訊系統的主軸 具有高操作頻率且高傳輸速率的通訊系統已被視為次世代通訊系統的主軸 具有高操作頻率且高傳輸速率的通訊系統已被視為次世代通訊系統的主軸。。。。在近在近在近在近 幾年 幾年 幾年 幾年，，，，60606060----GHzGHzGHzGHz 附近的頻帶中附近的頻帶中附近的頻帶中附近的頻帶中，，已有，，已有已有已有 777-7-GHz--GHzGHz 的頻寬被釋出做為高速短距離通訊系統使用GHz的頻寬被釋出做為高速短距離通訊系統使用的頻寬被釋出做為高速短距離通訊系統使用的頻寬被釋出做為高速短距離通訊系統使用。。。。 此頻帶具有可應用在高達十億位元高傳輸速率的無線個人網路 此頻帶具有可應用在高達十億位元高傳輸速率的無線個人網路 此頻帶具有可應用在高達十億位元高傳輸速率的無線個人網路此頻帶具有可應用在高達十億位元高傳輸速率的無線個人網路(WPAN)(WPAN)(WPAN)以及點對點傳(WPAN)以及點對點傳以及點對點傳以及點對點傳 輸上的潛力 輸上的潛力 輸上的潛力 輸上的潛力。。。。 此論文中介紹了一個與三倍頻器整合的 此論文中介紹了一個與三倍頻器整合的 此論文中介紹了一個與三倍頻器整合的
此論文中介紹了一個與三倍頻器整合的 606060-60--GHz CMOS-GHz CMOS 直接降頻式接收器GHz CMOSGHz CMOS直接降頻式接收器直接降頻式接收器。直接降頻式接收器。。。此接收此接收此接收此接收 器包含了低雜訊放大器
器包含了低雜訊放大器 器包含了低雜訊放大器
器包含了低雜訊放大器、、、、降頻混降頻混降頻混頻器以及三倍頻器等電路降頻混頻器以及三倍頻器等電路頻器以及三倍頻器等電路頻器以及三倍頻器等電路，，並且使用了，，並且使用了並且使用了 0.13並且使用了0.130.130.13----um CMOSum CMOSum CMOSum CMOS 技術來設計並製造 技術來設計並製造 技術來設計並製造 技術來設計並製造。。。藉由使用三倍頻器。藉由使用三倍頻器藉由使用三倍頻器藉由使用三倍頻器，，所需要的頻率合成器之操作頻率可以由，，所需要的頻率合成器之操作頻率可以由所需要的頻率合成器之操作頻率可以由所需要的頻率合成器之操作頻率可以由 60 60 60 60 GHzGHzGHzGHz 降至 降至 降至 降至 202020 20 GHzGHzGHzGHz，，並使得頻率合成器的實現變，，並使得頻率合成器的實現變並使得頻率合成器的實現變並使得頻率合成器的實現變得得得得較較為較較為為為容易容易容易容易。。根據量測結果顯示。。根據量測結果顯示根據量測結果顯示根據量測結果顯示，，，，此電路由此電路由此電路由此電路由 於佈局時發生的錯誤 於佈局時發生的錯誤 於佈局時發生的錯誤 於佈局時發生的錯誤，，，使得增益降至，使得增益降至使得增益降至 13.9 dB使得增益降至13.9 dB13.9 dB13.9 dB。。量測結果證實此電路具有。。量測結果證實此電路具有量測結果證實此電路具有 50.5 GHz 量測結果證實此電路具有50.5 GHz 50.5 GHz 50.5 GHz 到到到到 58.5 GHz 58.5 GHz 58.5 GHz 58.5 GHz 的頻寬的頻寬的頻寬的頻寬，，，，以及在中心頻率以及在中心頻率以及在中心頻率以及在中心頻率 54.5 GHz54.5 GHz54.5 GHz54.5 GHz 具有具有具有具有--12 dBm--12 dBm12 dBm 的輸入12 dBm的輸入的輸入的輸入 11-11---dBdBdBdB 增益壓縮點與增益壓縮點與增益壓縮點與增益壓縮點與 --5 dB5 dB5 dB5 dB 的的的的 S11S11 特性S11S11特性特性特性。。。。並且並且並且並且，，從修改後的模擬結果可知，，從修改後的模擬結果可知從修改後的模擬結果可知從修改後的模擬結果可知，，，，雜訊大小約在雜訊大小約在雜訊大小約在雜訊大小約在 9.2 dB9.2 dB 左右9.2 dB9.2 dB左右左右左右。。。。此此此此 電路操作在 電路操作在 電路操作在 電路操作在 1.2 1.2 V1.2 1.2 VVV 的供應電壓下的供應電壓下，的供應電壓下的供應電壓下，，，並且消耗並且消耗並且消耗並且消耗 11.4 mW11.4 mW 的直流功率11.4 mW11.4 mW的直流功率的直流功率。的直流功率。。除此之外。除此之外除此之外，除此之外，，，此論文此論文此論文此論文 中也討論了造成頻率漂移以及增益降低的原因 中也討論了造成頻率漂移以及增益降低的原因 中也討論了造成頻率漂移以及增益降低的原因 中也討論了造成頻率漂移以及增益降低的原因。。。。從討論可知從討論可知從討論可知從討論可知，，若小心佈局電路，，若小心佈局電路若小心佈局電路若小心佈局電路，，，，此架此架此架此架 構的接收器可達到比量測結果更優異的特性 構的接收器可達到比量測結果更優異的特性 構的接收器可達到比量測結果更優異的特性 構的接收器可達到比量測結果更優異的特性，，，，並且非常適合用在低功率並且非常適合用在低功率並且非常適合用在低功率並且非常適合用在低功率，，，，高傳輸速率高傳輸速率高傳輸速率高傳輸速率 的無線通訊系統中 的無線通訊系統中 的無線通訊系統中 的無線通訊系統中。。。。
除了 60除了除了除了 606060--GHz--GHzGHz 接收器之外GHz 接收器之外接收器之外接收器之外，，，，此論文也提出一個此論文也提出一個 70此論文也提出一個此論文也提出一個 707070----GHzGHz 的低雜訊放大器電路GHzGHz 的低雜訊放大器電路的低雜訊放大器電路的低雜訊放大器電路。。。。在在在在 此低雜訊放大器中 此低雜訊放大器中 此低雜訊放大器中 此低雜訊放大器中，，，我們使用了三級串接的共源級架構來取代高頻常見的疊接架構以，我們使用了三級串接的共源級架構來取代高頻常見的疊接架構以我們使用了三級串接的共源級架構來取代高頻常見的疊接架構以我們使用了三級串接的共源級架構來取代高頻常見的疊接架構以 提升雜訊特性 提升雜訊特性 提升雜訊特性 提升雜訊特性。。。並且可將電路的供應電壓降至。並且可將電路的供應電壓降至並且可將電路的供應電壓降至並且可將電路的供應電壓降至 0.8 V0.8 V0.8 V0.8 V 來達到低電壓以及低功率的設來達到低電壓以及低功率的設來達到低電壓以及低功率的設來達到低電壓以及低功率的設 計 計 計 計。。。。量測結果顯示此低雜訊放大器在中心頻率具量測結果顯示此低雜訊放大器在中心頻率具量測結果顯示此低雜訊放大器在中心頻率具量測結果顯示此低雜訊放大器在中心頻率具有有有有 10.9 dB10.9 dB10.9 dB 增益10.9 dB增益，增益增益，，，以及小於以及小於以及小於以及小於--12 dB--12 dB12 dB12 dB 的的的的 S11 S11 S11 S11 以及以及 S22以及以及S22S22S22 特性特性特性。特性。。由模擬結果可知在。由模擬結果可知在由模擬結果可知在 67.8 GHz由模擬結果可知在67.8 GHz 的雜訊大小可達到67.8 GHz67.8 GHz的雜訊大小可達到的雜訊大小可達到的雜訊大小可達到 5.1 dB5.1 dB5.1 dB5.1 dB。。。。 除此之除此之除此之除此之 外 外 外 外，，，，此電路涵蓋了此電路涵蓋了此電路涵蓋了此電路涵蓋了 656565 至65至至至 72 GHz72 GHz72 GHz 的頻寬72 GHz的頻寬，的頻寬的頻寬，，非常適合用在寬頻的應用上，非常適合用在寬頻的應用上非常適合用在寬頻的應用上。非常適合用在寬頻的應用上。最後。。最後最後最後，，，，這個操這個操這個操這個操 作在 作在 作在 作在 0.80.80.80.8----VV 低電壓的電路所消耗的功率只有VV低電壓的電路所消耗的功率只有低電壓的電路所消耗的功率只有 5.4 mW低電壓的電路所消耗的功率只有5.4 mW5.4 mW5.4 mW，，並被實現在，，並被實現在並被實現在並被實現在 0.380.380.38 0.38 mmmmmmmm2222的晶片面的晶片面的晶片面的晶片面 積中 積中 積中 積中。。。。此結果證實了此電路非常適合用在此結果證實了此電路非常適合用在此結果證實了此電路非常適合用在此結果證實了此電路非常適合用在 50 GHz50 GHz50 GHz 以上高頻的接收器中50 GHz以上高頻的接收器中以上高頻的接收器中以上高頻的接收器中。。。。
The Design and Analysis of 60-GHz CMOS
Receiver Front-End
Student: Po-Hung Chen
Advisor: Dr. Chung-Yu Wu
Department of Electronic Engineering &
Institute of Electronics
National Chiao Tung University
Abstract
In the next-generation wireless communication, high data rate transmission with a high operating frequency is expected. Over the past few years, the 7-GHz unlicensed band around 60 GHz has been released for high-speed and short-range communication systems. It has great potential in application of high data-rate wireless personal–area network (WPAN), high speed WLAN and point-to-point link, with possible data rate of gigabits per second.
In this thesis, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is presented. The proposed receiver which consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler are designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the frequency synthesizer can be reduced from 60 GHz to 20 GHz. This makes the implementation of the frequency synthesize much easier. Based on measurement results, as a result of the layout error, the receiver power gain is decreased to 13.9 dB. The measurement result presents the main circuit characteristics: covering 3dB-bandwidth from 50.5 GHz to 58.5 GHz,
input-referred 1-dB compression point of -12 dBm, input return loss of -5 dB at center frequency of 54.5 GHz and consumes 11.4 mW from 1.2-V power supply. Moreover, the re-simulated noise figure (NF) considering the undesired effects is about 9.2 dB. Afterwards, the reasons of malfunction which cause the frequency shift and gain reduction are discussed here. From the discussion, with the carefully layout, the proposed receiver can achieve much better performance than measurement and is confirmed to be suitable for low-power and high data-rate wireless communication systems.
Besides the 60-GHz receiver, a 70-GHz LNA is also presented. In the proposed LNA, three-stage common-source topology is used instead of cascode configuration to improve the noise performance. As a direct consequence of the use of common source structure in the proposed LNA, the voltage can be reduced to 0.8 V, which is much lower than that for the cascode structure. Therefore, the level of power consumption can be reduced greatly. The measured LNA gain is about 10.9 dB and the input and output return losses are lower than -12 dB at center frequency with the simulated noise figure of 5.1 dB. Furthermore, the 3-dB bandwidth covers from 65 GHz to 72 GHz which is suitable for wideband applications. Finally, this circuit can be operated on a low supply voltage of 0.8-V and only consumes 5.4 mW with a 0.38 mm2 chip area. It is proved that the proposed LNA is feasible to use it in building fully integrated receiver at frequency of above 50 GHz.
誌謝
誌謝
誌謝
誌謝
首先我要對吳重雨老師多年來的細心栽培與指導致上最誠摯的感謝。在老師的諄 諄教誨下，不僅學會了積體電路設計方面的技巧及專業知識，在面對人、事、物的態 度以及解決問題的方法也是受益良多。尤其在實驗室豐富的硬體及軟體資源的支援 下，提供了我一個最佳的學習環境。此外要感謝老師在我研究方向最迷惘的時候，給 予我適時的指導與啟發，以及對於我想法的支持與鼓勵，師恩浩蕩，銘記於心。再來 要感謝論文口試的評審委員郭建男教授、蕭碩源博士以及高宏鑫博士對我的建議與指 導。 在實驗室的夥伴中，首先感謝陳旻珓以及羅怡凱兩位壆長，在這兩年來總是全力 給予學習上的支持與指導。謝謝王文傑、虞繼堯、蘇烜毅、黃祖德、Fadi、詹豪傑學 長們在這一段時間給予了我許多幫助還有指點。也要感謝與我ㄧ路奮鬥的夥伴們，晏 維、順維、資閔、國忠、維德、必超、廷偉、雨軒、人文、旭佑、世豪、松諭、宗裕、 巧伶、萬諶、國軒、國權等一群好朋友及同學，共同渡過富有挑戰性的研究生階段。 除了這兩年一起在實驗室打拼之外，也在緊繃的生活中增添不少輕鬆的氣氛，使我的 碩士生活增添了很多美好的回憶。 最後，我要對我的家人致上最深最誠摯的感謝，感謝父母的養育之恩以及長久以 來無怨無悔的付出與栽培，在我面臨許許多多挑戰的時候，始終給予最堅強的後盾， 讓我無後顧之憂。也謝謝他們能支持我的想法，讓我自由的追逐自己的夢想，逐步邁 進。 陳柏宏 于 風城交大 96年 夏Contents
Chinese Abstract………i
English Abstract………ii
Contents………..………..iii
Table Captions………...viii
Figure Captions………ix
Chapter 1 Introduction... 1
1.1 Background...11.2 Reviews on CMOS RF Front-end Receivers...3
1.2.1 Receiver Architectures ...4
1.2.2 Review on 60-GHz CMOS Receivers...7
1.2.3 Review on Building Blocks of CMOS Receiver ...10
1.2.4 Review on Frequency Multiplier...13
1.3 Motivation ...15
1.4 Thesis Organization ...15
Chapter 2 A High-Frequency Frequency Multiplier ... 16
2.1 Design of the Frequency Tripler...16
2.1.1 Operational Principle ...16
2.1.2 Design Considerations...18
2.1.3 Circuit Realization...19
2.1.4 Simulation Results of Frequency Tripler ...23
2.2 Comparison with Previous Works ...27
Chapter 3 RF Front-End Circuits ... 29
3.1 Receiver Architecture and Design Considerations ...29
3.2 Low Noise Amplifier Design...34
3.2.1 Design Consideration ...35
3.2.2 A 0.8-V 70-GHz Three-stage Cascaded Common-source Topology with Inductive Feedback ...39
3.2.3 A 60-GHz Two-stage Low Noise Amplifier...42
3.3 Down Conversion Mixer ...54
3.3.1 Design Consideration of Mixer...55
3.3.2 Circuit Realization of Mixer ...59
3.3.3 Simulation Results of Mixer ...63
3.4 Simulation Results of Receiver Front-end ...65
Chapter 4 Experiment Results... 71
4.1 Layout Description ...71
4.2 Measurement Consideration and Setup ...74
4.3.1 Measurement of 70-GHz Low Noise Amplifier...74
4.3.2 Measurement of 60-GHz Receiver ...78
4.3 Experiment Results...81
4.3.1 Experiment Results of 70-GHz LNA ...81
4.3.2 Experiment Results of 60-GHz Receiver ...86
4.4 Discussions and Comparisons ...89
Chapter 5 Conclusions and Future Work... 95
5.1 Conclusions ...95
5.2 Future work ...96
List of Tables
Table 2.1 Detail parameters of proposed frequency tripler ... 20
Table 2.2 Post simulation summary of the proposed frequency tripler ... 27
Table 2.3 Comparison with published frequency multiplier... 28
Table 3.1 Detail parameters of 70GHz LNA ... 40
Table 3.2 Detail parameters of 60GHz LNA ... 43
Table 3.3 Post simulation summary of the 70GHz LNA ... 50
Table 3.4 Post simulation summary of the 70GHz LNA ... 53
Table 3.5 Device parameters of the down-conversion mixer circuit... 61
Table 3.6 Post simulation summary of the proposed mixer ... 65
Table 3.7 Post simulation summary of the receiver front-end with corner ... 69
Table 3.8 Post simulation summary of the receiver front-end with temperature variation ... 70
Table 3.9 Post simulation summary and compassion of the receiver front-end ... 70
Table 4.1 Summary of the 70-GHz LNA... 85
Table 4.2 Summary of the RUT... 88
Table 4.3 Comparison of previously reported LNAs for frequency above 50 GHz ... 89
Table 4.4 Comparison of measurement and modified simulation results ... 93
List of Figures
Figure 1.1 The architecture of the zero-IF receiver ... 3
Figure 1.2 The block diagram of super-heterodyne receiver ... 4
Figure 1.3 The block diagram of super-heterodyne receiver ... 5
Figure 1.4 The block diagram of [4]... 8
Figure 1.5 The block diagram of [5]... 8
Figure 1.6 The block diagram of [6]... 9
Figure 1.7 Circuit schematic of the V-band CMOS LNA in [8]... 10
Figure 1.8 Simplified circuit diagram of the single-gate quadrature balance mixer in [6] ... 11
Figure 1.9 (a) Conventional and (b) proposed mixer in [5]... 12
Figure 1.10 Simplified circuit diagram of the frequency doubler in [5] ... 13
Figure 1.11 Schematic circuit diagram of the 25.5-76.5 GHz single-ended frequency tripler ... 14
Figure 2.1 The circuit scheme of the proposed CMOS frequency tripler ... 19
Figure 2.2 Simulation results of even-order HRR due to R5... 21
Figure 2.3 The simulation results of odd-order harmonic output powers versus Ls... 21
Figure 2.4 The simulation results of even-order harmonic output powers versus Ls... 22
Figure 2.5 The simulation results of even-order HRR due to Ls... 22
Figure 2.6 The simulation results of the relative output power ... 24
Figure 2.7 The harmonic rejection ratio to different harmonic ... 24
Figure 2.8 The simulation results of the output waveform at 57 GHz ... 25
Figure 2.9 The simulation results of the output waveform at 60 GHz ... 25
Figure 2.10 The simulation results of the output waveform at 64 GHz ... 25
Figure 2.11 The output power versus fundament frequency input power at 20-GHz input ... 26
Figure 2.12 The phase noise contribution due to the frequency tripler ... 26
Figure 3.1 The proposed 60GHz direct-conversion receiver architecture ... 30
Figure 3.2 Geometrical lengths shortening by using Meander configuration ... 32
Figure 3.3 The test pattern of meander configuration ... 32
Figure 3.4 Inductance and quality factor variation as a function of S... 33
Figure 3.5 Inductance and quality factor variation as a function of S... 33
Figure 3.6 The input stage of proposed LNA ... 36
Figure 3.7 The equivalent noise model of the inductive degeneration configuration ... 36
Figure 3.8 The circuit diagram of CMOS V-band LNA ... 40
Figure 3.9 The circuit diagram of CMOS 60 GHz LNA ... 42
Figure 3.10 Comparison of simulated NFmin with different device width... 45
Figure 3.11 Comparison of simulated NFmin with different gate bias ... 45
Figure 3.12 (a) Conventional and (b) Proposed circuit diagram of Cascode topology ... 46
Figure 3.13 Simulated I/O return loss of the proposed 70GHz LNA ... 47
Figure 3.15 Simulated NF of the proposed 70-GHz LNA... 48
Figure 3.16 Simulated P1dB of the proposed 70GHz LNA ... 49
Figure 3.17 Simulated Rollet stability factor of the proposed 70GHz LNA ... 49
Figure 3.18 Simulated S11 of the proposed LNA of 60GHz receiver ... 51
Figure 3.19 Simulated voltage gain of the proposed LNA of 60GHz receiver ... 51
Figure 3.20 Simulated noise figure of the proposed LNA of 60GHz receiver... 52
Figure 3.21 Simulated P1dB of the proposed LNA of 60GHz receiver... 52
Figure 3.22 Simulated stability factor and meansure of the proposed LNA of 60GHz receiver... 53
Figure 3.23 Circuit block of the proposed down-conversion mixer ... 54
Figure 3.24 Frequency translation of white noise from mixer input MOS... 58
Figure 3.25 The circuit diagram of the proposed down-conversion mixer ... 61
Figure 3.26 The circuit diagram of the conventional Gilbert cell mixer... 62
Figure 3.27 The circuit diagram of the proposed LNA/mixer interface ... 62
Figure 3.28 Simulated noise figure of the proposed mixer... 63
Figure 3.29 Simulated conversion gain of the proposed mixer... 64
Figure 3.30 Simulated input 1dB compression point of the proposed mixer... 64
Figure 3.31 Simulated conversion gain of the direct-conversion receiver ... 66
Figure 3.32 Simulated noise performance of the direct-conversion receiver ... 67
Figure 3.33 Simulated linearity and P1dB of the direct-conversion receiver ... 67
Figure 3.34 Simulated output power as a function of LO input power at 60GHz ... 68
Figure 3.35 Simulated noise figure as a function of LO input power at 60GHz ... 68
Figure 3.36 Differential IF output waveform ... 69
Figure 4.1 The 70-GHz LNA layout view... 73
Figure 4.2 The 60-GHz receiver layout view. ... 73
Figure 4.3 Chip microphotograph of the LNA... 75
Figure 4.4 Measuring environment at laboratory ... 76
Figure 4.5 Measuring environment at NDL ... 76
Figure 4.6 Instrument setup for LNA S-parameter analysis... 77
Figure 4.7 Instrument setup for LNA spectrum analysis ... 77
Figure 4.8 Instrument setup for LNA noise analysis ... 77
Figure 4.9 Chip microphotograph of the receiver ... 79
Figure 4.10 Instrument setup for Rx S-parameter analysis ... 79
Figure 4.11 Instrument setup for Rx spectrum analysis... 80
Figure 4.12 Instrument setup for Rx noise analysis... 80
Figure 4.13 Instrument setup for Rx waveform analysis ... 80
Figure 4.14 Measured S21 for the proposed LNA ... 82
Figure 4.15 Measured S11 for the proposed LNA... 82
Figure 4.16 Measured S12 for the proposed LNA ... 83
Figure 4.18 Measured 1-dB compression point for the proposed LNA... 84
Figure 4.19 Measured simulated power gain for the proposed LNA ... 84
Figure 4.20 Measured S11 for the proposed receiver ... 87
Figure 4.21 Measured conversion gain for the proposed receiver... 87
Figure 4.22 Measured P1dB for the proposed receiver ... 88
Figure 4.23 The schematic error of the LNA circuit in receiver ... 91
Figure 4.24 The modified simulation result and comparsion with measurement results ... 91
Figure 4.25 The transimission line layout of the receiver... 92
Chapter 1
Introduction
1.1 Background
Over the past few decades, wireless communication systems have been under significant development and are more closely related to our daily life than ever before. The most active RF/microwave bands are called industrial, scientific and medical (ISM) bands at 2.4 GHz, 5.2 GHz and 5.8 GHz for wireless LAN, which were allowed by the FCC for unlicensed transmissions [1]. However, due to the relative lower bandwidth, these systems can only access several Mbps and remain bottleneck for wireless broadband communications. Nowadays, the wireless system is still surging under increasing demands of high data rate and lower power consumption. Therefore, these issues have motivated the system designer to explore the higher frequency bands such as 60-GHz ISM band.
Recently, a 7-GHz band covering the range from 57 to 64 GHz has been released for unlicensed use in high-speed and short-range communication systems. The attraction of this band is its large bandwidth of 7 GHz and the lack of restrictions. There is only a maximum power restriction, on the order of +40dBm depending on the continent. It has great potential in the application of high speed WLAN and point-to-point links, and offers a possible data rate of gigabits per second.
In general, building high frequency circuits usually use special semiconductor materials, such as InP or GaAs. These processes have much higher electron mobility comparing to silicon substrate and allow for much faster devices. Moreover, SiGe process is also widely
applied in recent years due to its high performance characteristics. So far, existing millimeter wave receivers which use SiGe or HEMT have the great potential to implement wireless components for 60-GHz applications due to its high unit current gain frequency (fT) [2]-[3].
However, as the fT reaches 80 GHz in 0.13-um bulk CMOS technology, the advanced bulk
CMOS technology becomes the potential choice for implementation of high speed wireless components. The bulk CMOS technology has the great advantages of low cost and high level integration. Recently aggressive downscaling of CMOS device sizes have resulted in significant improvements of their RF performances at a faster rate than SiGe bipolar and GaAs. Based on these features of CMOS process compounded with innovations in circuit design, it makes considerable improvements in wireless systems.
In the next generation wireless communication system, low cost, low power and high-performance 60-GHz transceivers are expected to entail high level of complexity. Even though there are still some restrictions to design the high-performance integrated receiver front-end using CMOS technology, we can use some circuit techniques or system architectures to overcome these limitations. So far, several 60 GHz band receivers and receiver building blocks like LNA and mixer using CMOS technology have been reported [4]-[8]. We would like to roughly describe these circuit techniques and find out a better solution for the proposed receiver architecture. Moreover, some frequency multipliers using HEMT or SiGe process have been reported [9]-[12]. From the authors’ knowledge, there is still not any frequency tripler circuit proposed using CMOS technology. We would also like to introduce the frequency multiplier circuits and their operation principle in the following subsections.
1.2 Reviews on CMOS RF Front-end Receivers
The transceiver is quite a major component in the wireless communication equipment that commonly includes a receiver, a transmitter and a frequency synthesizer. The RF front-end receiver is a major component in the wireless communication equipments which generally consists of several main circuit blocks: a low-noise amplifier (LNA), down-converters, low pass filters and some baseband processing circuits. Conventionally, LNA amplifiers the RF signal received from the antenna with low noise contribution. Down-converters mix the output of LNA and local oscillator (LO) signal generated by frequency synthesizer to the desired intermediate frequency. Filters suppress the unwanted signals or interferences to provide a moderate signal quality for the baseband processing circuits to reach a reasonable performance. Figure 1.1 shows one of the receiver architectures for example.
Since the 60-GHz system has wide operating bandwidth, it is somehow different from narrow band receivers. As a result, some circuit blocks are supposed to have a wideband characteristic or multiple switched circuits used to work at various frequencies, and more than one single carrier frequency is required in the receiver chain for frequency down-conversion. The architecture of the receiver must be selected appropriately to satisfy different system issues, for example complexity, cost and power dissipation. The characteristics of different receiver architectures are discussed in the following subsections.
1.2.1 Receiver Architectures
As RF receiver is evolving continuously, several main architectures have been generalized. The well-know architectures that widely used in recent years are super-heterodyne receiver, homodyne receiver and low-IF receiver [13].
Super-heterodyne receiver
This architecture has been most widely used to gain the better selectivity and extreme sensitivity [14]. The block diagram of a typical double conversion super-heterodyne receiver is shown in Figure 1.2.
The received RF signal from the antenna is filtered first by a RF pre-scale filter and amplified by a LNA. The amplified signal is further discriminated from the image signal by an image rejection filter and applied to the first RF mixer. This down-conversion mixer translated the RF signal to lower intermediate frequency (IF) by mixing with the LO signal, where ωIF=ωRF-ωLO. At the output of the mixer, the desired signal is discriminated from the
other channels by channel select filter and feed to the IF mixer. Through the IF mixer, the signal is down-convert to the more low IF frequency with additional filtering. The same as the RF mixer, the frequency of the IF signal is depended on the LO frequency that supplied to the IF mixer. The main selectivity of desired channel is provided at the same IF independent of the carrier frequency. Since the adjacent channels are filtered, the desired channel is discriminated from them.
The first IF (IF1) frequency must be designed carefully. A high IF1 increase the difference
frequency between image and desired signal and gets better image-rejection performance. However, it requires a channel-selection filter with high Q-factor in this case and is difficult to implement on chip. On the other hand, a low IF1 is difficult to obtain high image rejection but
allows great suppression of nearby interferers. Furthermore, due to the lower frequency, a channel-selection filter only requires lower Q-factors and is much easier to implement. This super-heterodyne receiver can easily overcome the DC-offset problem and has the better performance. The main drawback is its complexity and inadequacy of full integrating a receiver because the high-Q low loss filters are hard to implement using standard CMOS technology.
Homodyne receiver
The homodyne receiver also called direct-conversion receiver or zero-IF receiver which eliminates many off-chip components and promising for single chip receiver, as shown in Figure 1.3. Since the RF signal is directly down-converted to the baseband, the image problem is eliminated because image is one of the sideband about the carrier of the desired signal. However, the lower part of the input spectrum itself is overlapped with the upper part of the spectrum. To avoid loss of information, two sides of input spectrum must be separated into in (I) and quadrature (Q) phase in translate to zero frequency [15]
Besides the image reduction, this architecture shows several advantages: high integration, simplicity of the structure, low cost and low power consumption. Moreover, the possibility of changing the bandwidth of the integrated low-pass filters is another advantage if multi-mode or multi-band applications are of concern [16].
However, the homodyne receiver suffers some drawbacks. The most serious problem is the DC offset impairment due to the LO leakage, which arise from capacitive and substrate coupling [17]-[18]. Due to the limited reverse isolation of mixers and LNAs, especially at high frequency, some of the LO signals may leak to the mixer, LNA, or even antenna. They will reflect to nearby objects and be mixed with the LO signal itself. This could saturate the consequent stages and affect the signal detection process. This problem may become more aggressive if self-mixing varies with time. This effect may be serious in CMOS process utilizing conductive substrate. In additional to DC offset, flicker noise, I/Q mismatch and even order distortions are other issues. I/Q mismatches may corrupt the down-converted signal and the bit error rates rise. Furthermore, since the down-converted signal is a baseband signal, it suffers the more serious flicker noise. These effects may become much more serious especially in CMOS technology [19].
Low-IF receiver
In a low-IF receiver, the RF signal is mixed down to a non-zero low or moderate intermediate frequency, typically a few megahertz. Low-IF receiver has many of the desirable properties which the homodyne receiver has. Moreover, the architecture can avoid the DC offset and flicker noise problems which concerns seriously in homodyne receiver.
The use of a non-zero IF suffers from the image issue again. This image signal can be rejected by quadrature downconversion (complex mixing) and poly-phase filter [20]. However, double-quadrature architecture requires a quadrature generator on RF path and additional two mixers to implement which indicate the more power consumption is required.
Furthermore, the signal bandwidth in low-IF conversion is twice that in homodyne receiver. This requires doubling the analog-to-digital conversion sampling rate and results in more power consumption. The main disadvantage is the large mirror signal suppression requirement. In a zero-IF receiver, the mirror signal is the wanted signal itself. While in the low-IF case, it may be larger than the wanted signal. In addition, the double signal bandwidth in low-IF conversion mandates to double the baseband filter bandwidth, which further increase design complexity and power consumption [21].
1.2.2 Review on 60-GHz CMOS Receivers
As the 60-GHz band system is evolving continuously, several receivers have been published and analyzed. These receivers use different architectures to approach the better performance and high integration [4]-[6]. The followings are representative reviews of the state-of-the-art 60-GHz receivers.
A 60-GHz CMOS Receiver Front-end [4]
The direct-conversion receiver is illustrated in this paper which is implemented using CMOS 0.13-um technology and operates under 1.2-V supply voltage. Figure 1.4 shows the block diagram of the receiver. The circuit consists of a LNA, quadrature mixers, and baseband amplifiers. For testing considerations, the balun is included here to convert the LO input signal from single-ended to differential. The low power consumption and high performance receiver characteristics offer the possibility of using the CMOS technology to implement the 60-GHz system instead of many III-V circuits. However, this type of architecture requires a 60-GHz frequency synthesizer to generate the LO signal, but such a high-frequency frequency synthesizer is difficult to implement and has the poor performance with high power consumption due to high frequency pre-scalar.
Figure 1.4 The block diagram of [4]
A mm-Wave CMOS Heterodyne Receiver with on-Chip LO and Divider [5]
This paper describes a heterodyne receiver using 90-nm CMOS technology and operates under 1.8-V supply voltage. This structure avoids quadrature turn separation and eases the management of interconnect which allows to be integrated with other high-frequency building blocks. Figure 1.5 shows the receiver architecture, where the RF mixer is directly driven by the LO and the IF mixers is driven through a divided by 2 circuit (with fLO=40 GHz).
However, the divide-by-2 circuit must operate at a nominal frequency of 40 GHz and consumes large power consumption with requiring the 40-GHz PLL.
A High Integrated 60-GHz CMOS Front-End Receiver [6]
This paper describes a highly integrated 60-GHz CMOS receiver front-end which is fabricated in a 1P6M 0.13-um standard digital CMOS process and operates under 1.2-V power supply. The circuit consists of a LNA, a quadrature balanced down-conversion mixer, a 30GHz VCO, and a frequency doubler, as shown in Figure 1.6. By using the frequency doubler, only the 29-GHz PLL is required to down convert the 60-GHz signal to 2-GHz IF frequency. This is much easier to implement 29-GHz frequency synthesizer comparing to 60-GHz one when integrating with the receiver. However, the doubler can not provide the differential output signal associated with a mixer and such a circuit still consumes a large amount of power. Moreover, the 60-GHz mixer is down-converted to 2-GHz IF frequency and uses the inductor to peak the signal. This may reduce the noise contribution from the load of the mixer but more inductors are required which occupies large chip area. This architecture requires two PLLs to down-convert the RF signal to baseband and is much more complex with large power consumption.
1.2.3 Review on Building Blocks of CMOS Receiver
Besides the receivers, several building blocks of receiver front-end at frequency of V-band (50~75 GHz) using CMOS technology have been published in recent years. These circuits provide some solutions and techniques to overcome the limitation of the device fT
which is around 80 GHz in 0.13-um CMOS technology. Here, we review these published V-band CMOS circuits to obtain the issues which must be pay more attention when designing the V-band circuits.
A Miniature V-band 3-stage Cascode LNA in 0.13-um CMOS [8]
In this design, the three stages cascaded LNA using 0.13-um CMOS technology with operating under 2.4-V supply voltage is presented. The circuit schematic diagram is shown in Figure 1.7. This architecture uses the cascode device configuration to achieve high gain performance. All of the input, output and inter-stage matching networks are conjugated matched for maximum power transition. However, this structure requires a higher supply voltage and consumes much more power. Moreover, the parasitic capacitance at input stage of a cascode structure causes the signal loss and also increases the noise figure. As a result, the entire noise figure is much larger than conventional common-source architecture.
Single-gate quadrature balanced mixer [6]
This paper presents a quadrature balanced down-converting mixer consisting of two unit single-gate mixers with a 90° branch-line hybrid, as shown in Figure 1.8. The single-gate mixer down converts the RF frequency to 2-GHz IF signal. By taking advantage of the intrinsic device capacitances, the 90° phase shift can be realized by using CPW (coplanar waveguide) transmission lines shorter than λ/8.To reduce the length of the transmission lines, the LO and RF matching networks are co-designed with the 90° branch-line hybrid and gate-bias network. In addition, the insertion loss of the passive component can also be reduced. The on-chip LC components at the drain of CS stage complete the IF matching at 2-GHz. It also filters the LO and RF signal which is not desired at the output. By using the inductor for matching network, the noise contribution from the load can be reduced, but the larger chip area is required. This architecture provides good linearity but the conversion gain is negative which may lead the reduction of the entire receiver gain. Moreover, large amount of transmission lines require large chip area to implement on chip.
Gilbert-cell based mixer [5]
As operating at 60-GHz, the conventional Gilbert-cell mixer which is illustrated in Figure 1.9(a) has the poor performance due to several reasons: the total capacitance at the drain of M1 gives rise to a pole on the order of fT/2, the switching pair M1, M2 must carry the
entire bias current of M3 and the noise contribution from the switching stage may increase.
Moreover, only the small voltage drop across the load resistors is allowed because of supply voltage limitation. These make the diminution of the conversion gain.
To improve these issues, the modified down-conversion mixer using inductive peaking and current injection techniques are implemented, which is shown in Figure 1.9(b). The inductor L1 resonates with the total capacitance seen at the drain of M3 and carries part of the
drain current of M3. Thiscould lead the load resistance to be doubled. Moreover, since M1 and
M2 carry smaller current, they can switch more abruptly. These improvements can abruptly
improve the gain and the noise performance of the mixer.
1.2.4 Review on Frequency Multiplier
In general, active multipliers are configured as doublers which have been demonstrated with good performance [23]. So far, several frequency multipliers using HEMT or SiGe processes have been published and analyzed [9]-[12]. The following reviews some of the techniques of the frequency multipliers.
Frequency doubler using 0.13-um CMOS technology [6]
The schematic of the three-stage frequency doubler is shown in Figure 1.10. It consists of a 30-GHz input driver, a frequency doubler core, and a 60-GHz LO buffer. The Cascode devices form the input and output stages. The inter-stage matching is also applied using reactive components. The frequency doubler is made up by CS amplifier which is biased close to its threshold voltage to efficiently generate the desired second order harmonic signal. A passive network at the drain of the transistor can reject the 30 GHz fundamental while maximizing the second order harmonic at 60 GHz. In additional, it can optimize the power transfer to the output buffer. The input and output of the doubler core circuit are matched to 50 ohm at 30 GHz and 60 GHz separately.
However, this structure has some drawbacks: it requires large power consumption, applying with many transmission lines, and more importantly, the circuit can not generate the differential LO signals to supply to the mixer. These issues may require to be considered when integrating with other building blocks of the receiver circuit.
An optimized 25.5–76.5 GHz pHEMT-based coplanar frequency tripler [12]
This tripler schematic diagram is shown in Figure 1.11, which presents a single-stage MMIC tripler with W-band output frequency. This circuit is based on a double δ-doped 0.15-um gate-length AlGaAs/InGaAs/GaAs PHEMT process. The HEMT device is operated under class AB bias point to efficiently generate the third order harmonic of the input.
This circuit is emphasized on selecting the optimum input and output terminations to get the maximum power transfer at fundamental and third-order harmonic of the input respectively. The terminating impedances are chosen to avoid signal losses and enhance the power at the desired harmonic. A shorter stub with a shunt capacitor is also applied here to eliminate the fundamental signal which is not expected at the output. From many aspects, this approach provides excellent performance but still can not generate the differential signal. Moreover, the circuit is fabricated using pHEMT process and large power consumption is a great concerned. In additional, the integration with other circuits is another issue.
1.3 Motivation
As mentioned above, some published receivers for 60-GHz applications have been developed and surveyed. These receivers require high-frequency frequency synthesizers to generate appropriate LO signal to down-convert the RF frequency to baseband. This may lead the receiver performance become poor because the frequency synthesizer performance degrades violently when operating at higher frequency. Moreover, the tuning range of the VCO also degrades due to smaller inductor values. This tuning range may not sufficient to cover the entire 57~64 GHz band and requires more than one PLL to cover the whole frequency band. Based on the drawbacks and design considerations of receiver architecture mentioned above, a wideband direct-conversion topology integrated with a frequency tripler has been proposed in this thesis. The design is realized by using TSMC 0.13-um CMOS technology under the standard supply voltage of 1.2 V. It attempts to design a low cost, low power and wide bandwidth circuit for 60-GHz system applications. This circuit also has great potential to be integrated with frequency synthesizer and baseband circuits.
1.4 Thesis Organization
Chapter 2 presents a novel frequency tripler circuit which can be applied in 60-GHz receiver front-end. The detail design considerations are also introduced here with its simulation results. In Chapter 3, the receiver architecture and its building blocks are presented. It includes a LNA, a down-conversion mixer and output buffers. The basic theory and simulation results of each building block are also illustrated here. Chapter 4 contains experimental results and discussions. Finally, conclusions and future work are presented in Chapter 5.
Chapter 2
A High-Frequency Frequency Multiplier
A novel configuration of balanced frequency tripler using standard 0.13-um CMOS technology is proposed. In this chapter, the circuit design consideration and theoretical analysis of frequency tripler are introduced together with the simulation results. The simulation results show that the circuit has great potential to apply in the high-frequency system such as 60-GHz receiver front-end.
2.1 Design of the Frequency Tripler
A frequency tripler based on FET type is very attractive for being integrated with other elements of a monolithic transceiver. In this design, by importing only 20-GHz input signal, the frequency tripler can successfully generate sufficient amplitude of the differential 60-GHz signal to be as LO signal of the mixer.
2.1.1 Operational Principle
The analysis of the frequency multiplier is usually a combination of gate bias and fundamental RF input levels for optimum generation of a desired harmonic signal [24]. To decide the bias point of the FET device, the drain current dependence model illustrated by Fudem and Niehenke is introduced here [25].
The optimal bias point is opted midway between pinch-off and the onset of forward condition which is consistent with a Class-A amplifier. When operating on this bias point, a large amplitude AC signal is required to over-drive the device both into pinch-off and forward conduction every cycle. The resulting drain current waveform is then severally clipped at both
ends. This clipped waveform successfully results the harmonics. If the ac signal becomes larger, the output waveform can be approximately considered as square-wave results. The Fourier transformation associated with a perfect square-wave is given by:
n n 2 ( 1) I , I 0 , n peak I n odd n n even
π
− = =As can be seen, for the perfect square-wave, only the odd order harmonic is generated and even order term which we do not desired can be eliminated. For a square wave, if n=3 for the tripler design, the output amplitude of I3 can be generated approximately 0.212Ipeak. This
mode of operation obtains superior third-order conversion than biasing the device near the pinch-off which is more commonly used.
Besides biasing between pinch-off and the onset of forward condition, there is still another bias point that can obtain the same optimal value of I3. This solution can be obtained
by generating rectangular output waveform with a duty cycle of 1/6 rather than square one. Unlike the square-wave considered previously, although rectangular-wave does obtain the same conversion of the odd order harmonic, it also contains significant even order harmonics, especially second order harmonic which we do not desire.
The most significant benefit of choosing a 1/6 duty cycle in bias point design is the DC power reduction. In this mode, the device always operating in the cut-off region and rarely consumes DC power until AC signal is supplied. Furthermore, the fundamental content under this operation is less than that of square-wave, thus the fundamental rejection can be improved. Nevertheless, there are several serious drawbacks in this approach: poor even order harmonic rejection, high AC drive level of the fundamental input, and the breakdown issue due to large drive power.
2.1.2 Design Considerations
There are several limitations that need to be considered when implementing the frequency tripler which applies in 60-GHz receiver front-end. Especially, the design is implemented by using 0.13-um CMOS technology with 1.2-V supply voltage.
From the analysis that mentioned above, two optimal bias conditions are proposed. One is biasing in the middle between cut-off and forward conduction region, which generate square wave in the output. The other operation point is biasing at well below the cut-off region and generate 1/6 duty cycle rectangular wave with large AC signal. If we want to generate a 60-GHz LO signal, we must implement a 20-GHz frequency synthesizer or VCO to provide the sufficient input AC signal level for the tripler circuit. However, in 0.13-um CMOS technology, it is hard to generate such a large output swing signal due to low supply voltage. Beside, the FET device model of the CMOS process is not quite accurate when biasing well below cut-off region and the performance of the circuit can not be guaranteed. Hence, in the CMOS technology, the bias point of the device is better to be opted midway between pinch-off and onset of forward condition which is consistent with a Class-A amplifier.
Nevertheless, in practical case, the output waveform can not produce the perfect square-wave. Therefore, the undesired even order harmonics are no longer be zero, especially the second order harmonic is the extreme one. In the design of the frequency multiplier, harmonic rejection is also an import demand. The most popular method to filter out these undesired outputs is using the inductor peaking approach. By choosing appropriate value of LC tank, the band pass filter characteristic can be obtained. Another popular way is using the transmission lines with length of particular wavelength ratio to filter out the undesired signal. However, this method requires large chip area to implement the transmission lines.
2.1.3 Circuit Realization
The circuit scheme of the proposed two-stage CMOS frequency tripler is shown in Figure 2.1. It consists of a tripler core circuit and an output buffer stage with a fully differential configuration. The tripler function is made by MOS M1 and M2. As the
fundamental signal (20 GHz) is applied to the gate terminals of M1 and M2, the third order
harmonic signal (60 GHz) can be generated due to the output waveform distortion that mentioned in previous subsection. The inductors L1 and L2 are used to resonant with the
parasitic capacitance at the third harmonic frequency of the input signal and the desired output signal can be extracted. Moreover, due to the band pass characteristic of the LC tank, the undesired harmonic signals will be filtered to some extent.
The M3 and M4 perform as CS amplifiers and the load inductors L3 and L4 are also
resonated at the third harmonic frequency. By using additional gain stage, not only can the desired signal be enhanced further but also the other undesired harmonics can be suppressed. A resistance R2 is used to select the dc operation point of the mixer LO-port and can save a dc
bias pin. In additional, to provide the stable dc bias, a bypass capacitance C5 is also added.
Because the even harmonic signals at the output nodes are common-mode characteristic, appropriate value of R5 can be designed to eliminate the undesired even order
harmonic signals. The simulation result of the 2nd and 4th harmonic rejection improvement due to R5 is shown in Figure 2.2
To further improve the performances, the source inductor LS is applied to enhance the
even order harmonics at the source terminal of M1,2 to mix with the input fundamental signal.
Thus, the third harmonic signals at the output nodes can be enhanced, as shown in Figure 2.3. When even-order harmonics are involved, the LS can be seen as source degeneration inductor
and a cause of even order signal gain reduction, as illustrated in Figure 2.4. Further improvement of the harmonic rejection ratio (HRR) is expected which shows in Figure 2.5. Although larger inductance value gets better performance, but it is not easy to implement such a large inductor and it requires large area. So we choose the appropriate value of source inductor here. The detail device parameters of proposed frequency tripler are list in Table 2.1.
Table 2.1 Detail parameters of proposed frequency tripler
M1,2 18 um / 0.13 um R1,2 5 kohm
M3,4 9.6 um / 0.13 um R3,4 5 kohm
L1,2 w=3 r=37 nr=1, CENT-Tap R5 8 ohm
L3,4 Tline 230 pH R6 200 ohm
LS1 Tline 200 pH C1,2 MIM 30um x 30um
VB1 0.65 V C3,4 MIM 20um x 20um
Figure 2.2 Simulation results of even-order HRR due to R5
Figure 2.4 The simulation results of even-order harmonic output powers versus Ls
2.1.4 Simulation Results of Frequency Tripler
The performance of the proposed frequency tripler is simulated under the input power of 4 dBm. To count the loading effect of the mixer, the circuit is integrated with the mixer and obtains the inter-stage performances. Figure 2.6 shows the simulated relative output power of the frequency tripler between 56~65 GHz. In Figure 2.7, the HRR over the 57~64 GHz are calculated. It shows that the HRR can achieve better than 24 dB in each case. Since the output impedance is not 50-ohm, the simulation results taken as affirming the relative harmonic amplitude. The accurate output swing waveform at 60-GHz can be obtain by using transient analysis, as shown in Figure 2.8 to Figure 2.10. As can be shown, the output swing of the frequency tripler is between 125 mV and 270 mV. At last, the third-harmonic output power versus input power of the fundamental signal is illustrated in Figure 2.11. Obviously, the third-harmonic output power achieves saturate when input power is larger than 4 dB. Hence, we choose the 20-GHz input signal as 4 dBm here which is available to be generated by using 20-GHz PLL or VCO under 0.13-um CMOS process.
To obtain the phase noise contribution due to the proposed circuit, an additional 20-GHz VCO has been designed and connected to the proposed frequency tripler. Figure 2.12 shows the simulated phase noise performance of the 20-GHz VCO and the output signal of the frequency tripler circuit when VCO is connected as the fundamental input signal. As can be seen, the phase noise increases 11.8 dBc/Hz at 1 MHz offset before and after the frequency tripler circuit. Ideally, tripling the signal will cause the 9.54 dBc/Hz phase noise enhancement due to frequency transition. Hence, the phase noise contribution due to the proposed circuit itself is about 11.8 – 9.54 = 2.26 dBc/Hz.
Figure 2.6 The simulation results of the relative output power
Figure 2.8 The simulation results of the output waveform at 57 GHz
Figure 2.9 The simulation results of the output waveform at 60 GHz
Figure 2.11 The output power versus fundament frequency input power at 20-GHz input
2.2 Comparison with Previous Works
In the following, the simulation results are compared with the previous works. The main results of the frequency multiplier are including input power level, output swing, HRR and power consumption. So far, from the author’s knowledge, there is still not any frequency tripler circuit implemented using CMOS technology. We can only compare with the published works which are fabricated using pHEMT or SiGe technology. The simulation results summary of the proposed CMOS frequency tripler and the comparison with previous works are shown in Table 2.2 and Table 2.3, respectively.
As can be see, although we use the CMOS technology, the proposed frequency tripler performs the high output swing and the excellent harmonic rejection ability. A larger HRR can diminish the harmonic effects that influence the mixer performance. Since the 20-GHz VCO is available to reach the 4-dBm output power with 1.2-V power supply, this input power is quite make sense while simulating. From simulation results, the output voltage swing of the frequency tripler is larger than 125 mV and is enough to turn on and turn off the MOS device in the mixer stage. To deserve to be mentioned, the power consumption is much smaller than others and has great potential to implement the low power front-end circuits.
Table 2.2 Post simulation summary of the proposed frequency tripler
Technology 0.13-um CMOS 1P8M
Center Frequency 60 GHz Input Power (20 GHz) 4 dBm Output Swing (60 GHz) 270 mV HRR 1st 31 dB HRR 2nd 31 dB HRR 4th 47 dB DC Power Dissipation 8.5 mW Supply Voltage 1.2 V
Table 2.3 Comparison with published frequency multiplier
This work [9] [11] [26]
Technology (um) 0.13 CMOS 0.15 pHEMT 0.15 pHEMT 0.25 pHEMT*
Sub-harmonic Number 3 3 3 3 Center Frequency (GHz) 60 36 76.5 76.5 Input Power (dBm) 4 9 8.5 17 Output Power (dBm) **270 mV -0.4 4.2 0 Conversion Loss (dB) 4.8 9.4 4.3 17 HRR 1st (dB) 31 22 16 24 HRR 2nd (dB) 31 22.1 32 19 HRR 4th (dB) 47 N/A 13 N/A
Power Consumption (mW) 8.5 39.2 N/A 50
Supply Voltage 1.2 V 1.5 V 2.5 V 2 V
* Dual recess process ** only output swing can be obtained
Chapter 3
RF Front-End Circuits
First of all, proposed receiver architecture is introduced together with its building blocks. In addition to the frequency tripler, the receiver requires a low noise amplifier and a down-conversion mixer. The frequency tripler is implemented by that mentioned in Chapter 2 and the other building blocks will be designed and simulated in the following subsections. Subsequently, a complete 60 GHz direct-conversion receiver which is integrated by these building blocks is simulated and the simulation results are presented.
3.1 Receiver Architecture and Design Considerations
Receiver Architecture
Figure 3.1 shows the block diagram of the proposed receiver. The circuit consists of a LNA, down-conversion mixers, output buffers and a frequency tripler. First of all, the RF input signal is amplified by a LNA which has low noise and sufficient gain to enhance the signal to noise ratio (SNR). The down-conversion mixer following LNA provides extra gain and down convert the RF signal to IF by mixing with proper LO signals. To obtain the desired LO signal, the 20-GHz differential input signal is supplied and through a frequency tripler on chip, the signal is multiplied to 60 GHz. Because of the poor properties of active and passive device characteristics at high frequency, this approach can design the high performance frequency synthesizer at relative low frequency. In other words, by supplying LO signals using low frequency PLL can promote the circuit to have better phase noise performance and reduce the power consumption of high frequency pre-scalar. To obtain the output performance of the receiver, the output buffer is exploited here for measurement consideration.
Figure 3.1 The proposed 60-GHz direct-conversion receiver architecture
Receiver Specifications
So far, there is still not a standard specification for 60 GHz band wireless communication system. From the system requirement, we could specify the receiver issues as follows:
The FCC made the 59~64 GHz unlicensed band available for use at first and extended it to 57~64 GHz subsequently. Both of the bands are widely designed and well applied in different countries. The 3-dB bandwidth covers from 57 to 64 GHz band are a better solution to conform each specification. For the sensitivity which can be calculated from IEEE 802.16 [6], the noise figure requirement of the receiver could be obtained. We note that the sensitivity is about -65 dBm and the channel bandwidth of 2 GHz drives to a noise figure of 12 dB.
Design Consideration of Transmission Lines
Since the fT of nMOS is about 80 GHz in 0.13-um CMOS technology, the circuits would
suffer from poor performances unless passive resonant devices are utilized in the design. Even though spiral inductors have better quality factors over tens of gigahertz, the large device occupied area will cause circuit integration even more difficult. In addition, the substrate eddy current at millimeter-wave will degrade the overall performance of the receiver. The receiver at the 60 GHz band usually claims for wide bandwidth in virtue of system requirement. Although high Q inductors get up to high gain performance, the bandwidth requirement may
not be achieved at the same time. More significantly, since silicon substrate is neither a perfect conductor nor good insulator, it would cause some current flow through the substrate. Magnetic coupling to the substrate significantly influences the inductance value at these frequencies and requires detailed knowledge of the substrate profile to develop an accuracy simulation models.
In contrast to spiral inductors, transmission lines (Tlines) substantially confine the electric/magnetic fields and hence better lend themselves to model. Coplanar lines in CMOS technology have already been characterized for frequency up to 50 GHz [5]. However, this structure still occupies large area and is not easy to integration a system. In this work, incorporates microstrip structures as they interact negligibly with the substrate and can be modeled more accurately. Meander configuration is applied to the circuit in order to mitigate the integration perplexity and exorbitant area usage, shown in Figure 3.2. The signal line is implemented by metal 8 while metal 1 under the signal line is used for being as ground plane. The ground plane can fully confine the electric and magnetic fields and eliminate the substrate induced losses. Comparing to coplanar architecture, this configuration saves the Tlines area even more and could alleviate routing difficulties when integrate the circuits.
By using the electromagnetic field simulator HFSS, the s-parameter around 60GHz could be simulated to compute the equivalent inductance value LS and interior resistance RS. The
meander space S may be decided by layout and magnetic coupling considerations. Although small S can reduce the geometrical length, the mutual coupling between lines will become larger. In order to make sure how spacing S effect the performance, a simple structure is established as shown in Figure 3.3. Figure 3.4 plots the line characteristics as S varies from 5 um to 35 um. As expected, LS and Q increase to some extent when S becomes larger. As this
value increase to about treble the line width (about 15 um), the Quality factor reach to relatively constant and would not strongly influence the performance. This value is also acceptable for space consideration with other Tlines.
For a given meander length S=15 um, there are two parameters that may affect the inductance value (LS) and quality factor (Q): total Tline length L and the width W. Figure 3.5
plots the equivalent inductance and quality factor as W varies from 3 um to 12 um while maintaining fixed total length at 400 um. It can clearly be seen that LS decreases and Q
increases as the width becomes larger. This is due to the fact that inductance is mainly determined by the outer magnetic flux generating from the conductor. Consequently, the self inductance increases when the width diminishes. Moreover, the resistance is inverse proportional to the width and quality factor can be improved as width become larger. Even though wider width can obtain better quality factor, it requires longer length to get the desired inductance and cause more parasitic capacitance. From the simulation results, the characteristic diminishing returns as W exceeds 5 um. Thus this value of W is chosen in this work. We can obtain the desired inductance by selecting the appropriate value of length.
Figure 3.2 Geometrical lengths shortening by using Meander configuration
Figure 3.3 The test pattern of meander configuration
Figure 3.4 Inductance and quality factor variation as a function of S
![Figure 1.8 Simplified circuit diagram of the single-gate quadrature balance mixer in [6]](https://thumb-ap.123doks.com/thumbv2/9libinfo/7494938.115742/24.892.187.757.517.1098/figure-simplified-circuit-diagram-single-quadrature-balance-mixer.webp)
