BSIM-4 C-V Model Calibration and Simulation for 65nm 4-port RF MOSFET

As mentioned previously, C-V model in BSIM-4 includes gate capacitance model and junction diode capacitance model [17]. The former one incorporates coupling capacitances originated from the gate electrode of MOSFETs and the latter one is contributed from S/D to body junction depletion or diffusion capacitances. For logic circuits, the gate delay of a CMOS inverter is determined by both categories of capacitance, i.e. gate capacitances and junction capacitances. As for RF and analog circuits, the cut-off frequency fT serving as the fundamental limitation of operation frequency is determined by gate capacitance, rather than junction capacitance [25]. In this thesis focusing on RF MOSFETs design and modeling, gate capacitance model is the key to determine the simulation accuracy for RF circuits design.

In our recent work, an extensive research effort has been focusing on the analysis of parasitic gate capacitances in nanoscale multi-finger MOSFETs [26, 27]. A comprehensive analysis method has been established for parasitic gate capacitances extraction and modeling, and for accurate simulation of fT and RF circuit performance [26, 27]. The important insight and conclusion achieved from our work can be summarized as two key points. The first one is that the parasitic capacitances can be classified as extrinsic parasitic and intrinsic parasitic capacitance. The former is contributed from pads, interconnection lines, and lossy substrate, and can be extracted and removed using improved open deembedding method, i.e. openM1 deembedding [27]. The latter consists of gate related fringing capacitances, such as gate sidewall fringing capacitance (C_of) and finger end fringing capacitance (Cf(poly-end)) and cannot be removed using all of the existing open deembedding methods [27]. The second key point is that both extrinsic and intrinsic parasitic capacitances are not scalable with devices scaling and the impact on fT and other high frequency performance increases dramatically in nanoscale

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devices[26, 27].

In BSIM-4, the gate capacitance model is composed of three components, namely intrinsic, overlap, and fringing capacitances. This gate capacitance is originated from the version of BSIM-3.3.2 with some minor revisions and three options are available for BSIM-4, which can be matched with the options from BSIM-3.3.2, shown in Table 3.9.

Table 3.9 BSIM-4 capacitance model pptions and matching with BSIM-3.3.2 options BSIM-4 capacitance model Matched options in BSIM-3.3.2

Options Features Intrinsic capMod Overlap/fringing capMod

capMod=0 Simple and piece-wise model 0 0

capMod=1 Single-equation model 2 2

capMod=2 Default of BSIM-4

Single-equation and charge- thickness model

3 2

Before going through the details of three capacitance components, the geometrical parameters of MOSFETs have to be defined to appropriately separate the three components and then simulate each component of capacitance with sufficient accuracy. The geometric parameters include drawn dimensions (length and width) on layout and intrinsic channel dimensions for I-V and C-V modeling. The intrinsic dimensions are denoted as effective channel length and effective channel width. Ideally, a single set of effective channel length and channel width can fit both I-V and C-V models for the same device. However, in practice, different sets of parameters are generally required for I-V and C-V models to achieve respective fitting to the measured I-V and C-V characteristics.

For I-V model, the effective channel length Leff and effective channel widths, denoted as W_eff or W_eff ‗ are defined as :

eff drawn 2

L L  XL dL (3.70)

LLN LWN LLN LWN

LL LW LWL

dL LINT

L W L W

    (3.71)

eff drawn 2

W W  XW dW (3.72)

 

' _{gsteff s bseff s}

dW dW DWG V DWB  V   (3.73)

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or

' 2 '

eff drawn

W W  XW dW (3.74) ' WW_WWN WL_{WWN WLN}WWL_LWN

dW WINT

W L L W

    (3.75)

where XL and XW represent the offset of gate length and channel width from the drawn dimensions after lithography and etching process. dL represent channel length variation due to S/D lateral diffusion under the gate and dW‘ is the channel width variation, maybe from bird‘s beak encroachment for LOCOS or divot and trench top corner rounding for STI. LINT and WINT represent the components of dL and dW‘, respectively, which are extracted from conventional I-V method [28]. Note that dW associated with W_eff incorporates gate and body biases dependence with fitting parameters DWG and DWB, respectively.

As for C-V model, the effective channel length and effective channel width, denoted as Lactive

and W_active are defined as :

active drawn 2

L L XL dL (3.76)

L L N L W N L L N L W N

L L C L W C L W L C d L D L C

L W L W

    (3.77)

drawn 2

active

W W XW dW

 NF   (3.78)

WLN WWN WLN WWN

WLC WWC WWLC

dW DWC

L W L W

    (3.79)

where DLC and DWC are different from LINT and WINT in I-V model and can be bias-dependent variables. It means that Leff and Weff used in I-V model can be different from L_active and W_active used in C-V model for the same device with specified dimensions.

Theoretically, Leff and Lactive represent the effective channel lengths defined by the metallurgical junctions of S/D lateral diffusion to body. However, the graded S/D junction profile generated by lightly doped S/D (LDD) or S/D extension (SDE) regions makes the effective channel length a strongly bias-dependent parameter and introduces a dramatic difficult to the determination of

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Leff and Lactive from electrical measurement, either I-V or C-V methods. In our previous work, a decoupled C-V method was developed for an accurate extraction of effective channel length and source-and-drain series resistance, simultaneously [29]. The extracted source-and-drain series resistance associated with LDD or DD profiles reveals a strong bias dependence [29].

In BSIM-4, L_active is measured and extracted under flatband voltage built at the gate to S/D interface. Additional parameters such as LLC, LWC, LWLC for dL and WLC, WWC, WWLC for dW are introduced as fitting parameters to allow an optimized fitting to devices with various dimensions. Ideally, Lactive and Wactive can precisely define the intrinsic channel region contributing intrinsic gate capacitance. Furthermore, dL defines the length of S/D lateral diffusion to gate overlap region, which contributes the overalp capacitance. Regarding the fringing capacitance, it is a kind of intrinsic parasitic capacitance and cannot be scalable with the channel length scaling. The key parameters governing the fringing capacitance is the gate thickness, gate oxide thickness, and gate to contact spacing, etc [30]. The smaller gate to contact space and the thinner gate oxide will lead to larger fringing capacitance. As for multi-finger MOSFETs widely used in RF circuits, the narrower channel width and simultaneous increase of finger number will increase finger-end fringing capacitance [27].

Table 3.10 lists the geometrical parameters extracted from UN65 multi-finger MOSFETs for I-V and C-V simulation, respectively. Note that both Lactive and Leff are shorter than Ldrawn due to significant CD loss from patterning and etching, i.e. XL (-20nm). Furthermore L_active for C-V simulation is smaller than half that of Leff for I-V simulation, due to significantly larger dL from DLC >> LINT. The ratio of L_active and dL can be used to predict the weighting factor of the intrinsic (channel) capacitance and overlap capacitance in the total gate capacitance. Note that dL is not scalable with length scaling and the overlap capacitance will dominate higher ratio with device scaling.

Table 3.10 Geometrical parameters extracted from UN65 multi-finger MOSFET for I-V and C-V simulation

104 Geometrical parameters for I-V simulation

W_F (m) N_F W_drawn (m) L_drawn(m) XL (m) LINT (m) LL LW LWL LLN LWN dL (m) L_eff (m) 2.0E-06 32 6.40E-05 6.0E-08 -2.00E-08 -4.0E-09 3.725E-16 -5.00E-16 1.577E-23 1 1 2.205E-09 3.559E-08

Geometrical parameters for C-V simulation

W_F (m) N_F W_drawn (m) L_drawn(m) XL (m) DLC (m) LLC LWC LWLC LLN LWN dL (m) L_active (m) 2.0E-06 32 6.40E-05 6.0E-08 -2.00E-08 1.237E-08 -5.00E-17 -1.14E-15 -5.00E-23 1 1 1.151E-08 1.699E-08

Besides the effective channel length and effective channel width, gate oxide thickness is one more fundamental parameter for accurate C-V simulation. In BSIM-4, there are three kinds of gate oxide thickness, such as physical gate oxide thickness (TOXP), electrical gate oxide thickness (TOXE), and nominal gate oxide thickness (TOXM). TOXP is the physical thickness of the gate oxide formed on the Si substrate, which is free from poly gate depletion and inversion layer quantization effects. TOXE is the electrical equivalent thickness of the gate oxide at active state, i.e. strong inversion in which additional thicknesses are contributed from the quantum well of inversion layer (W_inv) and poly gate depletion (X_poly). Note that both W_inv and Xpoly are not scalable with TOXP reduction and their influence increases with device scaling with thinner TOXP. The gate capacitance under strong inversion, represented by kox 0/TOXE is used to calculate the inversion carrier density, which contributes to drain current. TOXM is the gate oxide thickness at which the parameter is extracted as a nominal value and is used in VT model to allow k1ox and k2ox be tunable with TOXM.

Considering quantum well thickness effect associated with the inversion layer, charge thickness model (CTM) was proposed and implemented as follows to calculate effective oxide capacitance C_oxeff from which the inversion carriers and gate charge density can be accurately calculated to simulate the intrinsic channel (gate) capacitance.

According to series capacitance principle, C_oxeff is given by

oxp cen oxeff

oxp cen

C C

C C C

 

 (3.80)

si cen

DC

C X

  (3.81)

where the inversion charge layer thickness XDC can be formulated as

105

Vgst,eff is the effective gate over-drive to realized a unified formula for calculating inversion charge density from weak inversion (subthreshold) region to strong inversion region, as given by (3.80)~(3.82). Note that poly gate depletion effect has been incorporated by the term with NDEP for poly gate doping concentration.

 

Then, the inversion charge density can be calculated by

( , )

inv oxeff gsteff CV eff

q  C  V _ (3.86) where_is employed to simulate body charge thickness by including the deviation of surface potential_Sfrom 2_B, i.e. the threshold value for strong inversion

S 2 B

note that V_{gsteff CV,} is the effective gate-overdrive created for C-V simulation, with major difference from V_gsteffin the terms m and* Voff', given by

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tan (1 )

* 0.5 MINVCV

m 

   (3.90)

'

eff

VOFFCVL Voff VOFFCV

  L (3.91) To ensure charge conservation, terminal charges instead of terminal voltages are used as the state variables. The terminal charges associated with gate, body, source, and drain are formulated as follows. The gate charge Q is composed of the mirror charges from the channel _g charge , accumulation charge Q_acc, and body depletion charge Q_sub.

( )

g b s d

Q  Q Q Q (3.92)

b acc sub

Q Q Q (3.93)

inv s d

Q Q Q (3.94) The total charge is calculated by integrating the charge along the channel as follows. The threshold voltage along the channel is modified due to non-uniform body charge given by (3.95)

( ) (0) ( 1)

th th bulk y

V y V  A  V (3.95)

0^Lactive ( ) 0^Lactive( )

c s d active c active oxe gt bulk y

Q Q Q W



q y dy  W C



V A V dy (3.96)

0^Lactive ( ) 0^Lactive( )

g active g active oxe gt th FB s y

Q W



q y dy W C



V V V   V dy (3.97)

0^Lactive ( ) 0^Lactive( ( 1) )

b active b active oxe th FB s bulk y

Q W



q y dy W C



V V    A  V dy (3.98)

For MOSFETs operating in saturation region, the inversion charges Qinv are partitioned intoQ and_s Q according to the partitioning ratios XPART, such as XPART=1, 0.5, and 0 _d forQ_d /Q =0/100, 50/50, and 40/60. _s

For capMod=2, i.e. the default capacitance model with single equation and charge thickness model (CTM), the inversion channel charges are partitioned as follows

XPART=0.5 (50/50)

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gsteff CV gsteff CV bulk cveff CV

active active oxeff s

bulk cveff CV

gsteff CV bulk cveff CV bulk cveff CV

gsteff CV eff

gsteff CV gsteff CV bulk cveff CV

active active oxeff d

bulk cveff CV

gsteff CV bulk cveff CV bulk cveff CV

gsteff CV eff

s gsteff CV eff bulk cveff CV

bulk cveff CV

d gsteff CV eff bulk cveff CV

bulk cveff CV

As mentioned previously, the intrinsic capacitance is represented by the effective channel length, L_active, which is much shorter than the gate length after patterning and etching, i.e.

Ldrawn-XL, and the remaining portion is defined as overlap region, which contributes so called overlap capacitances. Due to the fact that the overlap region is not scalable with the gate length scaling, the overlap capacitance dominates an increasing rate of the total gate capacitance with

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device scaling and becomes a key factor governing the gate delay and cut-off frequency for high speed and high frequency design. Accurate overlap capacitance model is essential for accurate simulation of AC and RF performance. However, the critical sensitivity of the overlap region to the S/D lateral diffusion profile from LDD or SDE (S/D extension) and spacer variation complicates the bias dependence and makes the overlap capacitance modelling a challenging work. In BSIM-4, the overlap capacitance model was implemented with a single equation for both accumulation and depletion condition by using smoothing parameters, such as V_gs,overlap and V_gd,overlap for source and drain sides. Note that the intrinsic capacitances under active mode are non-reciprocal, i.e. Cgs≠Csg and Cgd≠Cdg but the overlap capacitances are considered reciprocal, i.e. C_gs,overlap=C_sg,overlap and C_gd,overlap=C_dg,overlap. The overlap capacitance model implemented for capMod2 is described as follows.

Source side overlap capacitance model with bias dependence is given by

, , Drain side overlap capacitance model with bias dependence is given by

, ,

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where CGSO and CGDO represent bias independent overlap capacitance from heavily doped S/D . GSL and CGDL are bias dependent overlap capacitance from LDD or SDE region.

CKAPPAS and CKAPPAD are bias dependent fitting parameters associated with the terms GSL and GDL, respectively.

The gate overlap charge can be calculated according to charge conservation law given by

 

, , , ( )

overlap g overlap d overlap s active gb

Q   Q Q  CGBO L V (3.110) where CGBO is a model parameter, which represents the gate-to-body overlap capacitance per unit channel length.

Intrinsic channel capacitance and overlap capacitance constitute the intrinsic gate capacitance and another component of gate related capacitance, so called fringing capacitance is a kind of parasitic capacitance. Note that this kind of parasitic capacitance cannot be removed using existing deembedding and is defined as intrinsic parasitic capacitance to be distinguished from the conventionally known extrinsic parasitic capacitance from pads, interconnection lines, and substrate [26]. As mentioned previously, the gate related fringing capacitances are composed of two major components, such as gate sidewall fringing capacitance (C_of) and finger end fringing capacitance (Cf(poly-end)). In our recent work, an extensive study has been done based on 3-dimensional (3-D) interconnection simulation (Raphael) and devised deembedding method, Cof and Cf(poly-end) can be precisely extracted for an accurate determination of intrinsic gate capacitance, inversion carriers density, effective mobility, and intrinsic cut-off frequency f_T [26]. Note that the gate sidewall fringing capacitance is so called outer fringing capacitance (Cof) and is independent of biases. On the other hand, inner fringing capacitance (C_if) is a component of intrinsic channel capacitance and reveals a strong bias dependence. The effect of Cif is significant in weak inversion region but becomes negligible in strong inversion region. In our previous work, a 3-D integral model has been developed to accurately simulate Cof, which are composed of gate-to-S/D diffusion (Cg,Diff ) and gate-to-contact (Cg,CT) [30]. This 3-D integral

110

model can precisely predict the dependence of device layout and geometry, such as gate length, gate oxide thickness, gate thickness, gate to contact space, and contact dimensions, etc [27].

In BSIM-4, the outer fringing capacitance model just follows a simple sidewall capacitance formula derived based on a conformal mapping method [31], as given by

7 where CF represent the outer fringing capacitance per unit width. This simplified formula suggests the larger CF associated with thinner TOXE but cannot predict the dependence of layout and geometrical parameters.

In summary, the capacitances associated with MOSFETs are classified into 4 categories, such as extrinsic parasitic capacitance, fringing capacitances, overlap capacitance, and intrinsic capacitance, as shown in Fig. 3.74. The extrinsic parasitic capacitance is contributed from pads, interconnection lines, and substrate and can be removed by an open deembedding. Note that openM1 deembedding is essential to achieving a clean deembedding and approaching the intrinsic MOSFET. However, all of the DUTs with various dimensions require their dedicated openM1 deembedding structures and it leads to much larger chip area. In this thesis, due to limited chip area, openM3 deembedding is a compromised solution to cope with the limitation.

MOSFET

Fig. 3.74 MOSFET capacitances classified into four categories for C-V modeling : extrinsic

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parasitic capacitance, fringing capacitance, overlap capacitance, and intrinsic capacitance

Fig. 3.75 illustrates the small signal equivalent circuit for a standard MOSFET after open deembedding. Note that the overlap and fringing capacitances are lumped together with intrinsic capacitance and cannot be removed or extracted by open deembedding. A feasible approach is to turn off the active channel under cold device condition, i.e. Vg=Vd=Vs=Vb=0, which is equivalent to turn off the intrinsic capacitance, and then to extract the overlap and fringing capacitances from the measured Y-parameters. According to the 4-port Y-parameters under cold device condition, 4 components of gate related capacitances can be extracted as follows :

Im( 11)

gg

C Y

  (3.112) Im( 12)

gs

C Y

   (3.113) Im( 13)

gd

C Y

   (3.114) Im( 14)

gb

C Y

   (3.115)

13

11 12 Im( ) 14

Im( ) Im( ) Im( )

g gg gs gd gb

Y

Y Y Y

C_ C C C C

   

        (3.116)

13 12

,

Im( ) Im( )

gd ext gd gs

Y Y

C C C

 

     (3.117)

1 2

gb gb gb

C C C (3.118) For cold device under ideal condition, the 4 components of gate related capacitances of intrinsic

MOSFETs should follow conservation law, i.e. Cgg-(Cgs+Cgd+Cgb)=0 and symmetric S/D feature, i.e. C_gs=C_gd. However, the 4-port Y-parameters measured from practical device, even after open deembedding reveals an offset between Cgg and Cgs+Cgd+Cgb, as shown in Fig.

3.76(a) and represented by Cg given by (3.116), and also difference between Cgs and Cgd

denoted as C_gd,ext given by (48) and shown in Fig. 3.76(b). Both C_g and C_gd,ext are considered parasitic capacitances from inter-metal coupling, which cannot be removed by using openM3

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deembedding. Regarding cold device at turn-off state, the channel is out of inversion carriers and the gate to body is free from shielding effect. As a result, gate to body capacitance, C_gb cannot be negligible. As shown in Fig. 3.76(c), the measured Cgb versus frequency indicates a frequency independent component, C_gb1 in higher frequency region, above 25GHz and a frequency dependent component, Cgb2 in lower frequency region, below 25GHz. As shown in Fig. 3.75, the frequency independent term is implemented as C_gb1, contributed from inter-metal coupling between the gate and body contacts. The frequency dependent component is deployed by a parallel RC, i.e. R_gb//C_gb2. in which R_gb is one of body resistances.

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Fig. 3.75 Small signal equivalent circuit of a standard MOSFET after open deembedding

0 5 10 15 20 25 30 35 40

114

0 5 10 15 20 25 30 35 40

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

C gb (fF)

(c)

Freq-dependent, C_gb2

Freq-independent C_gb1

Freq (GHz)

Cold device Vg=Vd=Vs=Vb=0 C_gb= -Im(Y₁₄)/

Fig. 3.76 The gate related capacitances extracted from 4-port Y-parameters after openM3 deembedding on 4-port RF MOSFET (a) Cgg and Cgs+Cgd+Cgb (b) Cgs and Cgd (c)

Cgb=Cgb1+Cgb2

For cold device under turn-off condition, Cgs and Cgd are contributed from overlap and fringing capacitances and the parameters associated with the overlap and fringing capacitances model can be extracted step by step, according to the flow as shown in Fig. 3.78. First, the fringing capacitance C_of can be determined from Raphael simulation based on our previous work and 65nm device layout/geometrical parameters [30]. The fringing capacitance model parameter, CF can be adjusted according to Cof from Raphael simulation, shown in Fig. 3.77.

Then, bias-independent parameters in overlap capacitance model, such as CGSO and CGDO are extracted through an iteration flow to fit C_gs and C_gd of cold device. As for the intrinsic capacitance model parameters extraction, VOFFCV are NOFF identified as two key parameters governing the gate bias dependent from weak inversion to strong inversion. Finally, bias-dependent parameters in overlap capacitance model, such as CGSL, CGDL, CKAPPAS, and CKAPPAD can be extracted under saturation condition with higher Vds. Fig. 3.78 illustrates the capacitance model parameters extraction flow as described. Table 3.11 summarizes the capacitance model parameters extracted from UN65 n-MOSFET (W2N32) with ZBB, FBB, and RBB, and also the default model for a comparison. Fig. 3.79 (a)~(d) show a comparison between measurement and simulation for C_gg, C_gs, C_gd, and C_gb under ZBB

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(Vbs=0). The results reveals a large deviation from the meaurement by using default C-V model parameters and a good match with measurement when adopting the modified C-V mdoel parameters (Fig. 3.79). Similarly, the improved matching with measurement by simulation using the model parameters modified for FBB (V_bs=0.6V) and RBB (V_bs=0.6V) can be achieved, as shown in Fig. 3.80 and Fig. 3.81.

50 100 150 200 250

Gate Oxide Thickness, Tox (nm) Cof

Fig. 3.77 Gate sidewall fringing capacitances, Cof=Cg,Diff+Cg,CT simulated by Raphael for UN65 n-MOSFET (a) C_of, C_g,Diff, and C_g,CT vs. L_g (b) C_of, C_g,Diff, and C_g,CT vs. L_g,CT (c) C_of, C_g,Diff, and C_g,CT vs. T_g (d) C_of, C_g,Diff, and C_g,CT vs. T_ox

Fig. 3.77 Gate sidewall fringing capacitances, Cof=Cg,Diff+Cg,CT simulated by Raphael for UN65 n-MOSFET (a) C_of, C_g,Diff, and C_g,CT vs. L_g (b) C_of, C_g,Diff, and C_g,CT vs. L_g,CT (c) C_of, C_g,Diff, and C_g,CT vs. T_g (d) C_of, C_g,Diff, and C_g,CT vs. T_ox

在文檔中 四埠射頻金氧半電晶體與共用源汲極主動區之新型串疊結構的小訊號等效電路模型 (頁 122-143)