Chapter 4 New Cascode Design and Modeling for RF Circuits Simulation
4.3 Dual-gate MOSFET Equivalent Circuit Model and Parameters Extraction Method
4.3.1 Small Signal Equivalent Circuit Model of Dual-gate MOSFET at Off State
dual-gate MOSFET at off state, i.e. cold device condition with all of the terminals at zero bias.
To enable a complete model parameters extraction flow, this small signal equivalent circuit is divided into two parts – one region remarked by solid-line box is the intrinsic device model incorporating all of the gate related capacitances except gate to body capacitances, and the other enclosed by the dash-line box is the body network mode including gate (G1 and G2) to body capacitance (Cg1b and Cg2b), junction capacitances(Cjs1 and Cjd2), and body resistances.
First, the model parameters associated with the intrinsic device can be extracted from 4-port Y-parameters measured from the dual-gate test structure with ports assignment shown in Fig.
4.7(a). The extraction method is described by (4.5)~(4.11)
All of the gate capacitances except Cgb can be extracted from 4-port Y-parameters measured from dual-gate MOSFET as follows
137
4.7(b)
HF 2
| , gb
GB
gb g1b g2b
Im Y C
C C C
(4.12)
then, the inter-stage gate capacitances can be calculated from all of other gate capacitances determined from (4.5)~(4.12)
g1d1 gg1 g1s g1d g1b g1g2
C C C C C C (4.13)
g2s2 gg2 g2d g2s g2b g1g2
C C C C C C (4.14) The junction capacitances associated with S/D to B in M1/M2, namely Cjs1 and Cjd2 can be extracted from Im(YBS) and Im(YBD) measured from common gate structure, as given by (4.15) and (4.16)
| LF BS js1
C Im Y
(4.15)
| LF BD jd2
C Im Y
(4.16)
Note that all of the capacitances, except Cgb are extracted from Y-parameters at very low frequency to minimize the effect from parasitic inductances and resistances.
Finally, gate resistances associated with M1 and M2, denoted as Rg1 and Rg2 are extracted by Y-method given by (4.17) and (4.18). Note that the conventional Z-method, which has been frequently used in single MOSFET may not be applicable to dual-gate MOSFET. Fig. 4.10 summarize a complete model parameters extraction flow for small signal equivalent circuit model of dual-gate MOSFET at off state ((VG1= VG2= VD= VS= VB=0) in which the details of extraction method has been described by (4.5)~(4.18).
) ) |HF
G1G1
g1 2
G1G1
R Re(Y
Im(Y (4.17)
) ) |HF
G2G2
g2 2
G2G2
R Re(Y
Im(Y (4.18)
138 Cg1g2
G2 (4)
S (2) D (3)
Rbb Cjd2
B
Cjs2
Cjs1 Cg2b
Cg1b Cg1d1
Cg2d
Cg1s Cg2s2
G1 (1)
Lg2 Rg2
Rg1 Lg1
Ls Rs Rd Ld
Cg1d Cg2s
Rbb1 Rbb2
Cjd1 Rsd
Fig. 4.9 The small signal equivalent circuit model of dual-gate MOSFET at off state : the region remarked by solid-line box is the intrinsic device model excluding body network model and the region enclosed by dash-line box is the body network model
139
28
Extract In-stage cross-stage, and inter-gate capacitances from
dual-gate structure
Extract Cjs,Cjd, and Cgbfrom common gate structure Measure S-parameters from
dual- gate and common gate Off-state VG1=VG2=VD=VS=VB=0
Calculate
inter-stage capacitances
Extract and fine tune Rbb,Rbb2,Rbb3
Fig. 4.10 Model parameters extraction flow for small signal equivalent circuit model of dual-gate MOSFET at off state (VG1= VG2= VD= VS= VB=0)
In the following the extracted model parameters, such as in-stage capacitances, cross-stage capacitances, inter-gate capacitance, inter-stage capacitance, gate to body capacitance, junction capacitances, and gate resistances will be presented for a detailed discussion. Fig. 4.11 shows the in-stage gate capacitances Cg1s and Cg2d extracted from Im(YG1S) and Im(YG2D), which were measured from dual-gate MOSFET at off state and went through 4-port OpenM3 deembedding (short deembedding was not available due to problem with dummy short pads in L65003 for this thesis). It appears that Cg1s is larger than Cg2d. Taking a review on the layout and cross-section in the same plot, the distance between G1 and S is shorter than that between G2 and D and it explains why Cg1s is larger than Cg2d. At the same time, Cgs and Cgd
measured from the single MOSFET with the same finger width and number are provided for a comparison. Interestingly, a good match is demonstrated between Cgs/Cgd and Cg2d/Cg1s except somewhat larger difference between Cgd and Cg1s at very high frequency. The increase of capacitances at higher frequency suggests the impact from parasitic inductances and will be verified by simulation as follows. Fig. 4.12 demonstrates the cross-stage gate capacitances
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Cg1d and Cg2s extracted from Im(YG1D) and Im(YG2S) after 4-port OpenM3 deembedding.
Again, the difference between Cg1d and Cg2s, that is Cg1d >> Cg2s can be explained by the device layout in which G1 to D space is indeed shorter than G2 to S distance. Furthermore, the cross-stage capacitances are much smaller than the in-stage capacitances when put in the same scale for a comparison. It means that the gate to S/D coupling across different devices is reduced as compared with those in the same device. Fig. 4.13 makes a comparison between cross-stage gate capacitances and total gate capacitances Cgg1 and Cgg2. It demonstrates similar trend between M1 and M2 but some differences in the magnitude and ratio, that is Cgg1 >Cgg2, Cg1d >Cg2s, Cg1d /Cgg1 < 25%, and Cg2s /Cgg2 < 15%. Fig. 4.14 indicates the inter-gate capacitances Cg1g2 extracted from Im(YG1G2) also after 4-port OpenM3 deembedding. As expected, the magnitude is much smaller than in-stage gate capacitances and the weighting factor in the total gate capacitance is around 13~18% over the frequencies 1~40GHz. Again, the increase of Cgg1, Cgg2, and Cg1g2 at higher frequency suggests the influence from parasitic inductances at all of the four terminals, which were not eliminated because short deembedding was not available. Fig. 4.15 presents the inter-stage capacitances Cg1d1 and Cg2s2
calculated by (4.13) and (4.14) in which all of the other gate capacitances can be extracted from (4.5)~(4.12) for dual-gate MOSFET. Interestingly, Cg1d1 and Cg2s2 show minor difference in the magnitude and nearly the same frequency dependence, i.e. the higher frequency the smaller capacitance, which is in an opposite trend with that of in-stage, inter-gate, and total gate capacitances. At very low frequency, the ratio between the inter-stage capacitances in-stage capacitances, i.e. Cg1d1/ Cg1s and Cg2s2/Cg2d are around 25~33%. It explains why the total gate capacitance of M1 and M2, i.e. Cgg1 and Cgg2 in a dual-gate MOSFET can be effectively reduced as compared to the single MOSFET.
Regarding the gate to body capacitance Cgb, which can be extracted from Im(YGB) of common gate cascode structure, the results are shown in Fig. 4.16 with a comparison with that measured from single MOSFET. The Cgb measured from the common gate cascode structure,
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denoted as Cgb(G1+G2) is around two times that of single MOSFTE, i.e. Cgb(G1+G2)~2Cgb. Note that the major difference happens at very low frequency where Cgb(G1+G2) extracted from the common gate structure reveals a drastic increase but that of single MOSFET keeps much more flat with minor increase. It is suspected that the increase of Cgb(G1+G2) at very low frequency may be originated from the coupling from the gate through the inter-stage region, i.e. merged S/D diffusion (floating without contacts), then through the junction between merged S/D and body, and eventually to the body. Further effort is required to explore and clarify the mechanism. The layout of dual-gate MOSFET shown in Fig. 4.17 with the layers remarked for the contacts to gate, drain, body, and deep n-well (DNW) indicates that Cgb can be contributed from the inter-metal coupling capacitance via metal-3 (M3) on the gate contacts to metal-4 (M4) on body contacts. Fig. 4.18demonstrates the junction capacitances Cjs
and Cjd extracted from Im(YBS) and Im(YBS), which were measured from the common gate cascode structure at off state. Again, Cjs and Cjd are very close to each other and both reveal a drastic fall off with increasing frequency. This strong frequency dependence can be explained by body resistance network effect. Fig. 4.19 makes a comparison of the total gate capacitances between the dual-gate MOSFET, common gate structure, and single MOSFET.
The results indicate a close match between Cgg1+Cgg2 for dual-gate MOSFET and Cgg_CG for common gate structure. This consistency validates the accuracy of the gate capacitances determined by the extraction method and flow developed in this thesis. One more important point is that the total gate capacitance of dual-gate MOSFET is significantly smaller than twice that of single MOSFET, i.e. Cgg1+Cgg2 < 2Cgg, as shown in Fig. 4.19. This feature manifests the advantage of dual-gate MOSFET in suppressing Miller effect and the benefit in high frequency performance. Fig. 4.20 demonstrates the comparison of in-stage gate capacitances Cg1s and Cg2d, between measurement and simulation with and without parasitic inductances. As shown in Fig. 4.20(a), the simulation employing Lg=Ld =Ls=Lb =70pH can predict the increase of Cg1s and Cg2d at higher frequency and fit the measured data up to 40
142
GHz. On the other hand, the simulation without parasitic inductances shown in Fig. 4.20(b) indicates nearly a constant over the higher frequency up to 40 GHz. The verification by simulation proves the impact from parasitic inductances at higher frequency. Fig. 4.21(a) shows the gate resistances Rg1 and Rg2 of dual-gate MOSFET, extracted by Y-method given by (4.17) and (4.18). Both Rg1 and Rg2 approach a constant at sufficiently high frequency (f
>20GHz) and this frequency dependence can be reproduced by simulation as shown in Fig.
4.21(b). In this work, Rg1 and Rg2 associated with G1 and G2 of the dual-gate MOSFET are around 15, which is more than two times higher than that of single MOSFET. Referring to Table 4.2, Single-end contacts to the multi-finger poly gate fingers is considered the major cause responsible for the dramatic increase of Rg compared to that of standard multi-finger MOSFET in which two-end gate contacts are employed. The higher Rg will impose significant impact on fmax and NFmin, and an appropriate revision on the gate contacts layout is indispensable to eliminate the impact on mentioned high frequency performance.
Fig. 4.11 The in-stage gate capacitances Cg1s and Cg2d extracted from Im(YG1S) and Im(YG2D) of dual-gate MOSFET at off state. Cgs and Cgd of the standard MOSFET (W2N32) are
provided for a comparison.
0 5 10 15 20 25 30 35 40
10 15 20 25 30
35 VD=VG(1,2)=VB=VS=0
MOSFET Cgs Capacitances (fF) Cgd
Freq (GHz) Dual-gate MOSFET Cascode in-stage
Cg1s Cg2d
Cg2d Cg1s
G2
Drain Source
N+ N+
G2 G1 G1
N+
Merged SD
G2
S
G1 D143
Fig. 4.12 The cross-stage gate capacitances Cg1d and Cg2s extracted from Im(YG1D) and Im(YG2S) of dual-gate MOSFET at off state. In-stage capacitance Cg1s and Cg2d of the same device are provided for a comparison.
Fig. 4.13 The cross-stage gate capacitances Cg1d and Cg2s extracted from Im(YG1D) and Im(YG2S) of dual-gate MOSFET at off state. The total gate capacitances Cgg1 and Cgg2
associated with G1 and G2 of this dual-gate MOSFET are provided for a comparison.
0 5 10 15 20 25 30 35 40
144
Fig. 4.14 The inter-gate capacitances Cg1g2 extracted from Im(YG1G2) of dual-gate MOSFET at off state (VG1= VG2= VD= VS= VB=0).
Fig. 4.15 The inter-stage gate capacitances Cg1d1 and Cg2s2 calculated by (4.13) and (4.14) with all of the other gate capacitances extracted from (4.5)~(4.12) for dual-gate MOSFET at off state. In-stage capacitance Cg1s and Cg2d of the same device are provided for a comparison.
G2
145
Fig. 4.16 The gate to body capacitance Cgb extracted from Im(YGB) of common gate cascode structure at off state(VG= VD= VS= VB=0) and the comparion with Cgb measured the standard MOSFET (W2N32).
Fig. 4.17 The layout of dual-gate MOSFET with the layers remarked for the contacts to gate, drain, body, and deep n-well (DNW). Cgb can be contributed from the inter-metal coupling capacitance : metal-3 (M3) on the gate contacts to metal-4 (M4) on body contacts.
Gate Drain
Sourc e
Body DN
W
Body
DN W
0 5 10 15 20 25 30 35 40
0 5 10 15 20
VG=V
D=V
B=V
S=0
Cgb(W2N32)x2
Cgb(W2N32) Cgb(G1+G2)
Cascode Common-gate
Cgb (G1+G2)
Cgb (fF)
Freq (GHz)
MOSFET W2N32 Cgb Cgbx2
G (1)
D (3) Cascode Common-Gate
B(4) S (2) M2
M1
146
Fig. 4.18 The junction capacitances Cjs and Cjd extracted from Im(YBS) and Im(YBS) of common gate cascode structure at off state.
Fig. 4.19 The comparison of total gate capacitances measured from dual-gate MOSFET (Cgg1 +Cgg2), common gate MOSFET (Cgg_CG) and single MOSFET at off state.
147
Fig. 4.20 The comparison between the extracted in-stage gate capacitances Cg1s and Cg2d and those simulated with and without parasitic inductances (a) simulation with Lg=Ld =Ls=Lb
=70pH (b) simulation without inductance.
Fig. 4.21 The gate resistances of a dual-gate MOSFET (a) Rg1 and Rg2 extracted by Y-method (b) the comparison with simulation (BSIM4).
Table 4.3 summarizes a complete set of small signal equivalent circuit model parameters determined by the extraction method and flow, which have been developed for the dual-gate MOSFET at off state. In the following, an extensive verification on the model accuracy will be carried out through one-by-one comparison between the measurement and simulation by using this small signal equivalent circuit model for all of the 4-port S-parameters after openM3 deembedding. Fig. 4.22 ~ Fig. 4.25 present the 4-port S-parameters in terms of mag(Sij) (magnitude of Sij) in which i =1, 4, 3, 2 are corresponding to G1, G2, D, and S, respectively. The results demonstrate good match between measurement and simulation over
0 5 10 15 20 25 30 35 400
148
the frequencies up to 40 GHz. As for the phase(Sij) shown in Fig. 4.26 ~ Fig. 4.29, a good match with the measurement can be achieved by simulation for phase(Sii), i=1, 4, phase(S4i), i=1,3,4, phase(S21), and phase(S34) but leaving the other terms suffering larger deviation. The mismatch becomes particularly large for phase(S42), phase(S24), phase(S31) and phase(S31), which are all of the cross-stage parameters. The results suggest required improvement on both model accuracy and 4-port S-parameters measurement as well as deembedding.
Table 4.3 A complete set of small signal equivalent circuit model parameters of dual-gate MOSFET at off state
61
Capacitances fF Resistances Ω
Cg1s 19.6 Rg1 15
Cg2d 20.3 Rg2 16
Cg1d 6.53 Rd 1
Cg2s 2 Rs 1
Cg1g2 4.35 Rb 1
Cg1d1 7.53 Rbb1 70
Cg2s2 6.24 Rbb2 70
Cjd1 12 Rbb 700
Cjs1 22.9 Rsd_diff 1
Cjd2 22.76 Inductances pH
Cjs2 12 Lg 70
Cg1b 2.5 Ld 70
Cg2b 2.5 Ls 70
Lb 70
149 measurement. Lines : simulation by small signal equivalent circuit with body network model.
0 5 10 15 20 25 30 35 40 measurement. Lines : simulation by small signal equivalent circuit with body network model.
150 measurement. Lines : simulation by small signal equivalent circuit with body network model.
0 5 10 15 20 25 30 35 40 measurement. Lines : simulation by small signal equivalent circuit with body network model.
151 measurement. Lines : simulation by small signal equivalent circuit with body network model.
0 5 10 15 20 25 30 35 40 measurement. Lines : simulation by small signal equivalent circuit with body network model.
152 measurement. Lines : simulation by small signal equivalent circuit with body network model.
5 10 15 20 25 30 35 40
153