Small Signal Equivalent Circuit Model of Dual-gate MOSFET at Active State

be understood that both M1 and M2 operating saturation region, namely saturation- saturation, is the operation mode most favorable for a cascode amplifier. In this section, a small signal equivalent circuit model will be developed and certified for the dual-gate MOSFET at active state, i.e. saturation mode for both M1 and M2.

Fig. 4.30 illustrates the small signal equivalent circuit model proposed for the dual-gate MOSFET at active state. The bias condition for achieving saturation mode for both M1 and M2 is specified as VG1=0.4V, VG2=0.6V, VD=1.0V, and VS=VB=0. Following the extraction method and flow set up for dual-gate MOSFET at off state, the model parameters extraction method can be derived with necessary revision by incorporating transconductances and output resistances, such as g_m1 and r_o1 for M1, and g_m2 and r_o2 for M2. First, the gate capacitances associated with the core device can be extracted from 4-port S-parameters at active state under the specified bias condition, given by (4.19)~(4.28)

 

_active

Cgb can be and extracted from Im(YGB) measured from the common gate structure, Fig. 4.7(b)

 

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then, the inter-stage gate capacitances can be calculated from all of other gate capacitances determined from (4.19)~(4.26)

g1d1 gg1 g1s g1d g1b g1g2

C C C C C C (4.27)

g2s2 gg2 g2d g2s g2b g1g2

C C C C C C (4.28) The junction capacitances associated with S/D to B in M1/M2, namely Cjs1 and Cjd2 can be extracted from Im(Y_BS) and Im(Y_BD) measured from common gate structure at active state, as given by (4.29) and (4.30)

 

_active

| LF BS

js1

C Im Y



  (4.29)

 

_active

| LF BD

jd2

C Im Y



 (4.30)

Note that the other two junction capacitances in the inter-stage region, i.e. Cjd1 and Cjs2 cannot be directly extracted from 4-port Y-parameters and have to be calculated based on the bias-dependent junction capacitance model and the voltage drop at the inter-stage region predicted by simulation. Again, all of the capacitances except C_gb are extracted from Y-parameters at very low frequency to minimize the effect from parasitic inductances and resistances. The gate resistances associated with M1 and M2, i.e. R_g1 and R_g2 are considered weakly dependent on the gate and drain bias and can be approximated by the values at off state as shown in Table 4.3.

In the following, the extraction of transconductances and output resistances, such as gm1

and r_o1 for M1, and g_m2 and r_o2 for M2, based on Re(Y₃₁) = Re(Y_DG1) and Re(Y₃₃) = Re(Y_DD) as follows

)| _LF

m(Cascode) DG1

G Re(Y (4.31)

1

m2 o2 m(Cascode) m1

m2 o2

G g g r

  g r

 (4.32)

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Assume 1 1

1

m2 o2 m2 o2

m2 o2

g r g r

  g r 

 )| _LF

m(Cascode) m1 DG1

G g Re(Y (4.33)

)|_LF

out(Cascode)

DD

R 1

Re(Y (4.34)

(1 )

out(Cascode) o2 o1 m1 o1

R r r g r (4.35) Assume gm2=gm1 and ro2=ro1as the initial condition for an iteration cycle to achieve the optimized values for g_m1, g_m2, r_o1, and r_o2 respectively

o2 o1

initial condition : r r

( )

out(Cascode) o1 m1 o1

R r 2 g r

   (4.36)

( )

)|_LF

o1 m1 o1

DD

r 2 g r 1

  Re(Y (4.37) The iteration and optimization on r_o1 and r_o2 can be performed by best fitting to both 1/Re(Y₃₃)

= 1/Re(YDD) and 1/Re(Y22) = 1/Re(YSS).

Fig. 4.31 summarize a complete model parameters extraction flow for small signal equivalent circuit model of dual-gate MOSFET at active state (V_G1=0.4V, V_G2=0.6V, V_D=1.0V, and VS=VB=0) in which the details of extraction method has been described by (4.19) ~ (4.37).

Table 4.4 summarizes a complete set of small signal equivalent circuit model parameters determined by the extraction method and flow, which have been developed for the dual-gate MOSFET at active state. In the following, an extensive verification on the model accuracy will be carried out through the comparison between the measurement and simulation by using this small signal equivalent circuit model for all of the 4-port S-parameters after openM3 deembedding. First, transcondutance Gm=Re(Y31) and output resistance Rout=1/Re(Y33) are two most important parameters to verify the model accuracy at active state. Fig. 4.32(a)~(d) present Gm, Rout, and mag(S31) as well as mag(S33) related to the former two parameters.

Fig. 4.33~Fig. 4.36 present the 4-port S-parameters in terms of mag(Sij) (magnitude of Sij) in

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which i =1, 4, 3, 2 are corresponding to G1, G2, D, and S, respectively. The results demonstrate good match for mag(S_ij), i=1 and 4 but worse deviation for the others, such as mag(Sij), i=2 and 3. As for the phase(Sij) shown in Fig. 4.37~Fig. 4.40, a good match with the measurement can be achieved by simulation for most of the parameters, except somewhat larger deviation revealed in phase(S13) and phase(S24), i.e. the cross-stage parameters. This particularly large mismatch happened to those at off state as demonstrated previously. Again, the results suggest required improvement on both model accuracy and 4-port S-parameters measurement as well as deembedding.

G1 (1)

D (3)

Rbb

Cjd1

Body

Cjs1 Cjs2 Cg2b

Cg1b Cg2d

Cg1d1 Cg2s2

Cg1s

G2 (4)

Lg1 Rg1 Rg2 Lg2

Ls Rs Rd Ld

Cg2s

Cg1d

Rbb2

Rbb1 Cjd2

Rsd

S (2)

ro1

gm2 ro2

Cg1g2

gm1

Fig. 4.30 The small signal equivalent circuit model of dual-gate MOSFET at active state. M1 and M2 are operated at saturation mode and the channel conduction is modeled by gm1 and ro1

for M1 and gm2 and ro2 for M2.

157

63

Initial r_o1=r_o2to extract r_o1 from 1/Re(Y₃₃)

g_m2=Re(Y₃₁) Initial guess : g_m1=g_m2 Dual-gate MOSFET

Extract In-stage capacitances (active state) Adopt cross-stage & inter-gate cap. (off-state)

Measure S-parameters from dual- gate and common gate Active-state : V_G1=0.4V,V_G2=0.6V, V_D=1.0V, V_S=V_B=0

Common gate structure Extract C_js,C_jd, and C_gb

R_bb,R_bb2,R_bb3at off-state as initial values for fine tuning

Fine tune r_o1and r_o2get best fit to 1/Re(Y₂₂) and 1/Re(Y₃₃) calculate inter-stage capacitances

Fig. 4.31 Model parameters extraction flow for small signal equivalent circuit model of dual-gate MOSFET at active state

Table 4.4 A complete set of small signal equivalent circuit model parameters of dual-gate MOSFET at active state(VG1=0.4V, VG2=0.6V, VD=1.0V, and VS=VB=0)

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Capacitances fF Resistances Ω Inductances pH

C_g1s 34.54 R_g1 15 L_g 70

C_g2d 18.3 R_g2 16 L_d 70

C_g1d 7.53 R_d 1 L_s 70

C_g2s 2 R_s 1 L_b 70

C_g1g2 6.35 R_b 1 transconductance mA/V

C_g1d1 6.53 R_bb1 70 g_m1 20

C_g2s2 22.24 R_bb2 70 g_m2 26

C_jd1 8.94 R_bb 700 R_out Ω

C_js1 22.4 R_{sd_diff} 1 r_o1 206

C_jd2 17.6 r_o2 256

C_js2 8.94

C_g1b 2.5

C_g2b 2.5

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Fig. 4.32 The comparison of measurement and simulation for dual-gate MOSFET at active state VG1=0.4V, VG2=0.6V, VD=1.0V, VS= VB=0 (a) Gm=Re(Y31) (b) Rout=1/Re(Y33) (c) Mag(S31) (d) Mag(S33). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

New cascode : Dual-gate MOSFET VG1/V

New cascode : Dual-gate MOSFET VG1/V New cascode : Dual-gate MOSFET VG1/V

New cascode : Dual-gate MOSFET VG1/V

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Fig. 4.33 The measured and simulated Mag(S) of dual-gate MOSFET at active state VG1=0.4V, VG2²=0.6V VD=1.0V (a) Mag(S11) (b) Mag(S12) (c) Mag(S13) (d) Mag(S14). Symbols :

measurement. Lines : simulation by small signal equivalent circuit with body network model.

0 5 10 15 20 25 30 35 40

Fig. 4.34 The measured and simulated Mag(S) of dual-gate MOSFET at active state VG1=0.4V, V_G2²=0.6V V_D=1.0V (a) Mag(S₄₄) (b) Mag(S₄₁) (c) Mag(S₄₂) (d) Mag(S₄₃). Symbols :

measurement. Lines : simulation by small signal equivalent circuit with body network model.

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Fig. 4.35 The measured and simulated Mag(S) of dual-gate MOSFET at active state VG1=0.4V, VG2²=0.6V VD=1.0V (a) Mag(S33) (b) Mag(S32) (c) Mag(S31) (d) Mag(S34). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

0 5 10 15 20 25 30 35 40

Fig. 4.36 The measured and simulated Mag(S) of dual-gate MOSFET at active state V_G1=0.4V, V_G2²=0.6V V_D=1.0V (a) Mag(S₂₂) (b) Mag(S₂₃) (c) Mag(S₂₁) (d) Mag(S₂₄). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

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Fig. 4.37 The measured and simulated phase(S) of dual-gate MOSFET at active state V_G1=0.4V, VG2²=0.6V VD=1.0V (a) phase(S11) (b) phase(S12) (c) phase(S13) (d) phase(S14). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

0 5 10 15 20 25 30 35 40

Fig. 4.38 The measured and simulated phase(S) of dual-gate MOSFET at active state V_G1=0.4V, V_G2²=0.6V V_D=1.0V (a) phase(S₄₄) (b) phase(S₄₁) (c) phase(S₄₂) (d) phase(S₄₃). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

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Fig. 4.39 The measured and simulated phase(S) of dual-gate MOSFET at active state V_G1=0.4V, VG2²=0.6V VD=1.0V (a) phase(S33) (b) phase(S31) (c) phase(S32) (d) phase(S34). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

0 5 10 15 20 25 30 35 40

Fig. 4.40 The measured and simulated phase(S) of dual-gate MOSFET at active state V_G1=0.4V, V_G2²=0.6V V_D=1.0V (a) phase(S₂₂) (b) phase(S₂₄) (c) phase(S₂₃) (d) phase(S₂₁). Symbols : measurement. Lines : simulation by small signal equivalent circuit with body network model.

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4.4

Dual-gate MOSFET Simulation by BSIM-4 with Parasitic RLC Parameters

在文檔中 四埠射頻金氧半電晶體與共用源汲極主動區之新型串疊結構的小訊號等效電路模型 (頁 175-185)