Dual-gate MOSFET Measurement and Deembedding Method

Conventionally, almost all of RF CMOS circuit simulation and design reply on two-port S-parameters and the extracted model for fitting S- and Y-parameters in frequency domain. Basically, two-port characterization and modeling can appropriately fit two-terminal passive devices, such as resistors, capacitors, and inductors. However, this simplified approach generally forces 4-terminal devices lose freedom in bias schemes and available

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circuit topologies. MOSFETs given as the most frequently used 4-terminal devices, are generally limited to a 3-terminal configuration in RF circuit layout and design. This 3-terminal configuration, generally formed with body (B) shorted with source (S) to a common ground restricts MOSFET to a common source (CS) topology and non-availability of body biases. As for dual-gate MOSFET for new cascode, the restriction caused by two-port measurement and deembedding imposes significant impact on characterization and parameters extraction for modeling. To fix the mentioned problems, four-port measurement and deembedding become indispensable for dual-gate MOSFET parameters extraction and model development.

There are two kinds of four port test structures supported for high frequency S-parameter measurement. One is constructed with four GSG pads configured orthogonal between every two adjacent pads, namely 4-GSG, as shown in Fig. 4.3(b). Another one is built with two GSGSG pads in parallel with each other, namely 2-GSGSG, illustrate in Fig. 4.3(c). The later one becomes increasingly popular and recommended for the advantage of reduced area and potentially smaller parasitic due to shorter interconnection lines. Basically, the major differences between two structures are summarized as (i) 4-port on wafer calibration methods (ii) RF probes (iii) through pad layout and de-embedding method (iv) interconnection line layout for 4-terminal devices。 For on-wafer calibration in (i), Agilent PNA-L VNA can provide a better solution assisted with a dedicated calibration substrate。Regarding four port on-wafer measurement, NDL RF Lab. can support (i) and (ii). Note that probe correction is generally not employed in substrate calibration and has to be performed separately.

Conventionally, 12-error model is selected and the error terms are determined for each pair of probes using SOLT method on LRM substrate. In general, error terms determination is a sophisticated procedure but has a good stability with time. The major concern is contact impedance, which may evolve during the probe correction and has to be corrected at following de-embedding step。As for through pad layout and metal line routing for 4-terminal

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MOSFET in (iii) and (iv), dedicated effort is needed to explore an optimized design, which is relatively more challenging for RF MOSFET, a kind of active devices than 4-terminal passive elements like transformers. Four-port test structure like well known two-port structure incorporate multiple parasitic components (R, L, C), which are even more complicated than the two-port structure. Fig. 4.4 illustrates a simple equivalent circuit for a four-port structure incorporating parasitic impedances and admittances in each individual signal pad to ground and between every two adjacent signal pads. The basic de-embedding structures involve open and short dummy pads. First, open de-embedding for four port structures can be carried out according to a 4x4 Y-parameters matrix calculation. Then, four-port short de-embedding can be carried out according to the calculation of a 4x4 Z-parameters matrix.

Based on the equivalent circuit of 4-port short pads, the parasitic resistances (R) and inductances (L) extraction can be carried out, according to (4.1)~(4.4). Fig. 4.5(a) and (b) present Rg, Rd, and Rs, Rb extracted from two-port and four-port short deembedding structures (ShortM3 : top metal to metal-3) as shown in Fig. 4.3(a)~(c). Note that The parasitic R extracted from shortM3 indicate that 4-GSG suffers the maximum R at each port whereas 2-GSG can achieve the minimum values. All of the extracted resistances increase with raising frequency in the lower frequency domain, f <10GHz and gradually saturate to a constant when continuously increasing the frequency, well above 10GHz. The increase of R in the domain of f

<10GHz suggests the influence of skin effect. Fig. 4.6(a) and (b) shown the parasitic inductances, Lg, Ld, and Ls, Lb extracted from two-port and four-port shortM3 structures.

Similarly, the extracted L indicate that 4-GSG suffers the maximum L at each port whereas 2-GSG can keep the minimum values. However, these parasitic L reveal frequency dependence in contrast with that of parasitic resistances, that is all of the extracted L decrease with increasing frequency in f < 5GHz and gradually saturate to a constant when continuously increasing the frequency. The fall-off of parasitic L with increasing frequency suggests capacitive coupling effects, maybe from interconnection lines to the lossy substrate.

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Fig. 4.3 The layouts of 2-port and 4-port test structures for RF MOSFET measurement (a) 2-port tester with two GSG pads in parallel (b) 4-port tester, namely 4-GSG with four GSG pads in perpendicular direction between every two adjacent pads (c) 4-port tester, namely 2-GSGSG with two GSGSG pads in parallel.

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port4

port 2

Fig. 4.4 The equivalent circuit for a four-port test structure incorporating parasitic impedances (Zs) and admittances (Ypad, Yps)

Fig. 4.5 The parasitic resistance extracted from two-port (2-GSG ) and four-port (2-GSGSG, 4-GSG) shortM3 deembedding structures (a) Rg and Rd for interconnection lines to gate and drain pads (b)Rs and Rb for interconnection lines to source and body pads

0 5 10 15 20 25 30 35 40

0.0 1.0 2.0 3.0 4.0 5.0

(a) Short_M3

Resistances, Rg & Rd()

Freq (GHz) 2-GSG 2-GSGSG 4-GSG Rg Rd

0 5 10 15 20 25 30 35 400.0 1.0 2.0 3.0 4.0 5.0

Resistances, Rs & Rb() (b) Short_M3

Freq (GHz) 2-GSG 2-GSGSG 4-GSG Rs Rb

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Fig. 4.6 The parasitic inductances extracted from two-port (2-GSG ) and four-port (2-GSGSG, 4-GSG) shortM3 deembedding structures (a) Lg and Ld for interconnection lines to gate and drain pads (b) Ls and Lb for interconnection lines to source and body pads

4.3 Dual-gate MOSFET Equivalent Circuit Model and Parameters