Four-port RF MOSFET Layout and Measurement

In this thesis, there are totally three kinds of 4T RF MOSFET layouts and 4-port test structures implemented in different CMOS processes, such as UN90 (L90709), UN65 (L65003), and TN90RF (100A). 4-port RF MOSFET layout analysis for parasitic RLC extraction is introduced in sec. 3.1.2. 4-port RF MOSFET measurement and deembedding method are addressed in sec. 3.13. Finally, the parasitic resistance extraction from 4T RF MOSFET in 4-port test structure and the impact on electrical performance, such I-V and g_m

19

are presented in sec. 3.1.4. with a comparison with 3T RF MOSFET in 2-port test structure.

3.1.1 4T MOSFET Layout Analysis for Body Network Model Development

The circuit architectures of body network model and small signal equivalent circuits are critically determined by the layouts of RF MOSFETs, particularly for those built in 4-port test structures. Fig. 3.1(a)~(c) illustrate 3 different layouts of 4-port RF MOSFETs, which were implemented by UN65, UN90, and TN90RF processes, with test chip names given as L65003, L90709, and 100A, respectively.

Table 3.1 (a) summarizes 3 items of layout features in 4-port RF MOSFETs, which are identified as the major differences between the mentioned 3 test chips. For body contacts layout, L65003 adopts two rows of contacts in parallel with the gate finger, namely parallel body contacts. As for L90709 and TN90RF-100A, ring type body contacts enclosing the multi-finger MOSFET is employed to reduce body resistance. All of the 3 test chips were fabricated with deep n-well but different layouts in the connection to deep n-well and p-well body. For L65003, the deep n-well is tied together with p-well body and connected to port-4.

For L90709, deep n-well is connected to ground and p-well body is individually connected to port-4. As for TN90RF-100A, deep n-well is floating, i.e. without any connection to the external node. In this chapter, we will focus on the characterization, analysis, and modeling on L65003 and also the differences between L65003 and L90709. The study on TN90RF-100A will be presented in chapter 5.

In our previous work (YH Tsai in Prof. Guo group), a simple body network model as shown in Fig. 3.2 was developed for 4-port RF MOSFET in L90709. This body network model incorporates C_js and C_jd for junction capacitances from source and drain to body, and Cdnw for junction capacitance between deep n-well and p-well body. Rbb represents p-well body resistance and R_dnw is deep n-well resistance. According to L90709 layout feature, i.e.

body to port-4 and deep n-well to ground, this simple body network model is built with simple series RdnwCdnw from port-4 to ground (Fig. 3.2). Thus, the model parameters can be

20

extracted from 4-port Y-parameters, based on equivalent circuit analysis on the proposed body network model as follows. First, C_js and C_jd are extracted from Im(Y₄₂) and Im(Y₄₃) at very low frequency, given by (3.3) and (3.4). Then, the body resistance Rbb can be extracted from Re(Y₄₂) or Re(Y₄₃) with pre-extracted C_js and C_jd at very low frequency, denoted as R_bb(LF) given by (3.5) or (3.6). Also, Rbb can be determined from Re(Y42) or Re(Y43) at very high frequency, according to (3.9) or (3.10) and denoted as R_bb(HF). Note that it is considered that the Y-parameters under cold device condition (Vg=Vd=Vs=Vb=0) follow symmetric rule At very low frequency C C R

42( )

21

[ ]

[ ] 43( )

[ ] [ ]

Re( )

( )

jd LF

bb HF HF

jd LF js LF

R Y C

C C

   (3.10)

Theoretically, all of the RLC elements in the equivalent circuit should be constant independent of frequency. It is expected that R_bb(LF) extracted at very low frequency is equal to Rbb(HF) extracted at very high frequency. Table 3.2(b) summarizes Rbb extracted from L90709 and L65003 to verify 4-port RF MOSFET layout effects and frequency dependence.

The results from L90709 indicate very minor difference between Rbb(LF) and Rbb(HF) and prove that R_bb extracted from the equivalent circuit model is a simple resistance in dependent of frequency. Furthermore, the larger finger number can help reduce Rbb. However, Rbb extracted from L65003 reveal dramatic difference between R_bb(LF) and R_bb(HF). The extraordinary frequency dependence suggests that the body network model proposed for L90709 cannot be applied to L65003, due to fundamental differences in the 4-port RF MOSFET layout summarized in Table 3.2(a). As for L90709, the body network model is proven by a good match between the measured and simulated Re(Y43) using (3.2), as shown in Fig. 3.3. Note that Re(Y43) tends to saturate to a constant at very high frequency, which is predicted by (3.10). The saturation of Re(Y₄₂) or Re(Y₄₃) at high frequency suggests the saturation of substrate loss when the frequency increases beyond the attenuation frequency of the series RC in the body network model. However, the comparison of measured Re(Y₄₂) or Re(Y₄₃) between L90709 and L65003 shown in Fig. 3.4 indicates that both Re(Y42) and Re(Y43) reveal a fall off without any saturation when increasing frequency. Again, the results suggest that the simple body network model derived for L90709 is no longer valid for L65003. Potentially, a simple series RC for deep n-well cannot be applied to L65003 and a new body network model will be presented in sec. 3.2. Besides Re(Y42) and Re(Y43) for Rbb, Cdnw is one more important parameter to verify the difference between L90709 and L65003 with different layouts in deep n-well and p-well body. Considering that all of the capacitances related to body, i.e. port-4 have to follow charge conservation law, C_dnw can be extracted from 4 components of Im(Y_4i)

22

(i=1,2,3,4) at very low frequency given by (3.11).



44 43 42 41



0

1 Im( ) Im( ) Im( ) Im( ) |

Cdnw Y Y Y Y _

 ^

    (3.11)

Fig. 3.5 (a) and (b) present Cdnw extracted from L90709 and L65003, respectively. Note that C_dnw determined at very low frequency reveal different body biases dependence between L90709 and L65003. For L90709 with deep n-well separated from p-well body, the body biases (ZBB, FBB, and RBB) applied to p-well lead to corresponding biases at body to deep n-well (grounded) and significant variation of Cdnw at very low frequency. As for L65003 with deep n-well tied together with p-well body, the body biases are applied to p-well body and deep n-well simultaneously and it leads to zero bias at the junction between deep n-well and p-well and explains why the C_dnw are not sensitive to various body biases.

(a) (b) (c)

Fig. 3.1 4T RF MOSFET layouts implemented in test ships using different processes (a) UMC 65nm standard logic UN65SP (b) UMC 90nm low leakage process UN90LL (c) TSMC 90nm RF process TN90RF

S (2) D

(3) Rbb

Body (4)

Cjs

Cjd Cdnw Rdnw

Fig. 3.2 A Simple body network model for L90709 4T RF MOSFET with deep n-well and

23

p-substrate connected to ground and p-well body to port-4

Table 3.1 (a) 4T RF MOSFET layouts in test chips using different processes Processes

body contact layout

deep n-well Dummy poly

UN65sp_L65003 Parallel Connected to body 1

UN90LL_L90709 Guarded Ring Connected to Ground 1

TN90RF_100A Guarded Ring Floated 2

4T MOSFET layout features

Table 3.1 (b) Rbb extracted from Re(Y42) and Re(Y43) under very low and very high frequencies for 4T RF MOSFETs in UN90_L90790 and UN65_L65003

4T MOSFET

process/layout Re(Y₄₃) (LF) Re(Y₄₂) (LF) Re(Y₄₃) (HF) Re(Y₄₂) (HF)

L90709_W2N8 1002 729 992 869

L90709_W2N16 601 522 596 642

L90709_W2N32 372 344 368 361

L90709_W05N64 478 444 498 485

L90709_W1N32 539 486 531 567

L65003_W2N32 1050 958 385 324

Rbb ()

0 5 10 15 20 25 30 35 40 -2.0

-1.5 -1.0 -0.5

0.0 V_G=V_D=V_S=V_B=0

UN90-L90709 Meas Model W2N8

W2N16 W2N32

Re

(

Y 43

) (

10-3

)

Freq (GHz)

Fig. 3.3 Comparison of measured Re(Y₄₃) and simulated ²

43 2 2 2

( )

Re( )

1 ( )

jd jd js bb

jd js bb

C C C R

Y C C R





 

   derived

from simple body network model proposed for UN90 4T RF MOSFE layout with deep N-well connected to ground and body to port-4 (3 : drain, 4: body)

24

300 C_dnw L90709_W2N32 ZBB

L90709_W2N32 FBB

Fig. 3.5 Deep n-well to body junction capacitance C_dnw extracted from Y-parameters at very low frequency for 4T RF MOSFET with different layouts (a)UN90 L90709 (b) UN65 L65003

25

3.1.2 4T MOSFET Layout Analysis for Parasitic RLC Extraction

Four-port (4-port) S-parameters measurement and deembedding are fundamental works for 4-port RF MOSFET characterization and equivalent circuit model development. As mentioned previously, the high frequency characteristics is critically determined by the layout of the core device and test structure. In generally, there are two kinds of 4-port test structures, such as 4 GSG pads (4-GSG) and 2 GSGSG pads (2-GSGSG). In this thesis, the latter one, i.e.

2-GSGSG is adopted for taking the advantages of smaller parasitic RL and small chip area due to shorter interconnection. Regarding the deembedding method, open deembedding is employed to extract and remove the parasitic capacitances and short deembedding is taken to remove the parasitic resistances (R) and inductances (L). It has been known from our previous work that parasitic capacitances are contributed from the pads, interconnection lines, and lossy substrate underneath, and dummy open pad with interconnection lines to bottom metal, namely open-M1 is necessary to realize a truly clean open deembedding. Unfortunately, open-M1 is not available in this thesis, due to limited chip area. Fig. 3.6(a) illustrates the layout of 4-port open deembedding structure. The parasitic capacitances associated with this open deembedding structure can be determined by 4-port Y-parameters given by (3.12)~(3.15).

Note that 4 ports are assigned corresponding to 4 electrodes of the 4T RF MOSFET given by 1 : Gate (G), 2 : source (S), 3: drain (D), 4 : body (B). Fig. 3.6(b) presents the parasitic capacitances associated with gate, source, drain, and body, which were extracted from 4-port Y-parameters. The results indicate difference of around 1~5 fF in the parasitic capacitances between every two ports and reveal difference in the layout of interconnection lines to each port. Also, the significant difference between C_ss,open and C_dd,open suggests that layouts for interconnection to source and drain are exactly not identical and it will lead to asymmetric effect in the S- and Y-parameters between source and drain.

11 ,

Im( )_open

gg open

C Y

  (3.12)

26

22 ,

Im( )_open

ss open

C Y

  (3.13)

33 ,

Im( )_open

dd open

C Y

  (3.14)

44 ,

Im( )_open

bb open

C Y

  (3.15)

0 5 10 15 20 25 30 35 40

23 24 25 26 27 28 29 30 31 32 33 34

C_D,open

C_B,open C_S,open

C_G,open

Dummy open pads C_B,Open : body(B) CG,Open : gate(G) CD,Open : drain(D) C_S,Open : source(S)

Open pads capacitances (fF)

Freq (GHz)

(a) (b)

Fig. 3.6 (a) 4-port open deembedding test structure (b) parasitic capacitances of dummy open pads

27

3.1.3 4-port RF MOSFET Measurement and De-embedding Method

 4-port S-parameters measurement system setup

Fig. 3.7 illustrates the equipments configuration for 4-port S-parameters measurement.

This system incorporates Agilent PNA E8364B、test set N4421 for extending 2-port to 4-port and Agilent 4155 for DC parameter analyzer as shown Fig. 3.8. Note that RF cables and adapters are selected with the spec. of 2.4 mm to enable RF measurement up to 50 GHz. The off chip calibration before on-wafer measurement, namely short-open-load-thru (SOLT) is carried out through programmable control of wincal, which is offered by cascade.

 DC measurement setup

I-V measurement for DC characterization was performed using another system to avoid any change to the configuration of the 4-port S-parameters measurement system. This arrangement comes from the consideration that the 4-port S-paramters system with special configuration is not suitable for simultaneous measurement of S-parameters and DC parameters. In this work, the system for low frequency noise measurement as shown in Fig.

3.9 and Fig. 3.10 is utilized for DC measurement. The basic criterion to approve this approach is that the DC parameters measured by using mentioned two systems should be consistent for the same device and it has been proven through our verification.

 De-embedding methods

For the purpose of extracting MOSFET parameters from measured data, the on-chip RF measurement is adopted. After calibration of measurement system, we suppose to make the reference planes be located at the probe tips, as shown in Fig. 3.11. The rest work is focused on that how we get device parameters from measured data which excludes parasitic effects by using de-embedding method.

Open de-embedding

The open pad is the full structure only taken off device. Before doing any de-embedding step,

28

we have to transform measured S-parameter data of device with pads into measured Y-parameter data. The representation is shown as Fig. 3.12. Also, the measured S-parameter data of open pad have to be transformed into measured Y-parameter data.

From Fig. 3.13 of open pad equivalent circuit and Fig. 3.12, we can construct the Y-parameter matrices to represent open pad and device with pads.

mea

mea Y

S  (3.16)

1 1 12 13 14

12 2 2 23 24

13 23 3 3 34

14 24 34 4 4

C a C b C C C

C C a C b C C

open open

C C C a C b C

C C C C a C b

Y Y Y Y Y

Y Y Y Y Y

S Y

Y Y Y Y Y

Y Y Y Y Y

   

 

     

 

 

     

     

 

(3.17)

YC1a(b) ,YC2a(b), YC3a(b) and YC4a(b) are coupling parameters between pads and reference ground.

Y_CXY is the coupling parameter between two ports.

So far, we can use equation (3.16) and (3.17) to do the open de-embedding. The coupling parameters included in Y_mea can be de-embedded by this way.

open mea o

mea Y Y

Y _{_}   (3.18)

But remember that the ZRL1 ~ ZRL3 parameters are still remained in Ymea_o matrix.

29

Fig. 3.7 4 port S-parameters measurement setup including Agilent PNA E8364B, test set N4421, bias-Tee, RF cables, and adapters with 2.4mm spec. for high frequency measurement up to 50 GHz.

(a) (b)

(c)

Fig. 3.8 Measurement equipments (a)Agilent PNA E8364B (b) 4-port test set Agilent N4421 (c) DC parameters analyzer Agilent 4155

30

Fig. 3.9 Low frequency noise measurement system setup

Fig. 3.10 Low frequency noise measurement system in NDL

31

Port 2 Port 3

Ground pad

Devce

Port 1 Port 4

Ground pad Ground

Signal

Ground Ground

Signal

Ground

Reference planes locate at probe tips Ground

Signal

Ground

Ground

Signal

Ground

Fig. 3.11 Four-port test structure 2-GSGSG for 4-port S-parameters measurement

32 Y^C14

Device Z^RL3

Z^RL1

Z^RL2

Port 4 Port 1

Y^C23

Port 2 Port 3

Z^RL4 YC1a

YC12 YC34

Y^C13

Y^C24 YC1b

Y^C2b

Y^C2a Y^C3a

YC3b

YC4b

Y^C4a

Fig. 3.12 The equivalent circuit of a 4-port test structure with DUT and pads

33 Y^C14

Z^RL2

Port 4 Port 1

Y^C23

Port 2 Port 3

Y^C1a

Y^C12 Y^C34

Y^C13

Y^C24 Y^C1b

Y^C2b

Y^C2a Y^C3a

Y^C3b Y^C4b Y^C4a

Fig. 3.13 The equivalent circuit of 4-port dummy open pads for open deembedding

3.1.4 4-port RF MOSFET Parasitic RLC Extraction Results and Comparison with 2-port Structure

According to the pads layout for 4-port test structure and interconnect configuration for DC measurement as shown in Fig. 3.14, the parasitic resistances can be identified coming from two

34

major sources, such as on-chip pads to DUT interconnection lines denoted as RS(DUT) and off-chip DC cables denoted as R_S(Cable).

s s DC cable s DUT

R R _ R

Gate bias

DC Source cable resistance Pad to DUT metal

line resistance

Source bias

DC Source cable resistance

Bulk bias Drain bias

Fig. 3.14 The schematics of 4-port equivalent circuit incorporating parasitic resistances from off-chip DC cables and on-chip interconnection lines.

The aggressive device scaling driven by CMOS technology advancement can boost the gate speed and cut-off frequency, attributed to gate length scaling and driving current enhancement.

However, the merit achievable from device scaling is limited to the ideally intrinsic devices, which are free from parasitic resistances(R), capacitances(C), and inductance (L). In practice, the parasitic RLC cannot be eliminated to zero, under either chip operation or measurement and the merit from device scaling will be degraded. The impact of parasitic resistances on I-V characteristics can be identified from the I-V measurement on UN65 and UN90 RF MOSFETs in 2-port and 4-port test structures, as shown in Fig. 3.15(a) and (b), respectively. It has been known from our previous study that 4-port test structures generally lead to current degradation, due to longer interconnection line from the pads to DUT. As shown in Fig. 3.15(a), UN65 4-port n-MOSFET (W2N32) in L65003 reveals Idsat degradation as high as 21.63%, as

35

compared with that of 2-port n-MOSFET in L65909. Note that the adoption of DC bias-Tee in L65909 measurement is another key factor for suppressing parasitic resistance effect and improving Idsat. As for UN90 n-MOSFET shown in Fig. 3.15(b), the comparison between 2-port and 4-port nMOSFET (W2N16) indicates I_dsat degradation of around 10.16%, which is only half that of UN65 devices. The results suggest the higher driving current, the more degradation from the parasitic resistance.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0

5 10 15

20 UN90 NMOS W2N16, Vgs=0.2~1.2V 2-port (2-GSG)

4-port (4-GSG) 4-port (2-GSGSG)

I d (mA)

V_ds (V) 0.0 0.2 0.4 0.6 0.8 1.0

0 10 20 30 40 50

60 UN65 NMOS W2N32, measured Vgs=0.2~1.0V L65909 2-GSG

wi DC sense L65003 2-GSGSG wo DC sense

I d (mA)

V_ds (V)

(a) (b)

Fig. 3.15 The Ids-Vds measured from RF MOSFET W2N32 (a) 65nm devices : comparison between 2-port tester (2-GSG) in L65909 and 4-port tester (2-GSGSG) in L65003 (b) 90 nm devices in L90709 : comparison between 2-GSG, 4-GSG, and 2-GSGSG.

Presently, the 4-port S-parameters measurement system set up by NDL RF Lab. doesn‘t incorporate bias Tee with DC sense and cannot eliminate DC cable resistance when offering the DC voltage. Table 3.2 summarizes the configurations for DC I-V measurement, 2-port S-parameters, and 4-port S-parameters for a comparison.

According to the comparison of I-V characteristics for RF MOSFET with the same dimension (W2N32), measured from 2-port tester in L65909 and 4-port tester in L65003, shown in Fig.

3.15(a), the total parasitic resistance contributed from off-chip DC cable and on-chip

36

interconnection line is around 2Ω.The former, i.e. DC cable resistance can be measured by I-V meter (三用電表) and the result is around 1Ω.It suggests that the latter, i.e. pad-to-DUT interconnection line contributes remaining 1Ω.The assumed parasitic resistances were employed in the 4-port RF MOSFET for I-V simulation (BSIM-4) and the results shown in Fig.

3.16 indicates a good match between the measured and simulated Ids-Vds under various Vgs. The good agreement justifies the accuracy of the assumed parasitic resistance.

Table 3.2 The configurations for DC I-V measurement, 2-port and 4-port S-parameters measurement

DC

measurement

2 port S parameter 4 port s parameter

Bias Tee N Y Y

Power supply with DC sence

N Y N

Power supply HP4145 HP4142 HP4155

Bias Tee with DC sence N Y N

0.0 0.2 0.4 0.6 0.8 1.0

0 10 20 30 40 50 60

UN65 NMOS W2N32, Vgs=0.2~1.0V Meas. 2-GSGSG wo DC sense Sim. Rs=Rd=Rg=Rb=2

I

d

(mA)

V

ds

(V)

Fig. 3.16 Comparison of the measured and simulated I_ds-V_ds under various V_gs (0.2~1.0V) for 4-port RF NMOS W2N32 (65 nm L65003). Parasitic resistances at 4 terminals, Rs=Rd=Rg=Rb=2Ω were employed for I-V simulation

37

Due to the mentioned restriction of 4-port S-parameters measurement system currently available in NDL RF Lab., DC cable resistance cannot be removed from the measured I-V characteristics. Subsequently, the transcondutance g_m derived from I_ds-V_gs, i.e. g_m=dI_ds/dV_gs cannot avoid the influence from the cable resistance and the gm degradation may become significant for DUT with larger dimension and higher current. 。For I-V and large signal simulation performed by BSIM-4, the parasitic resistances from off-chip DC cable and on-chip interconnection lines have to be considered. As for small signal equivalent circuit simulation, it is assumed that the DC bias shift due to DC cable resistance can be neglected. The assumption comes from the fact that S-parameters measurement under normal condition is performed with bias Tee with DC sense, which can eliminate the effect of DC cable resistance. Furthermore, the g_m from small signal measurement is derived from the Y-parameters after open and short deembedding, which can eliminate the effect of pads to DUT interconnection lines resistance.

To verify the assumption, the impact of DC cable resistance on g_m from large signal I-V and small signal Y-parameters was investigated by BSIM simulation, as shown in Fig. 3.17. The gm

from large signal I-V is apparently lower than those from Y-parameters with or without DC cable resistance and the later one indicates very minor sensitivity to DC cable, due to bias Tee effect (with DC sense). Unfortunately, the 4-port S-parameters measurement system currently available at NDL RF Lab. doesn‘t incorporate bias Tee with DC sense. Due the undesired restriction, DC cable resistance effect cannot eliminated from g_m even using small signal measurement and the measured gm is always smaller compared to the intrinsic gm. However, the g_m degradation due to mentioned on-chip and off-chip parasitic resistances can be reduced by using Y-parameters than that determined I-V method.

38

0.0 0.2 0.4 0.6 0.8 1.0

0 10 20 30 40 50 60 70

80 UN65 NMOS W2N32 BSIM-4 sim. Vds=1V

gm=Id/Vg wi R_cable+R_{pad_metal} gm=Re(Y

31) wi R

cable

g_m=Re(Y₃₁) wo R_cable

V_gs (V) g m (mA/V)

Fig. 3.17 Comparison of simulated gm-Vgs at Vds=1.0V for 4-port RF NMOS W2N32 (65 nm L65003) under three conditions : I-V characteristics, Y-parameter without DC cable resistance, and Y-parameters with DC cable resistance.

39

在文檔中 四埠射頻金氧半電晶體與共用源汲極主動區之新型串疊結構的小訊號等效電路模型 (頁 40-61)