Chapter 3 Four-port RF MOSFET Modeling for Simulation with DBB ( UN65 CMOS
3.4 BSIM-4 with Improved Body Network Model for Four-port RF MOSFET
3.4.1 BSIM-4 I-V Model Calibration and Simulation for 65nm 4-port RF MOSFET with
In this thesis, 4-port RF MOSFETs with multi-finger structure and typical gate length have been designed and fabricated using UMC 65nm (UN65) CMOS process in which the physical gate oxide thickness is 1.6 nm and typical gate length on layout is 60 nm. The 4-port test structure is implemented to support 4-terminal (4T) MOSFETs in which the body and source are separated to allow various body biases, such as forward body bias (FBB), reverse body bias (RBB), and zero body bias (ZBB). The freedom of body biases is so call dynamic body biases (DBB) scheme and becomes a potential solution for low voltage and low power design. The controllable VT shift from DBB, namely dynamic VT becomes an effective approach to reducing voltage at on-state for low active power and suppressing leakage at off-state. To accurately predict the VT shift under DBB, the threshold voltage (VT) model becomes the first important model to be verified.
As shown in (3.49), the VT model implemented in BSIM-4 incorporates several geometry and bias dependent effects, such as short channel effect (SCE), narrow width effect (NWE), drain induced barrier lowering effect (DIBL), and drain induced threshold voltage shift effect (DITS). Short channel effect (SCE) is generally defined as VT lowering due to channel length reduction. The basic mechanism responsible for SCE is charge sharing effect from the depletion layer near the source/drain (S/D) junctions. The VT lowering effect becomes worse when
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increasing drain bias and/or reverse body bias, due to increasing depletion layer width and is implemented as DIBL effect, which is a function of drain voltage (Vds) and body bias (Vbs). For planar CMOS devices, channel length scaling to deep submicron and further to nanoscale regime, SCE and DIBL become excessively large and lead to extraordinarily high leakage current at off state. To fix this problem, the conventional channel doping technique is no longer valid and non-uniform channel engineering using retrograde channel and halo implantations becomes an effective solution. The former one, i.e. retrograde channel implantation results in vertical non-uniform channel profile and the latter one, i.e. halo implantation creates lateral non-uniform channel profile. The lateral non-uniform channel profile from halo implantation can reduce SCE in sufficiently short devices and keep body effect reasonably low (prevent from excessive increase of body effect) for very long devices. Unfortunately, the lateral non-uniform channel profile with lightly doped central channel and heavily doped halo region near S/D leads to undesired VT shift when increasing Vds in very long channel devices, which is defined as DITS in BSIM-4 [5]. The mechanism responsible DITS comes from the surface potential variation of the lightly doped channel, which is strongly modulated by drain bias even at subthreshold region [6-7].
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The model equation implemented for every individual effect is described as follows. The first term in (3.49) represents the body bias effect of the VT subject to non-uniform channel doping profiles from retrograde and halo implantations. VTHO is the virgin VT for ideally long channel device under zero body bias. K1ox represent the first-order body effect coefficient for uniformly doped channel and and K2ox is the second-order coefficient due to vertical non-uniform doping profile from retrograde channel implantation. Leff is the effective channel length, which is different from the gate length on layout. Note that Leff used in I-V model may be different from that used in C-V model. LPEB denotes the length subject to lateral non-uniform doping profile from halo implantation and the larger ratio of LPEB/Leff, i.e. the longer LPEB and/or shorter Leff, will lead to higher VT and larger body bias effect. built-in potential Vbi, and surface potentialS. Note that the characteristics length tdefined by (3.50) is determined by the substrate depletion width Xdepand electrical equivalent oxide thickness TOXE. The widerXdepand/or thicker TOXE will lead to longer t, i.e. smaller ratio
eff / t
L and then worse SCE, i.e. larger VT lowering due to SCE. On the other hand, the higher channel doping concentration to reduce Xdepand/or thinner TOXE can help reduce tand
DIBL has been known as another form of short channel effects, which becomes worse when increasing Vds. The primary mechanism responsible for DIBL is the source to channel barrier lowering driven by the raised surface potential at drain end, due to drain bias Vds. The third term
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in (3.49) represents the DIBL as a function of Vds, effective body bias (Vbs,eff), Leff and the ratio w.r.t. t, i.e. Leff / t. This DIBL model assumes the VT shift as a linear function of Vds. In addition to the linear dependence of Vds, the body bias under reverse condition will increase DIBL effect and resulted VT lowering.
0.5 ( 0 )
cosh( ) 1
bseff ds eff
t
ETA ETAB V V DSUBL
The fourth term in (3.49) represents DITS effect as an exponential function of Vds [21]. As mentioned previously, this DITS becomes significant in sufficiently long device and is simulated as a function of Leff as follows. Note that the longer Leff and higher Vds makes the term inside the napproach unity and resulted VT shift becomes very small. The result looks in contradiction with the expected DITS that is the larger VT shift associated with longer devices.[22, 23]
n 1
0(1 ds)
eff
t DVTP V
eff
nv L
L DVTP e
The last term in (3.49) represent narrow width effect (NWE) for CMOS using LOCOS or inverse narrow width effect (INWE) for modern CMOS devices using STI as the isolation technology[24].
( 3 3 )
' 0
bseff S
eff
K K B V TOXE
W W
Where, TOXE is electrical gate oxide thickness and Weff is the effective channel width.
In older technologies before 0.25um node, the LOCOS adopted as the isolation technique generally leads to narrow width effect, i.e. the narrower width, the higher |VT|. The increase of
|VT| with width scaling is originated from the bird‘s beak around the LOCOS corner, which contributes additional body charges required for depletion and lead to higher |VT|. As for modern technologies since 0.25um node, the isolation technique has been switched from LOCOS to STI. New feature associated with STI is that 2-dimensional field crowding effect
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and gate oxide thinning due to divot near STI top corner results in |VT| lowering from channel width scaling and it is known as inverse narrow width effect (INWE)[24]. In this study using 65nm CMOS technology (UN65), the width dependence of VT should follow STI feature, i.e.
INWE and the parameter K3 implemented in VT model of BSIM-4 for width dependence becomes negative to generate VT lowering with width reduction.
Besides VT model, mobility model is recognized as one more important model for accurate I-V simulation of MOSFETs. As a matter of fact, the carriers transport in inversion mode MOSFET is a kind of surface conduction instead of bulk transport. The carriers transport along the inversion channel encounters multiple scattering effects, such as phonon scattering, coulomb scattering, and surface roughness sattering. Note that all of three scattering mechanisms are dependent on the normal electric field Eeff at gate oxide/Si substrate interface, determined by the gate bias VGS and workfunction or gate overdrive VGT, and gate oxide thickness (TOXE). The effective mobility eff is determined by the Matthiessen‘s rule given by (3.51)-(3.54). Theoretically, the coulomb scattering dominates at low field and the surface roughness scattering becomes the dominant mechanism at high field.
Phonon scattering plays a role in the medium field where coulomb scattering and surface roughness scattering become less important. In BSIM-4, the normal field Eeff is calculated as a function of effective gate overdrive Vgst,eff, threshold voltage Vth , and electrical gate oxide thickness TOXE given by (3.55) for n-MOSFETs. According to (3.51)-(3.55), the effective mobility eff is simulated by the formula with the expression of (8) in which U0 represents the bulk mobility free from surface scattering, UA and UB are first–order and second-order coefficients for surface roughness scattering at higher field, and the last term with UD is proposed to simulate coulomb scattering at very low field. Note that body bias effect is incorporated in the linear term of normal field, i.e. the first order of surface roughness scattering and UC is fitting parameter to adjust body bias effect. For RBB, UC is positive to increase the normal field and surface scattering, and then degrade eff. As for FBB, UC
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gseff th gseff th th
bseff simulation of drain current in strong inversion region. Regarding the subthreshold I-V simulation, a unified channel charge density model adapted to both subthreshold and strong inversion regions is proposed to ensure a continuous and smooth transition from the subthreshold to strong inversion. This unified charge density model considering charge layer thickness is express by (3.57),
0 , ,
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Then, a unified expression of local charge density distribution function along the direction of channel length (y) is given by (3.64),
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1 dep _
oxe oxe
C Cdsc Term CIT
n NFACTOR
C C
(3.68)
_ ( ) 0.5
cosh 1 1
ds bseff
eff
t
Cdsc Term CDSC CDSD V CDSCB V
DVT L
(3.69)
WhereCdsc Term_ represents the coupling capacitance between source and drain along the channel. CIT is the capacitance due to interface states. Note that the subthreshold the subthreshold swing determined by n shares the same exponential dependence on channel length as DIBL effect.
In general, the simulation using default model parameters cannot fit the measured I-V characteristics in nanoscale MOSFET, particularly with DBB for our objective in this thesis.
Due to the fact, I-V model parameters extraction and optimization is indispensable. First, VT
extraction in both linear and saturation regions is the fundamental work to carry out VT model calibration. Linear VT (VT,lin) can be extracted from Ids-Vgs in linear region (|Vds|=0.1V or 0.05V), using maximum gm (gm,max) or constant current (CC) methods. After the extraction of VT,lin, the saturation VT (VT,sat) can be determined from Ids-Vgs in saturation region (|Vds|=Vdd
=1.0V for UN65), using CC method, according to the same current level corresponding to VT,lin. A comprehensive calibration on VT model requires multiple devices with a wide splits of channel lengths and widths. However, the splits of device dimensions cannot available from our test chip due to limited chip area. The compromised approach is taken to focus the optimized fitting for the multi-finger MOSFET with typical length, i.e. L=60 nm on layout, fixed finger wdith, WF=2m, and different finger numbers (N=16 and 32). As mentioned in the beginning, DBB effect is the major topic of our interest and VT model parameters modification to fit measured VT under ZBB, FBB, and RBB becomes the first step for I-V model calibration.
Following the accurate extraction and simulation of linear and saturation VT under DBB, the second step is mobility model parameters extraction and calibration based on Ids-Vgs in linear region. UD responsible for coulomb scattering at very low field (Eeff) is the first parameter to be
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extracted. After that, UA and UB contributing to surface roughness scattering at high field can be extracted through a fitting to Ids-Vgs in linear region, under higher Vgs. Subsequently, UC responsible for Vbs effect can be extracted from Ids-Vgs under DBB (i.e., ZBB, FBB, and RBB).
Note that the mobility model parameters extraction and optimization can be carried out through the best fitting to gm-Vgs in linear region, i.e. the first derivative of Ids w.r.t. Vgs, given bygm Ids/Vgs. The third step is DIBL effect related model parameters extraction from Ids-Vgs at high Vds, i.e. saturation region. The accuracy of extracted DIBL effect parameters can be verified by the VT shift from VT,lin to VT,sat. Also, DIBL reveals its influence on output resistance Rout from Ids-Vds under various Vgs. Besides DIBL effect, accurate simulation of Ids-Vds and Rout have to take into account of channel length modulation (CLM) effect and substrate current induced body effect (SCIBE). Finally, subthreshold I-V model parameters extraction and calibration is performed and verified by Ids-Vgs in semi-log scale, i.e.
ds gs
ogI V . Details of the subthreshold I-V model parameters can be referred to (3.66)
~(3.69).
The mentioned I-V model parameter extraction flow was performed on UN65 multi-finger MOSFET with L=60nm, WF=2
Table 3.8 presents the extracted model parameters associated with VT, mobility, and subthreshold current models, under ZBB, FBB (Vbs=0.6V), and RBB(Vbs=-0.6V), and the comparison with default ones provided by UMC for logic devices. Note that a single set of model parameters for various body biases, such as ZBB, FBB, and RBB is not available from current models in BSIM-4.
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Table 3.8 (a)VT and mobility models parameters extracted from UN65 MOSFET W2N32 under ZBB ((Vbs=0), FBB ((Vbs=0.6V), and RBB ((Vbs=-0.6V) (b) VT extraction result (a)
parameter Default ZBB (Vbs=0V) FBB (Vbs=0.6V) RBB (Vbs=-0.6V)
Vth0 88.1m 88.1m 88.1m 88.1m
K2 36.6m 36.6m 86.6m 36.6m
K1 113m 105m 105m 112m
U0 20.62m 28.42m 30.02m 25.82m
UA 1.29n 1.89n 1.49n 1.59n
UB 2.043a 2.343a 2.843a 2.343a
UC 71.11p 71.11p 71.11p 71.11p
UD 0 8.9125E17 1.035E18 8.9125E17
Voff -31.9m -31.9m -31.9m -31.9m
VoffL -4.04n -4.04n -4.04n -4.04n
NFACTOR 1233.9m 1233.9m 1233.9m 1233.9m
CDSC 453.4u 453.4u 453.4u 453.4u
CDSD 0.6m 0.6m 0.6m 0.6m
CDSCB 139.8u 139.8u 139.8u 139.8u
(b) after calibration
Vt,lin(ZBB) Vt,sat(ZBB) Vt,lin(FBB) Vt,sat(FBB) Vt,lin(RBB) Vt,sat(RBB)
Measure 0.3194 0.1413 0.2289 0.08575 0.3561 0.1585 Simulation 0.3143 0.1549 0.2369 0.0722 0.03422 0.17242
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In the following, I-V simulation was performed using BSIM-4 with the modified model parameters shown in Table 3.8.
Fig. 3.70(a),(b), and (c) present the comparison of simulated and measured Ids-Vgs at Vds=0.05V and 1.2V, under ZBB ((Vbs=0), FBB ((Vbs=0.6V), and RBB ((Vbs=-0.6V), respectively. Fig. 3.71 (a),(b), and (c) indicate simulated and measured gm-Vgs in linear and saturation regions (Vds=0.05V and 1.2V), and under DBB (ZBB, FBB, and RBB). Note that Ids-Vgs characteristics indicates excellent match between simulation and measurement.
However, gm-Vgs achieved from the first derivative of Ids vs. Vgs reveals somewhat deviation from measurement, at very high Vgs, particularly large for RBB condition. The results suggest further modification on mobility model parameters under RBB. Fig. 3.72 (a)~(c) demonstrates Ids-Vgs in semi-log scale, i.e. ogIds Vgsfrom measurement and simulation for a comparison.
The results indicate a good fitting in terms of gate swing and VT shift from VT,lin to VT,sat. Finally, the output characteristics, such as Ids-Vds from BSIM-4 simulation and measurement were shown in Fig. 3.73. Good match is demonstrated under various Vgs and specified body biases, i.e. ZBB (Vbs=0), FBB (Vbs=0.6V), and RBB (Vbs=-0.6V). The promsingly good fitting to the measured I-V and gm characteristics suggests that I-V model calibration can improve the simulation accuracy for 4-port multi-finger MOSFETs under DBB.
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0.0 0.2 0.4 0.6 0.8 1.0 1.2 0
10 20 30 40 50
60 UN65 NMOS W2N32 Vds=0.05, 1.2V Vbs=0 (ZBB)
Measured
Simulation(BSIM4)
I ds (mA)
Vgs (V)
(a)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0
10 20 30 40 50 60
Measured
Simulation(BSIM4) UN65 NMOS W2N32 Vds=0.05, 1.2V Vbs=0.6V (FBB)
I ds (mA)
Vgs (V)
(b)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0
10 20 30 40 50 60
Measured
Simulation(BSIM4) UN65 NMOS W2N32 Vds=0.05, 1.2V Vbs=-0.6V (RBB)
I ds (mA)
Vgs (V)
(c)
Fig. 3.70 UN65 NMOS W2N32, measured and simulated Ids-Vgs at Vds=0.05V and 1.2V (a)ZBB : Vbs=0V (b) FBB : Vbs=0.6V (c) RBB : Vbs=-0.6V
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Fig. 3.71 UN65 NMOS W2N32, measured and simulated gm-Vgs at Vd=0.05V and 1.2V (a)ZBB : Vbs=0V (b) FBB : Vbs=0.6V (c) RBB : Vbs=-0.6V.
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0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-4
10-3 10-2 10-1 100 101 102
Measured
Simulation(BSIM4) UN65 NMOS W2N32
Vds=0.05, 1.2V Vbs=0 (ZBB)
I d (mA)
Vgs (V)
(a)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-4
10-3 10-2 10-1 100 101 102
Measured
Simulation(BSIM4) UN65 NMOS W2N32
Vds=0.05, 1.2V Vbs=0.6V(FBB)
I d (mA)
Vgs (V)
(b)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-4
10-3 10-2 10-1 100 101 102
Measured
Simulation(BSIM4) UN65 NMOS W2N32
Vds=0.05, 1.2V Vbs=-0.6V(RBB)
I d (mA)
Vgs (V)
(c)
Fig. 3.72 UN65 NMOS W2N32, measured and simulated log(Ids)-Vgs at Vds=0.05V and 1.2V
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100
0.2V (a)ZBB : Vbs=0V (b) FBB : Vbs=0.6V (c) RBB : Vbs=-0.6V