Circuit Design

Figure 3.5 shows the block diagram of the proposed digital PWM DC–DC converter which consists of three parts: A/D converter, digital controller, and PWM generator.

3.4.1 A/D converter

This block samples V_err and I_L and transforms them into digital codes. Most of the dig-ital controllers use linear A/D converters to convert V_out to digital codes. Error voltage Verr is obtained by subtracting digitized Vout to the reference Vref. For future micro-processor voltage regulator module (VRM) applications, load current slew rates are more than 50 A/µs and regulation tolerances are less than 2 % [12]. A/D converters with high resolution and fast sampling rate are required to meet tight regulation tolerances and fast switching frequency. Although high resolution can be obtained from multistage A/D converters (pipeline and sigma-delta topology), their high conversion latency seems not suitable for real-time control. Flash topology can achieve a very high speed, low latency A/D conversion. However, its cost and power consumption grow exponentially with reso-lution. It is beneficial to avoid using these high power and expensive A/D converters. In this dissertation, a more simplified A/D conversion topology is proposed. Because Verr is the actual signal to evaluate proper duty ratio, the subtraction of V_ref and V_out is done by analog circuits. V_err is then converted into digital codes. Instead of using a full-range ADC, input range of the A/D conversion only covers the vicinity of zero. The resolution is not uniform for the input range. The mapping of V_err is partitioned into different sizes of region. As shown in Fig. 3.4, resolution is higher in the central region and lower when the error voltage is large. The basic idea is: when the error voltage is large, only the

direc-cm

Figure 3.6: Sampling and subtraction circuit for V_out.

tion and rough magnitude need to be measured. Higher resolution is needed to compute precise results only when V_out is close to V_ref. In general cases, when V_out is the signal to be converted, minimum discriminable difference of 12.5 mV at V_IN = 5V corresponds to 8–9 bits A/D conversion resolution. In addition, static and dynamic tolerances of target application determine the partition of quantization table. Therefore, large area is saved using this topology. I_L is encoded in 5-bit. Because I_L is used to reflect its extent of change, the resolution of IL need not be high.

Figure 3.6 shows the sampling and subtraction circuit for V_out. During each sampling period, it samples Vout and generates Verr by subtracting Vout from Vref. Low frequency errors such as OPAMP offset and flicker noise are canceled with the correlated double sampling (CDS) technique. The CDS technique has originally been introduced to reduce the noise produced in charged-coupled devices (CCD’s) [61]. It is widely used in

sampled-data systems and particularly in switched-capacitor (SC) circuits [62]. Assume clock phase φ₁ and φ₂ are non-overlapping and φ_1a is an early phase of φ₁. At time t = t₁, φ₁ = 1:

V_err(t₁) = V_os(t₁) (3.8)

And at time t = t₂ = t₁+ T_s/2, φ₂ = 1:

V_err(t₂) = −C1

C2(V_out− V_ref) + (1 +C1

C2)[Vos(t2) − Vos(t1)] (3.9) where Ts is the period of the clock. Therefore, if Vos doesn’t change with time, the second term would be eliminated. Then V_err will be only proportional to the difference between V_out and V_ref. NMOS switch is used for S5 to reduce parasitic capacitance in the negative input node of the opamp (VG). At the moment S5 is open, its channel charge will flow into VG and produces error voltage at output. Consequently, M5 is used to compensate this excess charge. Because both source and drain of M5 are tied together, size of M5 should be half of that of S5. To prevent channel charge of S2 to be stored in C1, VG should be floating when S2 is open. Thus, S5 should be open earlier than S2. Cf provides the OPAMP a feedback path when both φ1 and φ2 are low. Subtraction error can be as low as tenths of 1mv even when large offset exists. With careful layout techniques, matching accuracy between C1 and C2 can be better than 0.1 % [63]. This ensures adequate subtraction precision to obtain correct A/D conversion results.

Parallel comparators are used to convert Verr and IL to digital codes because their resolutions are relatively low. Low conversion latency of this “flash” conversion is desirable to reduce control latency which is especially important when the response speed is a major consideration.

Verr

K x Verrcfb K x Verrv

Clk sw

IL table

Look-up D[N:0]

shift

data_in

Shift Reg.

Figure 3.7: Circuit diagram of the digital controller.

3.4.2 Digital Controller

The digital controller performs duty ratio calculations in Eq. 3.7 which involve integration, multiplication, and addition. These numerical computations are usually performed by microcontrollers or DSPs. However, since V_err is partitioned into few regions and K_v is a constant, duty ratio increments (Kv× Verr) can be pre-calculated and stored on chip or in an external memory device. The term K_{cf b} × V_err can be also pre-calculated. These data will only occupy little memory space. An accumulator is used as the integrator.

Increments are accumulated in each switching cycle. Multiplication of Kcf b× Verr with I_L can be simplified to bit-wise shift of I_L if we choose K_{cf b}× V_err to be integer power of 2. Circuit diagram of the digital controller is shown in Fig. 3.7. An example of duty ratio calculation is shown below. Assume output resolution of duty ratio is 8 bits, we set Verr

= 0.1 V, K_v = 8, and K_{cf b} = 128. According to Fig. 3.4, V_err is in the region between 25 mV and 125 mV. Average of this region ((25 mV + 125 mV)/2 = 75 mV) is used to calculate Kv × Verr and Kcf b× Verr. That is, Kv × Verr and Kcf b × Verr are 0.6 and 9.6

respectively. K_{cf b}× V_err is approximated to 8 that is an integer power of 2. Therefore, duty ratio D[k] is generated as follows:

D[k] =

The first term is generated by the integrator and the second term is generated by the proportional current feedback. In the next cycle, assuming V_err is in the same region (Verr[k] = Verr[k + 1]), D[k + 1] will be:

Because K_v × V_err and K_{cf b} × V_err are obtained from a look-up table, only addition and bit-wise shift are performed by the control circuit. Both size and complexity of the

pwmout

Figure 3.8: N-bit counter based PWM generator.

controller are greatly reduced and can be integrated with other circuits. For flexibility in different loading conditions, tuning is done by simply changing the gain parameters stored in an external memory device.

Internal resolution of the controller is higher than the PWM generator by several bits.

It achieves finer control without losing fast response when duty increments per switching cycle are less then 1 LSB.

3.4.3 PWM Generator

The PWM generator receives duty ratio from the digital controller and modulates it to PWM signal. An N-bit counter based PWM generator is shown in Fig. 3.8. In the beginning of a switching cycle, the counter loads new duty ratio D[N : 0] and counts down. After D clock cycles, zero is detected at the output of counter. The PWM output is reset and the counter loads one’s complement of the duty ratio (D b). After D b clock cycles, the PWM output is set and the switching cycle ends. Therefore one switching period equals (D + 1) + (D b + 1) = 2^N + 1 clock cycles. Different from general counter based PWM generators, only one counter is used to count both ON and OFF duration.

Switching frequency of PWM output (f_SW) depends on the duty ratio resolution (N bits) and the input clock frequency (f_clk). Their relationship is stated below:

fSW = fclk

2^N + 1 (3.12)

Higher resolution means better control over the duty ratio. There are two reasons for the need of a high-resolution PWM generator. First, resolution of the PWM generator must be higher than the A/D converter in order to eliminate the limit cycles effect [36]. Limit cycles refer to steady-state periodic oscillations of the output voltage that are not due to the PWM switching activity. Second, since the differentiation of inductor’s current is proportional to the voltage across it, gradual change of duty ratio is needed to avoid large peak current. However, clock frequency must be doubled to increase resolution by one bit if switching frequency is kept the same. Thus, 8-bit resolution is moderate if switching frequency is around 200 kHz. For an 8-bit system with a 40 MHz clock, the duty ratios range from 1/257 to 256/257 and the switching frequency f_sw is 155.6 kHz.