應用於切換式直流至直流轉換器之高性能互補金氧半控制器

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(1)應用於切換式直流至直流轉換器之高性能互補金氧半控制器 HIGH PERFORMANCE CMOS CONTROLLERS FOR SWITCHING-MODE DC–DC CONVERTERS 研究生：左仲先指導教授：吳錦川. Student: Chung-Hsien Tso Advisor: Jiin-Chuan Wu. 國立交通大學電子工程學系電子研究所博士論文 A Dissertation Submitted to Institute of Electronics College of Electrical Engineering And Computer Science National Chiao Tung University For the Degree of Doctor of Philosophy in Electronic Engineering September 2004 Hsinchu, Taiwan, Republic of China. 中華民國九十三年九月.

(2) 應用於切換式直流至直流轉換器之高性能互補金氧半控制器研究生：左仲先. 指導教授：吳錦川. 國立交通大學電子工程學系電子研究所. 摘要本論文針對切換式直流至直流轉換器提出數種創新之高性能控制器。為了要達到快速暫態反應、高效率、穩定運作以及固定的切換頻率等需求，新型控制器的分析與設計在本論文裡有完整的探討，並利用 CMOS 類比及數位混合式積體電路技術實現控制電路。現存之自由運行控制電路具有架構簡單和反應極為快速之優點，然而切換頻率不固定，因此無法運用在對電磁干擾敏感的裝置中，同時相關的論文質與量皆相當缺乏，在理論分析方面仍有進一步探討的空間。在本論文中對於常見的兩種自由運行控制型式-漣漪控制和固定開啟時間控制進行理論研究，並針對缺點提出改進的電路架構。在固定開啟時間控制方面，設計可依據輸入輸出電壓調整開啟時間的電路，因此切換頻率幾乎不隨輸入輸出電壓以及負載電流變動。在論文中探討自由運行控制的不穩定. i.

(3) 現象，容易被回授信號上的雜訊干擾，因此提出創新的補償電路，可改善頻率響應以及雜訊免疫能力，利用內建積分器產生的斜坡信號用來觸發比較器，具有良好的雜訊免疫能力，可以達到穩定且快速的動作。控制電路利用 1 微米的互補式金氧半導體積體電路技術來實現，包含輸入輸出接腳的面積為 5.2 毫米平方，實驗結果顯示暫態反應十分快速，在輸入電壓 5 伏特，輸出電壓 2.476 伏特，負載電流 10 毫安培至 3 安培的情況下，效率可達 86 %至 93 %，負載穩壓度和線穩壓度分別為 0.032 %/A 和 0.034 %/V，均優於傳統電壓模式和電流模式的脈寬調變控制方式。在漣漪控制方面，提出了嶄新的方法，利用相鎖迴路調整延遲，用以鎖定切換頻率，並針對 buck 和 boost 兩種功率級分別提出電壓模式與電流模式之漣漪控制器。穩態反應分析、輸出電壓電流轉換函數、切換頻率函數以及頻率響應函數在論文中有推導及分析，根據頻率響應設計出補償網路，分析漣漪控制之各種特性。同時，將切換頻率與延遲的關係線性化之後，可得到一個線性模型，根據此模型，我們可以設計迴路參數和分析相鎖迴路的穩定度。穩壓器電路經由 SPICE 模擬，buck 穩壓器在輸入 20 伏特輸出 1.5 伏特的情況下，穩態切換頻率鎖定 300 kHz，負載穩壓度和線穩壓度分別為 0.0046 %/A 和 0.028 %/V；boost 穩壓器在輸入 2.4 伏特輸出 3.3 伏特的情況下，穩態切換頻率鎖定 300 kHz，負載穩壓度和線穩壓度分別為 0.96 %/A 和 0.75 %/V，其他模擬結果也包含在本論文內。傳統之類比式控制器存在調整困難，容易隨製程參數與外在環境漂移之缺點，數位式控制器則受限於電路數量較多與成本較高，針對此一問題，提出一種混合式控制電. ii.

(4) 路，利用比例式電流回授技術加速電源穩壓器之暫態反應，配合特別電路設計，簡化類比數位轉換與數位運算電路，具有架構簡單與高性能之優點，且容易調整控制參數。一般數位類比混合電路多利用電晶體等級的模擬分析系統的時域反應，在本論文中利用行為模型模擬系統的時域反應，可以大幅減少模擬的時間。控制電路利用 0.6 微米的互補式金氧半導體積體電路技術來實現，包含輸入輸出接腳的面積為 1.8 乘 1.8 毫米平方。當輸出電流由 2 安培增加至 20 安培時，輸出電壓最多降低 150 毫伏，並於 100 微秒內回到靜態容忍的界線內，大電流暫態反應符合嚴格的電源需求，並且與模擬的結果相符。. iii.

(5) iv.

(6) HIGH PERFORMANCE CMOS CONTROLLERS FOR SWITCHING-MODE DC–DC CONVERTERS. Student: Chung-Hsien Tso. Advisor: Prof. Jiin-Chuan Wu. Department of Electronics Engineering and Institute of Electronics National Chiao-Tung University. Abstract Several high performance controllers for switching-mode DC–DC converter are proposed. In order to achieve fast transient response, high efficiency, stable operation, and low switching noise, analysis and circuit design of the controllers are comprehensively investigated in this dissertation. Controllers are realized by CMOS analog and digital mixed-mode integrated circuits techniques. Free-running control is the simplest among all control topologies of switching power supply. However, the switching frequency depends on the operating conditions and power filters. Thus, the use is limited in noise sensitive devices. Besides, only few related literatures provide analytical insights into this kind of control. Two common free-running control. v.

(7) topologies, ripple control and constant on-time control, are investigated. Circuits architectures are proposed to improve these controllers. Switching frequency of the constant on-time regulator can be also stabilized by adjusting the on time according to input and output voltages. Unstable operation of free-running control due to noise on feedback signal is discussed. A novel compensation circuit is proposed to improve the frequency response and noise immunity of constant on-time control. This compensation circuit uses a built-in integrator to generate a ramp signal to trigger the comparator. Therefore, it is less susceptible to noise. Stable operation and fast response are obtained. The proposed control circuits are realized in a 1 µm CMOS technology with area of 5.2 µm2 including the I/O pads. Experimental results showed fast response during load and line transients. Efficiency from 86 % to 93 % is obtained over a load range from 10 mA to 3 A under 5 V input voltage and 2.476 V output voltage. The load and line regulations are 0.032 %/A and 0.034 %/V that are superior to conventional current-mode and voltage-mode PWM control. Switching frequency of the ripple control regulator can be synchronized by a novel method that uses a phase-locked loop to lock the switching signal with an input clock. Voltage-mode and current-mode control circuits are presented for the buck and boost power stages, respectively. Both steady-state response and small-signal model are discussed. Derived transfer functions are useful for designing the control loop and compensation network. By. vi.

(8) taking linearization of the relationship of switching frequency and delay, a linear model is obtained for loop parameter design and PLL stability analysis. The proposed regulators were simulated in transistor level using SPICE. Input voltage and output voltage are 20 V and 1.5 V respectively for the buck regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.0046 %/A and line regulation is 0.028 %/V. Input voltage and output voltage are 2.4 V and 3.3 V respectively for the boost regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.96 %/A and line regulation is 0.75 %/V. More simulation results are also shown in this dissertation. Analog controllers are sensitive to noise, process, temperature and component variations. Tuning these controllers is quite complicated as well. The uses of digital controllers are limited by their complex circuits and higher cost. In this thesis, the proportional current feedback technique is proposed to accelerate transient response of the voltage-mode switching regulators. With this technique, the complexity of analog-to-digital conversion circuits and digital computation circuits is greatly reduced. Performance can be easily tuned by adjusting the parameters. Instead of transistor-level simulation, a Matlab behavior model is build to simulate time-domain system response. Fast and accurate results can be obtained from this model. The proposed control circuits are realized in a 0.6 µm CMOS technology with area of 1.8×1.8 µm2 including the I/O pads. Experimental results showed the output voltage dropped 150 mV and recovered to static tolerance in 100 µs during a load transient from 2 A to 20 A.. vii.

(9) The performance of the regulator met strict requirements and verified the simulation results.. viii.

(10) Ðá Imagination reaches out repeatedly trying to achieve some higher level of understanding, until suddenly I find myself momentarily alone before one new corner of nature’s pattern of beauty and true majesty revealed. That was my reward. — Richard Feynman. Ê>×ØÅí°çÞ®³, >áNû`¤Ø–²=àøÑp˚, ùäBÊç XíŒ¸,«ØABíj² ³4í2-Nû, ¥…²=dÿ.ª?êA > á307õðÇÕûPÅ—Ø½Ç`¤ ØÆ`¤ 5p−`¤£ÏïC`¤ Ê^“‚ÈíNû ¤Õ´b>áÚ−Íq@È`¤, ÖVÊÚ‰ÚäD−„Ü jÞTX7óçÖ£í‡ >á307õðíÏ‰Q²= Šä²= ðJ2²= ûo²= ıp¯ ²= 1çÅJ£ïìAÊù“ø…,ín¸ÞºjÞíNù, °v> áõ²= ¶_ Ùd^ ôz¤²= Šà ¶`p Zèã `ón d ¦ vB ŒÜ†Æÿ£±NôüdJCWU Group ç!b¸FõðAºÊ ®jÞíX¶›Œ, ÊÞº,6uB|ßíF- >á!>Öíò2£¤b, éB ˜¢.ÉuKè, ø˜•V.}g)”š >áBíÂf, 8B£íÙ˙, :Kô>BÅ× >áBíðA, úBG| Ì¢`í=-, .v#8B2¥DÉa >áBí`äÓQ, ¯±´-XMOB, -Ë&OøÙB?FAÿ “You are the reason I am. You are all my reasons” >áFÊB|Ûb6Œív`, #8Å ÉaíAb ãJ¤d.#©øPBb>áíA. ˝!l 200410~. ix.

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(12) Table of Contents. 2d¿b. i. English Abstract. v. Ðá. ix. Table of Contents. xi. List of Tables. xv. List of Figures. xvii. 1 Introduction. 1. 1.1. Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1. 1.2. Trends and Challenges of Power Supply Design in Microelectronic Era . . .. 3. 1.2.1. High Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4. 1.2.2. Low Output Voltage and Low Noise . . . . . . . . . . . . . . . . . .. 4. 1.2.3. Compact Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4. 1.2.4. Fast Transient Response . . . . . . . . . . . . . . . . . . . . . . . .. 5. 1.2.5. Wide Duty Ratio Range . . . . . . . . . . . . . . . . . . . . . . . .. 5. 1.2.6. Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6. 1.3. Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6. 1.4. Research Goals and Contribution . . . . . . . . . . . . . . . . . . . . . . .. 8. xi.

(13) 1.5. Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 Switching Regulator Basics 2.1. 2.2. 9 11. Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1. Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. 2.1.2. Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Modulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1. Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . 14. 2.2.2. Pulse-Skipping Modulation (PSM) . . . . . . . . . . . . . . . . . . 14. 2.2.3. Pulse-Frequency Modulation (PFM) . . . . . . . . . . . . . . . . . 15. 2.3. Basic Converter Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 16. 2.4. Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.1. Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18. 2.4.2. Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19. 2.4.3. Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19. 2.4.4. Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 20. 2.4.5. Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . 21. 3 A Compact Digital Buck Controller with Proportional Current Feedback. 23. 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23. 3.2. Digital Control for Switching-Mode DC–DC Converter . . . . . . . . . . . 24. 3.3. Proportional Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . 25. 3.4. 3.3.1. Voltage-Mode and Current-Mode Control . . . . . . . . . . . . . . . 25. 3.3.2. Converter Load Transient Response . . . . . . . . . . . . . . . . . . 28. 3.3.3. Control Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 30. Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.1. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34. xii.

(14) 3.5. 3.4.2. Digital Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37. 3.4.3. PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39. Time Domain System Modelling and Simulation . . . . . . . . . . . . . . . 40 3.5.1. Behavior Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . 40. 3.5.2. Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42. 3.6. Experiment Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44. 3.7. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49. 4 A Frequency Stabilized Constant On-Time Controller with Low Noise Susceptibility. 51. 4.1. Constant On-Time Control and Frequency Stabilization Technique . . . . . 52. 4.2. Stability Issues of Free-Running Control . . . . . . . . . . . . . . . . . . . 54. 4.3. 4.4. 4.5. 4.2.1. Noise Induced Instability . . . . . . . . . . . . . . . . . . . . . . . . 55. 4.2.2. Loop Gain of Free-Running Regulator. . . . . . . . . . . . . . . . . 55. Compensation and Circuits Implementation . . . . . . . . . . . . . . . . . 60 4.3.1. Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62. 4.3.2. Timing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67. 4.3.3. Regulator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69. Simulation and Experiment Results . . . . . . . . . . . . . . . . . . . . . . 71 4.4.1. Steady State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73. 4.4.2. Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . 76. 4.4.3. Line Transient Response . . . . . . . . . . . . . . . . . . . . . . . . 78. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78. 5 Frequency Synchronized Ripple Controllers. 83. 5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83. 5.2. Voltage-Mode Ripple Control Buck Regulator with Fixed Output Frequency 84. xiii.

(15) 5.3. 5.2.1. Voltage-Mode Ripple Control Buck Regulators . . . . . . . . . . . . 84. 5.2.2. Circuit Design for Fixed Switching Frequency . . . . . . . . . . . . 86. 5.2.3. Phase-Locked Loop Analysis . . . . . . . . . . . . . . . . . . . . . . 93. 5.2.4. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 99. 5.2.5. Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 109. Current Mode Ripple Control Boost Regulator with Fixed Output Frequency. 5.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113. 5.3.1. Boost Converter Steady-State Analysis . . . . . . . . . . . . . . . . 114. 5.3.2. Boost Converter Small-Signal Analysis . . . . . . . . . . . . . . . . 119. 5.3.3. Current-Mode Ripple Control Boost Converter . . . . . . . . . . . . 124. 5.3.4. Circuit Design for Fixed Switching Frequency . . . . . . . . . . . . 126. 5.3.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 131. 5.3.6. Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 139. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142. 6 Conclusions and Future Works. 145. 6.1. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145. 6.2. Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148. Bibliography. 149. v. 161. Publication List. 163. xiv.

(16) List of Tables 2.1. Linear vs. switching regulators. (typical) . . . . . . . . . . . . . . . . . . . 13. 2.2. Converter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17. 3.1. Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45. 4.1. DC loop gain of buck regulator using proposed error amplifier. . . . . . . . 66. 4.2. Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72. 4.3. Performance summary and comparisons with other control schemes. . . . . 81. 5.1. Phase margins with various values of γ. . . . . . . . . . . . . . . . . . . . . 97. 5.2. Parameters of PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98. 5.3. Frequency selection guidelines [1]. . . . . . . . . . . . . . . . . . . . . . . . 100. 5.4. Parameters used in ripple control buck regulator. . . . . . . . . . . . . . . 109. 5.5. Parameters used in CMRC boost regulator.. xv. . . . . . . . . . . . . . . . . . 144.

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(18) List of Figures 2.1. Linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. 2.2. Switching regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. 2.3. Switching signal of pulse-width modulation. . . . . . . . . . . . . . . . . . 14. 2.4. Switching signal of pulse-skipping modulation. . . . . . . . . . . . . . . . . 15. 2.5. Three basic converter topologies. . . . . . . . . . . . . . . . . . . . . . . . 16. 3.1. (a) Voltage-mode PWM DC–DC converter with a synchronous buck filter. (b) Current-mode controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 26. 3.2. Actual waveform of LX when Ron of MOSFET is not zero. . . . . . . . . . 29. 3.3. Transient responses of the average inductor current (IL,avg ) and the output voltage during a load transient. . . . . . . . . . . . . . . . . . . . . . . . . 31. 3.4. Quantization table of error voltage. . . . . . . . . . . . . . . . . . . . . . . 32. 3.5. Proposed block diagram consists of: A/D converter, digital controller, and PWM generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33. 3.6. Sampling and subtraction circuit for Vout . . . . . . . . . . . . . . . . . . . . 35. 3.7. Circuit diagram of the digital controller. . . . . . . . . . . . . . . . . . . . 37. 3.8. N -bit counter based PWM generator. . . . . . . . . . . . . . . . . . . . . . 39. 3.9. Behavior model for MATLAB simulation. . . . . . . . . . . . . . . . . . . . 41. 3.10 Step load transient response. Parameters are listed in Table 3.1. (a) Output voltage. (b) Inductor current. . . . . . . . . . . . . . . . . . . . . . . . . . 42. xvii.

(19) 3.11 Zoomed waveforms of output voltage response. (a) With proportional current feedback, Vout dropped about 140 mV and returned to within static tolerance in less than 70 µs. (b) Without proportional current feedback, output voltage response didn’t meet the requirement. . . . . . . . . . . . . 43 3.12 Photomicrograph of the implemented chip. . . . . . . . . . . . . . . . . . . 45 3.13 Experiment setup.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46. 3.14 Measured step responses with proportional current feedback technique. Top: output voltage. Bottom: inductor current. . . . . . . . . . . . . . . . 47 3.15 Measured step responses without proportional current feedback technique. Top: output voltage. Bottom: inductor current. . . . . . . . . . . . . . . . 48 3.16 Measured power consumption at 2 A load. . . . . . . . . . . . . . . . . . . 49 4.1. Constant on-time buck regulator block diagram. . . . . . . . . . . . . . . . 53. 4.2. Constant on-time modulation waveform. . . . . . . . . . . . . . . . . . . . 53. 4.3. False triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56. 4.4. Ripple control regulator and modulation waveform. . . . . . . . . . . . . . 57. 4.5. Loop gain measurement of switching regulator. . . . . . . . . . . . . . . . . 59. 4.6. Loop gain of ripple control buck regulator. . . . . . . . . . . . . . . . . . . 60. 4.7. Loop gain of constant on-time control buck regulator. . . . . . . . . . . . . 61. 4.8. Gain compensated error amplifier. . . . . . . . . . . . . . . . . . . . . . . . 62. 4.9. Opamp schematic and specifications. . . . . . . . . . . . . . . . . . . . . . 63. 4.10 Simulated waveforms of error amplifier. . . . . . . . . . . . . . . . . . . . . 64 4.11 Proposed constant on-time modulation. . . . . . . . . . . . . . . . . . . . . 65 4.12 Loop gain of proposed constant on-time buck regulator. . . . . . . . . . . . 67 4.13 Duty ratio at different load currents of proposed constant on-time regulator. 68 4.14 Proposed regulator system including control IC and buck converter. . . . . 69 4.15 Waveforms in skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70. xviii.

(20) 4.16 Simulation result of digital soft-start operation. . . . . . . . . . . . . . . . 71 4.17 Chip photomicrograph of constant on-time controller. . . . . . . . . . . . . 72 4.18 Steady state waveforms at different load currents with VIN = 5 V and Vout = 1.71 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.19 Zero crossing point of inductor current at 5 mA load current. . . . . . . . . 75 4.20 Converter loop gain versus loading. . . . . . . . . . . . . . . . . . . . . . . 75 4.21 Measured efficiency versus load current with VIN = 5 V and Vout = 2.476 V. 76 4.22 Simulated load transient response. . . . . . . . . . . . . . . . . . . . . . . . 77 4.23 Measured load transient response in skip mode with VIN = 5 V and Vout = 1.71 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.24 Simulation result of line transient. . . . . . . . . . . . . . . . . . . . . . . . 80 5.1. Ripple control regulator block diagram. . . . . . . . . . . . . . . . . . . . . 84. 5.2. Output ripple of the voltage-mode ripple control regulator. . . . . . . . . . 85. 5.3. Frequency variations of the ripple control regulator. . . . . . . . . . . . . . 87. 5.4. Proposed ripple control buck regulator. . . . . . . . . . . . . . . . . . . . . 88. 5.5. Delay element.. 5.6. Phase-frequency detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90. 5.7. Charge pump and loop filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 91. 5.8. Hysteretic comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92. 5.9. Linear model of a PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89. 5.10 Switching frequency versus delay of ripple control buck regulator. . . . . . 95 5.11 Frequency response of PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.12 Required filter inductance at 200 kHz. . . . . . . . . . . . . . . . . . . . . 104 5.13 Required filter inductance at 300 kHz. . . . . . . . . . . . . . . . . . . . . 105 5.14 Required filter inductance at 450 kHz. . . . . . . . . . . . . . . . . . . . . 106 5.15 Required filter inductance at 600 kHz. . . . . . . . . . . . . . . . . . . . . 107. xix.

(21) 5.16 Comparison of allowable inductance range with different ESRs. . . . . . . . 108 5.17 Simulated load-transient responses. . . . . . . . . . . . . . . . . . . . . . . 108 5.18 Simulated line-transient responses. . . . . . . . . . . . . . . . . . . . . . . 110 5.19 Switching frequency comparison between the proposed and an original ripple control buck regulator during a line transient. . . . . . . . . . . . . . . 112 5.20 Boost converter schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.21 Boost converter waveforms in continuous conduction mode. . . . . . . . . . 115 5.22 Boost converter DC voltage gain. . . . . . . . . . . . . . . . . . . . . . . . 118 5.23 PWM switch model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.24 Effects of the RHP zero: a step increase in duty ratio causes a initial decrease in output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.25 Block diagram and waveforms of the current-mode ripple control regulator. 124 5.26 Inductor current waveform in a current-mode ripple control regulator. . . . 126 5.27 Frequency variations of the current-mode ripple control boost regulator. . . 129 5.28 Proposed frequency synchronized boost converter. . . . . . . . . . . . . . . 129 5.29 Type II error amplifier. (a)Configuration. (b)Gain and phase versus frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.30 Output voltage and inductor current waveforms of the boost converter. . . 133 5.31 Required filter inductance at 200 kHz. . . . . . . . . . . . . . . . . . . . . 136 5.32 Required filter inductance at 300 kHz. . . . . . . . . . . . . . . . . . . . . 137 5.33 Required filter inductance at 450 kHz. . . . . . . . . . . . . . . . . . . . . 138 5.34 Load transient responses: Comparison of the proposed with an original CMRC boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.35 Line transient response of proposed CMRC boost regulator. . . . . . . . . 140 5.36 Output Voltage, current command, and inductor current waveforms during line transient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141. xx.

(22) 5.37 Switching frequency comparison between proposed and an original CMRC boost regulator during line transient. . . . . . . . . . . . . . . . . . . . . . 143. xxi.

(23) Chapter 1 Introduction 1.1. Background. The rapid advances in computer, communications, and consumer electronics technology are having a major impact on our everyday lifestyle. This trend has been largely due to recent advances in emerging VLSI and ULSI semiconductor technology. While the brain of an electronic system is usually referred to the CPU, the heart of the system is the power supply. The CPU processes data and the power supply processes electric power. Due to various voltage and current requirements of different applications, design of power supply has become an important issue. Power conversion usually refers to the process of converting different forms of power supply such as AC–AC (frequency changers, cyclo-converters), AC–DC (rectifiers, off-line converters), DC–AC (inverters), or DC–DC conversion. The role of DC–DC power conversion becomes more important in these years. Electronics products need to provide high-performance capabilities at low-power dissipation levels in compact packages at affordable prices. In order to achieve faster and more efficient circuit operations, signal swing inside integrated circuits should be as low as possible.. 1.

(24) CHAPTER 1. INTRODUCTION. One dominant part of the power consumption in a CMOS circuit is the dynamic power consumption: 2 Pd ∝ f × VDD. (1.1). where f is the operating frequency and VDD is the supply voltage. It is clear from the above equation that reducing the supply voltage VDD can reduce power consumption greatly due to their squaring relationship. In analog integrated circuits, voltage reduction also provides an effective mean to reduce the power consumption if the performance degradation is accepted or compensated. The demands for higher functionality, smaller device size, and lower power dissipation have brought new technological issues. They can be resolved using more advanced semiconductor processes to implement the so-called system-on-a-chip (SOC). The processes have been improved from 0.35 µm to 0.25 µm, 0.18 µm, 0.13 µm, 90 nm and smaller for commercial products. By utilizing these advanced processes, more circuits can be implemented into one single chip and system size and complexity are greatly reduced. As the dimension of transistor continues to shrink, the gate oxide thickness of MOSFET also becomes thinner. To prevent electric breakdown, the maximum allowable supply voltage has dropped with each generation of semiconductor technology. For example, it is 3.3 V for 0.35 µm technology and 1.8 V for 0.18 µm technology. The operating voltage of an integrated circuit requires to scale down in order to maintain the reliability. Another reason to perform DC voltage conversion is supply voltage boosting in portable equipments. Small-size and light-weight portable equipments such as MP3 players, cellular phones, pagers, and personal digital assistants (PDAs) provide convenient entertainment,. 2.

(25) 1.2. TRENDS AND CHALLENGES OF POWER SUPPLY DESIGN IN MICROELECTRONIC ERA. communication, and data access functions. The size and weight limitations restrict the number of battery cells. Thus, the input voltage provided by the batteries is usually lower than the chip supply voltage. Step-up voltage conversions are required in these systems. As a result, it is a trend to drive high performance chips with an optimum operating voltage. Voltage regulators have to convert supply voltage provided by either standard system supply or batteries to various chip supply voltages. For example, in a personal computer (PC) system, there are several supply voltages required for different circuits such as 1.5 V for CPU and chipset, 2.5 V for memory module, 3.3 V and 5 V for standard logic chips. Elementary switching-mode converters have been well known since the 1970’s [2–7]. They can provide a wide range of output voltages; no matter lower or higher than the input voltage. Another feature, also the most important one, of a switching-mode converter is its dramatic improvement in weight and efficiency compared to dissipative regulators. The efficiency can often be higher than 80 % compared to 60 % (maximum) of a 5 V-to-3 V linear regulator. The efficiency of a linear regulator decreases as the difference between input and output voltage increases. Therefore, the switching-mode converter is a major choice for most power systems.. 1.2. Trends and Challenges of Power Supply Design in Microelectronic Era. In this microelectronic era, high performance, long operating time, compact size and low cost are essential factors of a successful electronic product. For example, it is expected a third generation (3G) cellular phone can process extensive multimedia data with standby. 3.

(26) CHAPTER 1. INTRODUCTION. time of a week and size of the palm [8–10]. These requirements challenge traditional power supply control techniques and converter design. In this section, trends of power supply design in microelectronic era are described.. 1.2.1. High Efficiency. While transistor numbers inside a single chip continues to double every 18 months as Moore’s Law predicts, energy density of batteries has increased little. Conversion efficiency is particularly important in battery-powered equipments. Low heat production also saves space for heat ventilation. Advanced power management techniques and converter circuits design will help to extend battery life and shrink device size.. 1.2.2. Low Output Voltage and Low Noise. In portable and high performance systems, electronic systems are designed to operate at the optimal supply voltage [11, 12]. Low operating voltage of new generation integrated circuits has set tight tolerance of converter’s output. Communication and audio circuits are also sensitive to noise interference. Low output ripple and low noise are essential. Fast transient response is required to prevent large output deviation during step load transient. In addition, fixed frequency operation of switching-mode converters is favorable, because it is easier to filter out switching noise.. 1.2.3. Compact Size. Generally, switching-mode converters are composed of many discrete components that occupy large space. Since physical size minimization is a major design objective in portable devices, reductions of external component counts and size are trends of switching-mode. 4.

(27) 1.2. TRENDS AND CHALLENGES OF POWER SUPPLY DESIGN IN MICROELECTRONIC ERA. converter design [13, 14]. Significant energy is dissipated in the parasitic impedances of external interconnection and components [15]. Therefore, integrating external components decreases energy loss. Higher switching frequency can reduce the required sizes of filter inductor and capacitor and also improve efficiency [16]. Further physical size minimization can be made by integrating controller with microprocessor or other circuits [17, 18].. 1.2.4. Fast Transient Response. Microprocessors today exhibit much heavier load and faster current slew rate. Advanced power management techniques are usually adopted. When the system is in sleep mode, some circuits are shut down and operating voltage is scaled down in order to minimize standby current. The most challenging issue comes from step load transients when the system transits from sleep mode to full loading mode. These two modes correspond to minimum and maximum loading conditions respectively. The regulator has to maintain output voltage within tight tolerance during this fast slew-rate transient. These power requirements have become new challenges [8, 19–23].. 1.2.5. Wide Duty Ratio Range. Many portable devices are powered by multiple input sources such as AC adapter and batteries. Under these conditions, range of duty ratio variation is quite large. Unstable operations are observed when using traditional PWM control especially at very low duty ratio. Wide load range also causes duty ratio to change significantly.. 5.

(28) CHAPTER 1. INTRODUCTION. 1.2.6. Digital Control. Switching-mode converters are one of the few analog parts in today’s electronic system. Due to cost and some practical issues, digital control of switching-mode converters has not been widely used. Digital control [24–37] provides versatile functions that enable more powerful features of switching-mode power supply. Sophisticated control schemes, converter status monitoring, and system integration can be easily implemented in the digital way. Fast design cycle of digital circuits is another attractive advantage. It is also less sensitive to noise, process, temperature and component variations. As the cost per transistor continuing drop with the advance of semiconductor process, above advantages have made digital control a more attractive choice for today’s switching-mode power supply.. 1.3. Motivation. A desirable controller regulates output voltage tightly in the presence of input voltage and load current variations. Voltage-mode PWM control scheme is commonly used in switching-mode power supplies. Design of this control scheme is simple and straightforward. The output voltage is controlled by directly changing the PWM duty ratio. Therefore, this control scheme is also called direct duty control. However, its application is limited because of slow response. Another popular control scheme is current-mode PWM control, which is also called current-programmed control and current-injected control, was introduced in 1978 [38–43]. This control scheme utilizes dual loops to control both output voltage and inductor current. It effectively eliminates the phase lag of the fil-. 6.

(29) 1.3. MOTIVATION. ter inductor and makes loop compensation easier. However, current sensing elements not only require additional circuitry but also reduce efficiency. Moreover, switching noise can easily corrupt the sensed current signal. Therefore, instability caused by noise is common in a current-mode system [44, 45]. Instability problem also occurs at very low duty ratio caused by high input voltages and low output voltages, which is encountered in notebook computer systems. Variable-frequency control, also called free-running control [46, 47], includes constant on-time, constant off-time control [39, 48–51], and ripple control [26, 52–57]. Free-running control is the simplest among all control topologies of switching power supply. It performs tightest control over output voltage (voltage mode) or inductor current (current mode). Main advantages of the free-running control are fast transient response and wide duty cycle range. It also eliminates the need of external compensation parts, resulting in compact size and low cost. However, the switching frequency depends strongly on the operating conditions and power filters. Thus, the use is limited in noise sensitive devices. Besides, only few related literatures provide analytical insights into this kind of control. There exist many subjects to be investigated, such as loop gain transfer function and noise immunity. Switching-mode converters have shown their advantage in conversion efficiency. Severe system requirements for future DC–DC converters demand new control schemes. Traditional methods will not yield acceptable results. Control circuit design techniques of switching-mode DC–DC converters are main concerns of this dissertation. Free-running control is a strong candidate for a high performance DC–DC converter. Switching fre-. 7.

(30) CHAPTER 1. INTRODUCTION. quency stabilization, loop gain compensation, and noise immunizing techniques of freerunning control are important topics worthy of further investigation. Digital PWM control is another topic in this dissertation. Digital control of switching-mode converters has become a popular topic in these years. The uses of digital controllers are limited by their complex circuits and higher cost. It is desirable to build a simple and integrable digital controller to provide a high performance operation.. 1.4. Research Goals and Contribution. The goals of this research are to design and analyze high performance CMOS integrated circuits for switching-mode DC–DC converters. Fast response, tight regulation, high stability, fixed frequency, and compact size are key factors of a high performance converter. Several achievements have been worked out in this research and are highlighted below: • Developed a simple and fast response digital PWM controller that utilizes proportional current feedback technique to speed up load transient responses. Novel A/D Converter design and control circuits reduce system complexity. It is particularly suitable for system integration. • Derived loop gain of free-running control. Improved noise immunity and loop gain by utilizing a novel error amplifier. Low switching noise and low output ripple make proposed regulator suitable for low voltage applications. • Developed improved ripple control regulators with fixed output frequency. This frequency synchronizing technique extends the application of ripple control regulators to noise-sensitive systems. Circuit design considerations and PLL analysis were. 8.

(31) 1.5. THESIS ORGANIZATION. presented.. 1.5. Thesis Organization. Chapter 2 introduces basic terms of the switching regulators. Some fundamental specifications and requirements of switching regulators are introduced such that limitations and trade-offs for designing can be understood easily. Chapter 3 demonstrates a digital PWM controller for high current applications. Proportional current feedback technique is introduced to achieve fast load transient response and good load regulation. Chapter 4 investigates unstable phenomenon of free-running control. A novel error amplifier is introduced to improve noise immunity and stability of the constant on-time controller. Complete control circuits are built on a single chip to verify proposed technique. Chapter 5 presents improved ripple control regulators. Ripple control regulators are simple and effective. However, their switching frequency is varying with operating conditions. Techniques to obtain frequency-synchronized operations are proposed. Analysis and simulation results are shown in this chapter. Chapter 6 concludes this dissertation.. 9.

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(33) Chapter 2 Switching Regulator Basics 2.1 2.1.1. Voltage Regulators Linear Regulators. Linear regulator is a simple, widely used DC–DC voltage regulator. Figure 2.1 illustrates a common linear power supply circuit. To provide the precise output voltage, the linear voltage regulator behaves as variable resistance between the input and the output. The linear regulators have many desirable characteristics such as low output ripple, good line and load regulation, fast transient response and low EMI. However, low efficiency limits their application. The linear device must drop the difference in voltage between the input and output. Therefore, the power dissipation is (Vin − Vout ) × Iout . The needs of heat sinks and good ventilation make them occupying more space.. 2.1.2. Switching Regulators. The switching-mode converter, also called switching regulator, consists of switching devices repetitively on and off, together with energy storage components (capacitors and inductors) to generate an output voltage. Regulation is achieved through the adjustment of duty ratio based on fed-back sample signals of the output stage. In fixed-frequency. 11.

(34) CHAPTER 2. SWITCHING REGULATOR BASICS. Iout Compensation. VIN. Error Amplifier. Cout Vout. Vref. Figure 2.1: Linear regulator.. Vout L VIN. D. C. Rload. Compensation. ERROR AMP. PWM OSC. Vref. Figure 2.2: Switching regulator.. regulators, the switching signal is adjusted through modulation of the pulse width with a fixed-frequency clock signal — this is known as pulse-width modulation (PWM) control. A PWM buck regulator is shown in Fig. 2.2. In pulse-skipping modulated (PSM) regulators, the switch pulse width and frequency are kept constant, but the output switch is gated on or off by the feedback control; while in pulse-frequency modulated (PFM) regulators, the pulse width and frequency are varying with load. Depending on the arrangement of switches and energy storage components, output voltages can be generated that are greater than or less than the input voltage. Compared. 12.

(35) 2.1. VOLTAGE REGULATORS. Table 2.1: Linear vs. switching regulators. (typical) Specification Linear Switching Line Regulation 0.02%–0.05% Load Regulation 0.02%–0.1% Output Ripple 0.5 mV–2 mV RMS Efficiency 40%–55% Power Density 0.5 W/cu. in. Transient Recovery 50 µs EMI None. 0.05%–0.1% 0.1%–1.0% 10 mV–100 mVP−P 60%–95% 2 W–10 W/cu. in. 300 µs High. with the linear regulator, PWM converter is superior in efficiency, size, and weight. With proper components, the power efficiency can be higher than 90%. This high efficiency feature makes it a popular choice in many applications. However, due to the switching operations, large ripples up to 100 mV can be observed at output. Large voltage and current swings also induce electromagnetic interference (EMI). These disadvantages make it less favorable for some applications such as communication and audio equipments. Additionally, control circuit for switching-mode power supply is usually more complex than linear regulator’s. External components such as filter inductor and capacitor are also required. In addition, transient response is slower due to the limit of the switching frequency. Table 2.1 lists some typical values of linear and switching regulators [4, 58].. In summary, switching-mode regulator is suitable for medium to high power applications. In low power applications, linear regulator is a proper choice because of its low cost. The cross point of cost-versus-power curves of switching-mode regulator and linear regulator is around 3 to 10 watts [22]. The boundary continues to decrease with the advances of technology.. 13.

(36) CHAPTER 2. SWITCHING REGULATOR BASICS. .

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(38) . . Figure 2.3: Switching signal of pulse-width modulation.. 2.2 2.2.1. Modulation Techniques Pulse-Width Modulation (PWM). The pulse-width modulation, or PWM, control technique maintains a constant switching frequency and varies the duty ratio according to output voltage and load current. Switching signal of PWM is shown in Fig. 2.3. The error voltage is modulated by a sawtooth waveform generated by an oscillator. The switching frequency is determined by the oscillator and the pulse width is controlled by the voltage error. This technique provides high efficiency at medium to high load conditions. At light load condition, reverse inductor current and switching losses degrade efficiency. Because the switching frequency is fixed, the noise spectrum is relatively narrow, allowing simple low-pass filter techniques to greatly reduce the peak-to-peak voltage ripple. For this reason, PWM is popular with telecom applications where noise interference is of concern.. 2.2.2. Pulse-Skipping Modulation (PSM). One of the simplest modulation techniques used for controlling a DC–DC Converter is pulse-skipping modulation (PSM). As shown in Fig. 2.4, in a PSM system, the switching. 14.

(39) 2.2. MODULATION TECHNIQUES. . .

(40) . Figure 2.4: Switching signal of pulse-skipping modulation.. signal has a fixed pulse width, as well as period. As long as the converter output is below the reference voltage, the PSM pulses continue to run the converter switch. Once the converter output reaches or exceeds the target, the PSM pulse is skipped. This operation will result in decreasing pulse density as the converter output reaches its target, or as the output loading decreases. When the converter output falls below the target, or as the output loading increases, the PSM pulse density will increase. However, the inductor selection is complicated, the peak-to-peak voltage ripple can be quite high, and the noise/ripple spectrum will vary greatly with the load.. 2.2.3. Pulse-Frequency Modulation (PFM). Pulse-frequency modulation is somewhat different from pulse-skipping modulation. The pulse width is variable and the pulse repetition rate is varied in accordance with load current and input/output voltages. As soon as the output voltage goes out of regulation, the switch turns on until the inductor current reaches the peak current limit [59] or until the predetermined time is up. The major drawback of PFM control is its varying switching frequency. Constant on-time control is a kind of PFM, which will be discussed. 15.

(41) CHAPTER 2. SWITCHING REGULATOR BASICS. Q. VL rL. IL. L. D. VIN. Vout rC. (a) Buck converter (down converter).. VL. rL. IL. L. D Q. VIN. Q. Rload. C. Vout. rC. Rload. C. (b) Boost converter (up converter).. D. IL. rC. VL L. VIN. C. rL. Rload. Vout. (c) Buck-boost converter (up-down converter).. Figure 2.5: Three basic converter topologies.. in Chap. 4. Switching frequency stabilizing technique of constant on-time control will be also presented in that chapter.. 2.3. Basic Converter Topologies. In this section, three basic converter types are described: the buck, boost, and buck-boost. Figure 2.5 depicts these converters. They all consist of an inductor, a capacitor, and a diode. There is also an electronic switch that is driven on and off at a high frequency (e.g.. 16.

(42) 2.3. BASIC CONVERTER TOPOLOGIES. Table 2.2: Converter characteristics. Topology. Voltage Gain. Conversion Type. Buck. Vout VIN. =D. Step-down. Boost. Vout VIN. =. Buck-boost. Vout VIN. D = − 1−D. 1 1−D. Step-up Step-up or step-down. 5 kHz–1 MHz). These topologies differ in the ways that these elements are connected. Each topology has unique properties, including the steady-state voltage conversion ratios, the nature of the input and output currents, and the character of the output voltage ripple. Another important property is the frequency response of the duty-cycle-to-output-voltage transfer function.. The output filtering capacitor C in each circuit is used to smooth out the ripple component of the output voltage due to high-frequency switching. By adding a feedback circuit (not shown in the figures), the output voltage of the converter can be regulated. In each of the converter shown in Fig. 2.5, the energy-storage inductor L can be chosen to be so large that the current in it is substantially smoothed. The buck converter, shown in Fig. 2.5(a), is characterized by a smoothed output current iout but a pulsating input current iin . The boost converter, shown in Fig. 2.5(b), is characterized by a smoothed input current but a pulsating output current. The buck-boost converter shown in Fig 2.5(c) has both pulsating input and output currents. Table 2.2 lists characteristics of these converters.. 17.

(43) CHAPTER 2. SWITCHING REGULATOR BASICS. 2.4. Performance Specifications. While designing an electronic system, output voltage and current rating are usually specified to the power supply. However, many other parameters are required to evaluate the performance of a power supply [2, 60]. In this section, some terms and definitions are described such that it will be easier to design or to evaluate a switching regulator.. 2.4.1. Efficiency. The efficiency of a power supply is defined as the ratio of the output power and input power and is calculated as follows: Efficiency =. Vout × Iout Pout × 100% = Vin × Iin Pin. (2.1). Efficiency can be regarded as the ratio of delivered power Pout to total consumed power Pin . Total power is the sum of the followings: (1) quiescent power: the quiescent current is the current flows into the chip. It is a goal of the chip designer to minimize this kind of power dissipation; (2) parasitic power: parasitic resistance in the output current path also dissipates power; (3) dynamic power: during the switching period, power is dissipated by charging/discharging gate capacitance of switching MOSFETs. It is a function of gate capacitance Cg , switching frequency fSW , and driving voltage Vdr . The relationship is shown below: Pd = Cg × Vdr2 × fSW. (2.2). ; (4)output power: power delivered to the load. An efficient power supply should transfer as much input power to the output as possible. An inefficient regulator has two major disadvantages. First, energy is wasted. This is particularly important in a battery-. 18.

(44) 2.4. PERFORMANCE SPECIFICATIONS. powered system. Second, large heat sinks and good ventilation are required, which add to the size and weight of the regulator.. 2.4.2. Load Regulation. Output voltage regulation is a regulator’s ability to maintain its output voltage within the specified tolerance under various load disturbances. A measure of this ability is output impedance of the regulator. There is usually a feedback path in a regulator to compensate for such changes and keep the output close to the nominal value. Load regulation is the percentage change in the steady state output voltage when the load current changes from its minimum value to the fully rated current. Load regulation is defined as: Load Regulation =. ∆Vout /Vnom × 100% ∆Iload. (2.3). where Vnom is the nominal output voltage.. 2.4.3. Line Regulation. Similar to the definition in the load regulation sub-section, line regulation is a measure of the effect of changes in the input voltage on the output voltage. The small signal lineto-output transfer function is called audio susceptibility. In some systems, input voltage may change as largely as 10 V. For example, in a notebook computer, the input voltage is 19 V provided by an AC adapter while it is around 8 V when battery power is used. There is a variety of methods used to specify line regulation; however, a common definition is: Line Regulation =. ∆Vout /Vnom × 100% ∆VIN. (2.4). The specification of line regulation is usually given by %/V between maximum and minimum input voltages and at a specified loading condition.. 19.

(45) CHAPTER 2. SWITCHING REGULATOR BASICS. 2.4.4. Transient Response. The transient response is a switching regulator’s response to sudden changes in load current. It is measured by the magnitude of output voltage drop and the time of recovery. The transient response relates to the bandwidth of switching regulator, output capacitor, equivalent series resistance (ESR) of output capacitor and the load current. A wide bandwidth regulator exhibits fast transient response. Limited by the bandwidth of switching frequency, switching-mode regulators are slower than linear regulators. Loop crossover frequency is typically limited to 1/5 to 1/10 of the switching frequency. Therefore, a large output filter is required to compensate slow transient response. In order to reduce overshoot and ringing in output voltage, an adequate phase margin must be obtained. Control scheme also affects loop bandwidth, for example, the current-mode control provides faster response than the voltage mode. If the output is suddenly switched from light load to full load, the shortage of the output current will cause a fall in output voltage. On the other hand, if the load is switched off, excess output current will cause a rise in the output voltage. The transient response is normally specified together with a recovery time and is stated as:. Vdev × 100% Vnom. (2.5). where Vdev is the maximum deviation from nominal output voltage Vnom at a full load transient.. 20.

(46) 2.4. PERFORMANCE SPECIFICATIONS. 2.4.5. Electromagnetic Interference (EMI). Electromagnetic interference (EMI) is a potential problem for the circuit designer. The switching process of a regulator produces voltage spikes resulting in EMI that interferes with proper operations of sensitive electronic equipments. The EMI spectrum begins at the switching frequency and often extends over 100 MHz that falls within the frequency bands commonly allocated for communications, such as low-frequency (LF), high-frequency (HF), and very-high frequency (VHF) bands. One obvious advantage of a fixed-frequency regulator is that the switching frequency and its harmonics are fixed which makes it easier to filter induced EMI.. 21.

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(48) Chapter 3 A Compact Digital Buck Controller with Proportional Current Feedback 3.1. Introduction. While most of the switching-mode controllers today are implemented by analog circuits, digital controllers begin to play important roles in this area. Although in its initial stage, digital switching regulator control provides obvious advantages over traditional analog control such as complex control algorithm and more interaction with the microprocessor. In this chapter, a digital voltage-mode PWM DC–DC converter with error-integration algorithm is presented. This architecture requires only a compact nonlinear A/D converter and few digital circuits. Components usually used by normal digital controllers such as microprocessor, DSP, and linear A/D converter are greatly reduced. Therefore, the compactness of the controller makes it feasible to integrate with other digital circuits. However, this integrator-based controller is inherently slow during load transients and is not able to meet regulation specifications of contemporary microprocessors. To improve the performance, a novel architecture using proportional current feedback is used. Although inductor current is sampled as a feedback signal, this controller is essentially a. 23.

(49) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. voltage-mode controller. In addition, the simple fashion of circuit realization is kept in this architecture. In the following section, general digital control for switching-Mode DC–DC Converter is firstly reviewed. In Sec. 3.3, the proposed control algorithm of proportional current feedback is presented. In Sec. 3.4, circuit implementation of the controller is discussed. A time domain system model that is used to simulate circuit behavior is presented in Sec. 3.5. The control chip is fabricated in a 0.6 µm digital CMOS process. In Sec. 3.6, experiment results are presented. Fast transient response proves effectiveness of the proportional current feedback technique.. 3.2. Digital Control for Switching-Mode DC–DC Converter. An analog PWM controller consists of analog circuit components such as error amplifier, comparator, and saw tooth generator. Additional components are required to compensate the two poles in the control loop caused by the buck filter. The saw tooth generator runs at a fixed frequency. Its output is compared with the error amplifier’s output. A PWM signal is generated by the comparator. Its duty ratio depends on the error amplifier’s output and its frequency is the same as the saw tooth generator. Analog controllers are sensitive to noise, process, temperature and component variations. The switching action itself is the main source of noise that pollutes the feedback signal. Tuning these controllers is quite complicated as well. While most of the controllers are designed using analog circuits, digital controllers [24–37] have become more popular nowadays. Benefiting from their programmability, digital controllers are smarter and more versatile than analog controllers are. Moreover,. 24.

(50) 3.3. PROPORTIONAL CURRENT FEEDBACK. they are less sensitive to noise and environment variations [27]. They are not limited in functions and complex computations can be performed. While most circuits in an electronic system are digital, it is much easier for a digital controller to integrate and communicate with other circuits. Further, design cycle of digital circuits is much faster than analog ones. Digital controllers are usually implemented with microprocessors or DSPs [24, 25]. In addition, A/D converters are required to convert controlled quantity, typically output voltage and inductor current. As the regulation tolerances are getting tighter, digital controllers may suffer from excessive cost and silicon area due to high resolution. Their costs are higher as compared with analog counterparts. Efforts have been made to reduce hardware complexity by exploiting a simplified A/D structure [33–36]. This kind of A/D converter will be introduced in this chapter.. 3.3 3.3.1. Proportional Current Feedback Voltage-Mode and Current-Mode Control. The voltage-mode control is a common approach used for switching regulator design [2]. The output voltage is controlled by comparing the output voltage with a reference voltage and using the resulting error to adjust the duty ratio D. Figure 3.1(a) shows a voltagemode PWM DC–DC converter with a synchronous buck filter. There is a single voltage feedback path. This negative feedback path keeps output voltage Vout track to the reference Vref . The amplified error voltage Av × Verr is then pulse-width modulated to drive the buck filter. Pulse width modulation is done by comparing the amplified error voltage with a saw-tooth waveform generated by an oscillator. The two MOSFETs conduct currents to charge and discharge node LX, respectively. During non-overlapping period. 25.

(51) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. IL. MH. LX. Vout L. DH DL VIN. ML. DRIVER. D. C. Rload Iload. Synchronous buck filter. Av x Verr. Voltage mode controller. PWM. ERROR AMP. Vref. OSC. (a) To driver. PWM. IL. Vout. Av x Verr. Current mode controller. ERROR AMP. Vref. (b). Figure 3.1: (a) Voltage-mode PWM DC–DC converter with a synchronous buck filter. (b) Current-mode controller.. 26.

(52) 3.3. PROPORTIONAL CURRENT FEEDBACK. of driver’s output, the diode provides the inductor current a continuous path. A square wave with large current driving capability is obtained at node LX. Large inductor and capacitor filter the square wave into a nearly DC voltage. Assuming all filter components are ideal, Vout would be directly proportional to D. Vout = D · VIN =. ton · VIN TS. (3.1). where VIN is the input supply voltage, TS is the period of the switching frequency, and ton is the on time of the PWM signal. Thus, this filter can transform the DC input voltage VIN down to DC output voltage Vout very efficiently. The major advantages of the voltage-mode control are simple feedback loop design and good noise margin. The PWM signal is generated from a large-amplitude saw-tooth waveform. However, any change in line or load is treated as an error of output voltage and must be corrected through the feedback loop. This means both slow line and load transient responses. Loop gain variation caused by the change in line also complicates the feedback compensation. The output filter consisting of an inductor and a capacitor adds two poles to the control loop. Thus, either dominant pole compensation or an added zero is required in the compensation. Voltage feed-forward is used to solve poor line regulation of the voltage-mode control. This is done by making the slope of the saw-tooth waveform proportional to input voltage. Therefore, the duty ratio responds to line variation immediately and loop gain is kept constant. However, application of voltage-mode control is still limited by its slow load transient response. The introduction of current-mode control alleviates major drawbacks of voltage-mode control. Figure 3.1(b) depicts a typical diagram of current-mode controller. A voltage. 27.

(53) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. signal proportional to output inductor current is used to replace the saw-tooth waveform in voltage-mode control. Because the error voltage represents the inductor current instead of output voltage, the effect of the output inductor is eliminated by the inner current control loop. Since there is only a single pole contributed by the output filter, simpler compensation and higher gain bandwidth are obtained. Fast line transient response is another advantage of the current-mode control. The rising slope of the inductor current is proportional to VIN − Vout , the duty ratio responds instantaneously to the change in input voltage. This attains to both fast response and invariable control gain with line voltage changes. Although current-mode control exhibits better dynamic performance over conventional voltage-mode control, there exists several drawbacks to a peak-sensing current-mode converter. First, open loop instability above 50 % duty ratio must be solved by slope compensation. Second, because the saw-tooth waveform derived from inductor current is small, noise will be easily inserted to the control loop, corrupting the stability. Therefore, current-mode control is not suitable for light load and wide line input/output load conditions.. 3.3.2. Converter Load Transient Response. In a real condition, transistors MH and ML in Fig. 3.1(a) act as switches but their on-state resistance RON are not zero. Figure 3.2 shows an actual waveform of LX when RON is not zero. During the on time of DH, the inductor current IL flows through MH and causes a voltage drop IL · RON = VN M OS across MH. At this time, voltage at LX is VIN − VN M OS . During the off time of DH, IL flows through ML and voltage at LX is −VN M OS . The 28.

(54) 3.3. PROPORTIONAL CURRENT FEEDBACK. t OFF. DH. tON T. DL. VIN - V NMOS. LX. 0V - V NMOS. Figure 3.2: Actual waveform of LX when Ron of MOSFET is not zero.. output voltage is the average voltage at LX. Equation 3.1 is modified to the following equation: 1 [(VIN −VN M OS )·tON +(−VN M OS )·tOF F ] TS tON · VIN − VN M OS = TS. Vout =. (3.2). From Eq. (3.1) and (3.2), assume NMOS RON = 10 mΩ and VIN = 5 V, when Iload = 0: D0 =. Vout tON,0 = VIN T. (3.3). When Iload = 20 A: Vout VN M OS tON,20 A + = V IN VIN T tON,0 20 A · 10 mΩ + = VIN T. D20A =. = D0 + 0.04. (3.4). Even though there is a large increase in Iload from 0 to 20 A, the duty ratio D only increases by 4 %. The steady state duty ratio is mainly determined by Vout /VIN . This 29.

(55) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. is one of the important features of the PWM regulator. From this point of view, the controller of a voltage-mode PWM regulator only have to make a small change in duty ratio when Iload increases from 0 to 20 A. However, owing to the nature of the LC filter, there are complicated operations between these two steady load conditions. Figure 3.3 shows transient responses of the average inductor current and the output voltage during a load transient. In the beginning of the transient, the output capacitor supplies extra current to the load because the inductor cannot provide sufficient current in a sudden. Output voltage drop V1 caused by equivalent series resistance (ESR) of the output capacitor is proportional to the load increment. Output voltage will continue to drop until the inductor current equals to the output current (t = T1 ). Dashed line represents output voltage of a slow response converter. Voltage drop V2 is deeper in the slow converter. In voltage mode, a change in load is treated as an error in output voltage. The output voltage will settle to a final value after several iterations through the control loop. The longest delay in the control loop is the LC time constant. Therefore, voltage-mode control is slow because the duty ratio is all determined by Vout .. 3.3.3. Control Architecture. In this dissertation, a simple implementation of digital voltage-mode controller is proposed. The duty ratio (D [k]) is generated from integral of error voltage (Verr ), which is stated below:. D[k] =. k X. (Kv × Verr [n]). n=0. 30. (3.5).

(56) 3.3. PROPORTIONAL CURRENT FEEDBACK. 20 Iload 0. 20A IL,avg. Vout V1 V2. T0. T1. T2. T3. Figure 3.3: Transient responses of the average inductor current (IL,avg ) and the output voltage during a load transient.. where Kv is a constant. For comparison, duty ratio of conventional digital voltage-mode control is stated below: D[k] = Kv × (Vref − Vout [k]). (3.6). There are two differences between Eqs. 3.5 and 3.6. First, Kv × Verr is equivalent to Kv × (Vref − Vout ) mathematically, but they differ in hardware realization. In Eq. 3.6, ADC input range of Vout must cover the entire input voltage that is usually 5 V because Vref may vary with application. Moreover, the resolution of the ADC must be at least 8 bits to obtain sufficient duty ratio accuracy. However, if Verr is digitized instead of Vout , ADC input range of Verr only has to cover the vicinity of zero, for example ±1 V. Second, because D[k] is an integral of Verr , the ADC resolution can be reduced with the magnitude of Verr , i.e. the resolution is decreased with increasing magnitude of Verr and vice versa. An example quantization table used in this design is shown in Fig. 3.4. The. 31.

(57) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. 0010. +1V. 0011. 0100. +0.125V. +0.25V. 1000 0111 0110 0101. 0001. 1001. 1010. +12.5mV -12.5mV. +25mV. 0. 1011. -0.125V. -25mV. 1100. -1V -0.25V. Verr = Vref - V out Figure 3.4: Quantization table of error voltage.. integrator together with the feedback loop will settle the output voltage to the final value Vref without losing accuracy. Because the controller is composed of a simplified ADC and an integrator, it requires less hardware as compared to conventional voltage-mode controllers. Owing to the high DC gain of the integrator-based controller, load regulation and line regulation of regulator are excellent. And the integration operation is insensitive to high frequency noise. However, this controller is inherently slow. It suffers from slow transient response. Therefore, proportional current feedback technique is proposed to improve the dynamic response. The proportional current feedback technique can be expressed as the following equation: D[k] =. k X. (Kv × Verr [n]). n=0. + IL [k] × Kcf b × Verr [k]. (3.7). Equation 3.7 includes two terms: The first integration term is the same as Eq. 3.5; the second term represents the proportional current feedback. Inductor current is sensed as a feedback signal. When the inductor current rises, the duty ratio will increase as well.. 32.

(58) 3.4. CIRCUIT DESIGN. A/D Converter V ref Vout. IL. Sample & Subtract. V err (T). Sample & Subtract. IL (T). Digital Controller. Parallel Comparators. Encoder. Parallel Comparators. Encoder. VCM. D[k]. Verr [k] Kv. 1/z. K cfb. PWM Generator. pwmout To filter. clk. I L [k]. Figure 3.5: Proposed block diagram consists of: A/D converter, digital controller, and PWM generator.. Proportional current feedback means the amount of current feedback is proportional to Verr . The more Vout drops, the more amount of current feedback is added to duty cycle. As discussed in the above text, while the output current increase from 0 to 20 A, the steady state duty ratio only increases by 4 %. However, during the load transient, variation of the duty ratio should be very large to prevent deep output voltage drop. Proportional current feedback accelerates recovery rate in two ways: First, inductor current variation directly affects the duty ratio. Second, voltage drop caused by the ESR is compensated by the error voltage proportional feedback. Therefore, dynamic response is improved by the proportional current feedback. When Vout approaches to Vref , the amount of current feedback is reduced gradually to keep the system stable. At the final state, the duty ratio contributed by the proportional current feedback is reduced to zero. The small duty ratio increment needed from one loading condition to another is generated by the voltage loop. This proportional feature helps the system to attain both fast transient response and stable steady state response.. 33.

(59) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. 3.4. Circuit Design. Figure 3.5 shows the block diagram of the proposed digital PWM DC–DC converter which consists of three parts: A/D converter, digital controller, and PWM generator.. 3.4.1. A/D converter. This block samples Verr and IL and transforms them into digital codes. Most of the digital controllers use linear A/D converters to convert Vout to digital codes. Error voltage Verr is obtained by subtracting digitized Vout to the reference Vref . For future microprocessor voltage regulator module (VRM) applications, load current slew rates are more than 50 A/µs and regulation tolerances are less than 2 % [12]. A/D converters with high resolution and fast sampling rate are required to meet tight regulation tolerances and fast switching frequency. Although high resolution can be obtained from multistage A/D converters (pipeline and sigma-delta topology), their high conversion latency seems not suitable for real-time control. Flash topology can achieve a very high speed, low latency A/D conversion. However, its cost and power consumption grow exponentially with resolution. It is beneficial to avoid using these high power and expensive A/D converters. In this dissertation, a more simplified A/D conversion topology is proposed. Because Verr is the actual signal to evaluate proper duty ratio, the subtraction of Vref and Vout is done by analog circuits. Verr is then converted into digital codes. Instead of using a full-range ADC, input range of the A/D conversion only covers the vicinity of zero. The resolution is not uniform for the input range. The mapping of Verr is partitioned into different sizes of region. As shown in Fig. 3.4, resolution is higher in the central region and lower when the error voltage is large. The basic idea is: when the error voltage is large, only the direc-. 34.

(60) 3.4. CIRCUIT DESIGN. C2. 1 S4. 1a_b 1. Vref. 1a. S2 Vout(T). M5. 2 S1. S3 Vcm. S5. VG Verr(T). C1 Vos. 1 2. 2. Vcm Cf. Figure 3.6: Sampling and subtraction circuit for Vout .. tion and rough magnitude need to be measured. Higher resolution is needed to compute precise results only when Vout is close to Vref . In general cases, when Vout is the signal to be converted, minimum discriminable difference of 12.5 mV at VIN = 5V corresponds to 8–9 bits A/D conversion resolution. In addition, static and dynamic tolerances of target application determine the partition of quantization table. Therefore, large area is saved using this topology. IL is encoded in 5-bit. Because IL is used to reflect its extent of change, the resolution of IL need not be high. Figure 3.6 shows the sampling and subtraction circuit for Vout . During each sampling period, it samples Vout and generates Verr by subtracting Vout from Vref . Low frequency errors such as OPAMP offset and flicker noise are canceled with the correlated double sampling (CDS) technique. The CDS technique has originally been introduced to reduce the noise produced in charged-coupled devices (CCD’s) [61]. It is widely used in sampled-. 35.

(61) CHAPTER 3. A COMPACT DIGITAL BUCK CONTROLLER WITH PROPORTIONAL CURRENT FEEDBACK. data systems and particularly in switched-capacitor (SC) circuits [62]. Assume clock phase φ1 and φ2 are non-overlapping and φ1a is an early phase of φ1 . At time t = t1 , φ1 = 1: Verr (t1 ) = Vos (t1 ). (3.8). And at time t = t2 = t1 + Ts /2, φ2 = 1: C1 (Vout − Vref ) C2 C1 )[Vos (t2 ) − Vos (t1 )] + (1 + C2. Verr (t2 ) = −. (3.9). where Ts is the period of the clock. Therefore, if Vos doesn’t change with time, the second term would be eliminated. Then Verr will be only proportional to the difference between Vout and Vref . NMOS switch is used for S5 to reduce parasitic capacitance in the negative input node of the opamp (VG). At the moment S5 is open, its channel charge will flow into VG and produces error voltage at output. Consequently, M5 is used to compensate this excess charge. Because both source and drain of M5 are tied together, size of M5 should be half of that of S5. To prevent channel charge of S2 to be stored in C1, VG should be floating when S2 is open. Thus, S5 should be open earlier than S2. Cf provides the OPAMP a feedback path when both φ1 and φ2 are low. Subtraction error can be as low as tenths of 1mv even when large offset exists. With careful layout techniques, matching accuracy between C1 and C2 can be better than 0.1 % [63]. This ensures adequate subtraction precision to obtain correct A/D conversion results. Parallel comparators are used to convert Verr and IL to digital codes because their resolutions are relatively low. Low conversion latency of this “flash” conversion is desirable to reduce control latency which is especially important when the response speed is a major consideration.. 36.