Future Works

In this dissertation, several prototypes have been developed to realize proposed control techniques. However, there are some efforts to do for better system performance: (1) Interleave topology may increase current capability and transient response; (2) An off-set reduced comparator and error correction technique can improve the accuracy of the A/D converter; (3) Integration of digital and driver circuits into the control chip will im-prove efficiency. Tapped delay line scheme for digital PWM generation is also a possible solution to increase efficiency but at the cost of more chip area [32]; (4) Feasible circuit implementation techniques are proposed in this dissertation to build fixed frequency ripple regulators. Further verification can be made on the silicon; (5) Because the current-mode ripple controller must sense the inductor current during the whole switching cycle. A resistor is placed in series with the inductor, which reduces efficiency. Current sense tech-nique without this sensing resistor is a possible way to improve the efficiency; (6) High switching frequency can further reduce component size and accelerate transient response.

Improvements on power MOSFET technology is the key to increase switching frequency.

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(A) Regular Journal Paper

Chung-Hsien Tso and Jiin-Chuan Wu, “Analysis and Implementation of Pro-portional Current Feedback Technique for Digital PWM DC–DC Converters,”

IEICE Transactions, vol.E86-C, no.11, pp.2300–2308, Nov. 2003.

(B) Brief Journal Paper

Chung-Hsien Tso and Jiin-Chuan Wu, “A Ripple Control Buck Regulator with Fixed Output Frequency,” IEEE Power Electronics Letters, vol.1, no.3, pp.61–63, Sept. 2003.

(C) International Conference Paper

1. Chung-Hsien Tso and Jiin-Chuan Wu, “An Integrated Digital PWM DC/DC Converter,” IEEE ICECS 2000, vol. 1, 2000, pp.104–107.

2. Chung-Hsien Tso and Jiin-Chuan Wu, “An Integrated Digital PWM DC/DC Converter Using Proportional Current Feedback,” IEEE ISCAS 2001, vol. 3, 2001, pp.65–68.