Design Considerations

In the previous subsection, we have demonstrated a feasible circuit configuration to re-alize fixed frequency operations. However, there are some prerequisites for the proposed technique to work properly. In this subsection, design considerations are investigated for a robust design. A design margin must be made to adapt component variations with manufacturing inaccuracy, aging and temperature.

Switching Frequency

The choice of switching frequency is a trade-off between size and efficiency. The value of the switching frequency determines the external components used in the converter, the frequencies of noise generated by the converter, and affects the performance of the con-verter. Refer to Eq. 2.2, the dynamic power dissipation is proportional to the switching frequency. However, sizes of the filter inductor and capacitor could be smaller by choosing a higher switching frequency. A well-performing high-frequency converter also has faster transient response than one of a low frequency. Table 5.3 lists frequency selection guide-lines for voltage regulator in notebook computers [1]. The boundary between high and low frequency is technology dependent. Advances in power MOSFETs improve current capability and switching efficiency thus extends the application toward higher frequencies.

Filter Capacitor

In fixed frequency regulators, the filter capacitor is selected to limit ripple voltage below the tolerance required by the specification. In a voltage-mode ripple control regulator, the output ripple is limited by the comparator hysteresis window. According to Eq. 5.2,

Table 5.3: Frequency selection guidelines [1].

Frequency Typical Comments

(kHz) Application

200 4-cell Li+ notebook Use for absolute best efficiency.

300 4-cell Li+ notebook Considered mainstream by current standards.

450 3-cell Li+ notebook For lighter load or where size is key.

600 +5 V input Allows the minimum possible size.

the filter capacitor’s ESR and ESL are the most critical parameters.

To calculate the ESR requirement, assume that the output voltage change due to the capacitor’s capacitance is much smaller than the voltage change due to the ESR, and that the capacitor’s ESL is negligible. In order to limit output voltage change within 100 mV due to a 6.5 A load step, the required ESR is:

r_C 6 ∆Vout

∆I_out = 100 mV

6.5 A = 15.4 mΩ (5.11)

The output capacitance must have sufficiently low ESR to meet output ripple and load-transient requirements. However, to maintain a fixed switching frequency, the ESR should be sufficiently high. Therefore, the switching frequency sets a minimum value of the ESR.

Assume capacitance voltage is negligible, the output voltage ripple is mainly composed of voltages across ESR and ESL. Before the delay is inserted to the control loop, the switching frequency must be higher than the target frequency. Assume the system delay is zero, from Eq. 5.2, the minimum ESR is:

rC > fSW × VIN × (VH × L − lC × VIN)

V_out× (V_IN− V_out) (5.12)

For example, minimum required ESR of the proposed design at 300 kHz is:

r_C > 300 kHz × 20 V × (20 mV × 2.2 µH − 1 nH × 20 V)

1.5 V × (20 V − 1.5 V) = 5.2 m Ω (5.13)

This ESR value can be obtained by using low ESR electrolytic or Tantalum capacitors in parallel. An ESR value close to the maximum value defined in Eq. 5.11 is suggested to ensure sufficiently high switching frequency. The actual capacitance value required relates to the physical size needed to obtain required ESR. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value. In addition, the capacitance must be high enough to absorb the inductor energy going from a full-load to no-load condition without causing a large overshoot.

ESL of the filter capacitor is another important parameter in a ripple control regulator.

The switching frequency equation Eq. 5.2 strongly depends on ESL and this parameter must be reduced to the following level:

l_C < (r_C × t_D + V_H × L × D/V_out) (5.14)

Otherwise, the voltage step across the ESL during switching exceeds the hysteresis win-dow, and the switching frequency becomes too high and uncontrollable. Typical ESL value of an SMD capacitor is around 1 nH.

Filter Inductor

In fixed frequency regulators, the choice of inductor value provides trade-offs between size and efficiency. Low inductor values cause large ripple currents, resulting in the small-est size, but poor efficiency and high output ripple. In the voltage-mode ripple control regulator, the ripple current is governed by the output voltage hysteresis and the filter

capacitor’s ESR. The inductor value affects the switching frequency. It limits how fast the output voltage traverses through the hysteresis window. As the inductance decreases, the output voltage changes faster, resulting in higher switching frequencies. Therefore, the in-ductor value is fairly critical and should be stable over the expected load and temperature range.

The minimum required inductance is one that causes the circuit to operate at the edge of critical conduction. In the buck power stage, the average output current is equal to the average inductor current, i.e. I_out(avg) = I_L(avg). At the edge of critical conduction, the average output current is equal to half of the peak-to-peak inductor current:

I_out(avg)= 1

2× ∆I = VIN− Vout

2 × L × D × T_S (5.15)

Therefore, the minimum required inductance is obtained with a given minimum output current, I_out(min):

L > V_IN− V_out

2 × I_out(min) × D × T_S ' V_out× (V_IN− V_out)

2 × V_IN × I_out(min)× f_SW (5.16) The maximum required inductance is determined by the hysteresis at a specified switching frequency. With an inductance larger than the maximum value, the switch-ing frequency will fall below the specified value. From Eq. 5.2, the output voltage ripple is equal to the hysteresis window with maximum inductance:

V_H = l_C× V_IN Lmax

+V_out× (V_IN − V_out) × r_C VIN× Lmax× fSW

(5.17)

The first term is caused by the ESL and the second term is caused by the ESR. Rearrange above equation, we have:

L 6 lC × VIN

V_H +Vout× (VIN − Vout) × rC

V_IN × V_H × f_SW (5.18)

The maximum allowable inductance is inversely proportional to V_H. Assume l_C = 1 nH, V_H = 20 mV, r_C = 15 mΩ, I_out(min) = 1.5 A, Figures 5.12 to 5.15 plot the required maximum and minimum values of the filter inductance at different switching frequencies.

The inductance value must be chosen between the lowest maximum value and the highest minimum value over the possible input voltage range at the specified switching frequency. The minimum allowable inductance is determined by the minimum output current, Iout(min). Lower Iout(min) requires higher inductance to avoid entering discontinu-ous conduction. I_out(min) is usually specified by the application. Therefore, the minimum allowable inductance is not adjustable. The maximum allowable inductance is determined by the hysteresis window, VH, and the capacitor ESR, rC. Decreasing VH lifts the upper limit of inductance but reduces noise immunity. Increasing r_C also lifts the upper limit but increases the output voltage drop during a load transient. These two parameters should be adjusted with caution.

A small VIN-to-Vout ratio also limits the choice of inductance. Refer to Fig. 5.15(c), when V_out = 2.5 V, the range of allowable inductance becomes very small if V_IN extends below 6 V. To solve this problem, increasing capacitor ESR is a possible approach because the load current is usually smaller at higher output voltage. A comparison of allowable inductance range with different ESR is shown in Fig. 5.16. If ESR is increased from 15 mΩ to 30 mΩ, maximum allowable inductance is increased. ESR can be adjusted by changing capacitance of the same material or by choosing different material.

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Figure 5.12: Required filter inductance at 200 kHz.

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Figure 5.13: Required filter inductance at 300 kHz.

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Figure 5.14: Required filter inductance at 450 kHz.

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Figure 5.15: Required filter inductance at 600 kHz.

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Figure 5.16: Comparison of allowable inductance range with different ESRs.

V_out (V)

3m 3.2m 3.4m 3.6m 10µµµµs/div

I_L (A)

Figure 5.17: Simulated load-transient responses.

Table 5.4: Parameters used in ripple control buck regulator.

Output voltage, V_out 1.5 V Input voltage, V_IN 20 V Hysteresis window, V_H 20 mV Output current, I_out 1.5–8 A Filter inductor, L 2.2 µH Filter capacitor, C 940 µF ESR of capacitor, r_C 15 mΩ ESL of capacitor, l_C 1 nH Input clock frequency, f_clk 300 kHz