Circuit Design for Fixed Switching Frequency

From Eq. (5.2), it is observed that the switching frequency is a function of internal delay which resides within the comparator and the switch driver. If total delay of the controller is controllable, the switching frequency is controllable as well. Refer to Eq. (5.2), hysteresis window, V_H, and filter inductance, L, limit the highest attainable switching frequency.

Below the limit, it is possible to fix the frequency by inserting appropriate system delay.

To control the switching frequency precisely, one straightforward approach is to cal-culate the total delay from Eq. (5.2) and subtract it to the internal delay. However, the drift of the switch driver delay and the comparator delay with supply voltage and tem-perature make this method impractical. The inserted delay value must be determined automatically by some mechanism.

Figure 5.4 shows the proposed control loop derived from the ripple control regulator.

A comparator with hysteresis is used to avoid false crossing detections caused by the noise. Different from conventional ripple controllers, a delay element is placed after the comparator. A negative feedback loop that uses a phase-frequency detector (PFD) is also added to determine the accurate delay value. The delay time caused by the delay element is directly proportional to VT H. The PFD is widely used in phase-locked loop (PLL)

V_out=2.5V

(a) Frequency vs. input voltage with different output voltages. (rC=15 mΩ) r_C=80mΩΩΩΩ

(b) Frequency vs. input voltage with different ESRs. (Vout=1.5 V).

Figure 5.3: Frequency variations of the ripple control regulator.

PFD

Figure 5.4: Proposed ripple control buck regulator.

circuits. It detects the phase/frequency differences between the clock input CLK_IN and the switching signal. If the switching signal runs slower than CLKIN, the PFD will control the low-side charge pump to discharge V_{T H}. Because delay is directly proportional to V_{T H}, decreasing V_{T H} is effectively increasing the frequency. If the switching signal is faster, it will pump VT H to increase the delay. With this mechanism, the switching frequency will be exactly the same as the clock input.

In the following paragraphs, we proceed to detail circuit design of each block in Fig. 5.4.

In order to obtain accurate system characteristics, most of the circuits are constructed by transistors.

D_b

A CMOS delay element is shown in Fig. 5.5. The delay value can be varied over a wide range by changing the control signals I_C and V_{T H}. The left side of the Fig. 5.5 is triggered by the rising edge of the input signal D and the right side is by the falling edge. Once the rising edge of D is detected, IC starts to charge Crise. When the ramp voltage Vcr exceeds the threshold voltage V_{T H}, the S-R flip-flop sets the output Q to logic high. Operations of the falling edge can be understood similarly. A delayed waveform of D is generated with identical duty ratio. The delay time, tD, is determined by IC, C, and VT H:

t_D = C × VT H

I_C (5.3)

Assume I_C = 10 µA ,C = 10 pF, and V_{T H} = 1 V, then we have t_D = 1µs. Reasonable delay time to keep a fix-frequency operation at 150 kHz–600 kHz is from 100 ns to 1 µs.

Large voltage swings are expected in Vcr and Vcf. In order to suppress the effect of channel-length modulation, cascode current sources are used. Detail circuits will be shown with the charge pump. In order to reduce charge sharing effect at node V_cr and V_cf, the current is steered to the switch during the reset mode. Small-size NMOS transistors

D Q R

D R Q 1

1 u1

u2

UP

DN delay

(a) u1

u2 UP DN

u2 u1

DN UP

(b)

Figure 5.6: Phase-frequency detector.

are recommended to implement the switches. Although smaller switches exhibit larger resistance, only capacitor discharging time is affected. It is not critical in this design.

The Charge-Pump Phase-Frequency Detector

Figure 5.6 shows the phase-frequency detector (PFD) used in the controller. The PFD comprises two D flip-flops and some resetting logic gates. The PFD is triggered by positive edges, the duty ratios of u1 and u2 are irrelevant. Thus, it is suitable for comparing PWM signals. An early arriving positive edge of u1 will set UP to high. On the other hand, an early arriving positive edge of u2 will set DN to high. Output will reset after a positive

 

Figure 5.7: Charge pump and loop filter.

edge of another input signal has arrived. A small delay is added in the reset path to eliminate the dead zone [70]. The dead zone is a non-ideal effect of PFD and charge pump. The charge pump will inject no current to the loop filter if phase error is too small. To solve this problem, UP and DN are simultaneously set high for a short time.

Figure 5.7 shows the charge pump circuit and the loop filter. The charge pump consists of two switched current sources that inject charge into or out of the loop filter and is driven by the PFD. If UP is high, the top current source charges the loop filter. If DN is high, the bottom current source discharges the loop filter. Thus, if u1 leads u2, the charge pump continues to charge the loop filters and VT H rises.

Parasitic capacitance at the drains of M1 and M2 causes charge-sharing problem that adds to static phase offset for PFD’s input [71]. To solve this problem, charge removal transistors M3 and M4 are placed to eliminate charge sharing.

The hysteretic comparator circuit is shown in Fig. 5.8(a). Two comparators are used to compare positive input with two threshold voltages vth and vtl. These two voltages constitute top and bottom threshold of the hysteresis. An opamp is used to buffer the negative input, in−. The threshold voltages are generated from the voltages across the two resistors in series. Therefore, the two threshold voltages track the negative input closely. If the positive input, in+, is higher than vth, the output is set high. If in+ is lower than vtl, the output is set low.

  





 

 

 

 





φi φo

Figure 5.9: Linear model of a PLL.

Switch Driver and Power Stage

The switch driver controls the power switches. Two N-channel MOSFETs are used as the power switches. The advantages of using an N-channel MOSFET are its low conduc-tion resistance R_DS(on) and low cost (compared to a P-channel MOSFET with the same RDS(on)). However, a driving voltage higher than the input voltage is required to fully turn on the high-side NMOS. Bootstrap is a common technique to obtain a high driving voltage by pumping the input voltage [1]. In addition, a dead time must be inserted between on-times of the high-side and low-side driving signals to prevent short current.

Real MOSFET models from the vendors are used in the simulation. The switch driver is not implemented and is modeled by an ideal voltage-controlled voltage source with finite output resistance and internal delay.