Error Amplifier

Figure 4.8: Gain compensated error amplifier.

In this section, the circuit implementation of the proposed loop gain compensated constant on-time controller is presented. Emphasis will be put on the design and loop gain analysis of the error amplifier. In the proposed design, current signal is constructed from integration of LX − V_out. Resetting mechanism and output error correcting loop are built in the error amplifier. Peripheral circuits such as timing circuits, pulse-skipping select circuit, and soft start circuit will also be addressed.

4.3.1 Error Amplifier

Figure 4.8 shows schematic of the error amplifier. Figure 4.9 shows schematic and spec-ifications of the operational amplifier used in the error amplifier. V 1 is negative integral of LX − V_out. At the beginning of the on state, a short pulse resets V 1 to V_out. During on state, V 1 ramps down from V_out with a slope proportional to V_out− V_IN. During off state, V 1 ramps up with a slope proportional to Vout. A2 and Q1 generate a current flowing through R1 and the magnitude is (V_out − V 1)/R1. This current is proportional to the AC component of V1 and can be seen as the reconstructed inductor current ripple. If the current mirrors IB are matched, I2 equals to I1. A voltage, V 2, contains the information

V_DD

Figure 4.9: Opamp schematic and specifications.

of both inductor AC current and output voltage DC error is obtained by forcing I2 to flow through R2 and is described below:

V 2 = V_{f b}− R2

R1(V 1 − V_out) (4.6)

The DC error feedback is used to achieve good voltage regulation. Loop gain compensation is done by changing V 2’s AC ripple that is proportional to RC values. The use of lateral PNP bipolar transistor Q1 extends the output voltage range to as low as one V_be(sat) (0.6 V). The lateral PNP transistor is available in CMOS process by exploiting parasitic device that exists in PMOS structure.

Waveforms of error amplifier are shown in Fig. 4.10. V 2 is compared with the reference voltage. If V 2 falls below V_ref, the comparator will trigger a new cycle. The positive edge of V_e triggers the one-shot timer that generates on-time pulses. Because the ripple is constructed from integration of large signal, LX, the modulation is much less sensitive

V2

V1 V_out V_ref V_fb

LX

V_e

Figure 4.10: Simulated waveforms of error amplifier.

to noise as compared with traditional constant on-time control. Due to large amplitude of the input signal, strict requirements of comparator are alleviated. A comparator with lower power and slower speed can be used here. Because the output voltage is used as an average value instead of a modulating ripple, output ripple of the converter can be further reduced. Therefore, the proposed design is suitable for low voltage applications.

As discussed in Sec. 4.2.2, modulation gain is inversely proportional to ramp slope.

Loop gain of constant on-time controller can be compensated by adjusting integrator’s RC value in error amplifier. Proposed modulation waveforms are shown in Fig. 4.11. A disturbance ∆V on reference voltage causes a change in switching period ∆T . Because



Figure 4.11: Proposed constant on-time modulation.

on time is fixed, ∆T is determined by the slope of V 2 during off time:

∆T = ∆V

In steady state, the relationship between output voltage and input voltage is:

V_out = T_ON

T V_IN (4.8)

New output voltage due to ∆T is:

V_out⁰ = T_ON

By combining Eqs. 4.7 and 4.9, the change in output voltage is:

∆V_out = V_out⁰ − V_out= V_out∆T

T = R1 R2

R_{IN T}C_{IN T}

T ∆V

Therefore, loop gain is the product of ∆V_out/∆V , feedback network gain V_ref/V_out, and

Table 4.1: DC loop gain of buck regulator using proposed error amplifier.

V_IN V_out f_SW = 1/T L R1/R2 R_{IN T}C_{IN T} Loop Gain Predicted

20 V 1.8 V 300 kHz 2.2 µH 2 24 µs 10.2 9.6

8 V 1.8 V 300 kHz 2.2 µH 2 24 µs 10.1 9.6

8 V 2.5 V 300 kHz 2.2 µH 2 24 µs 7.27 6.91

20 V 1.8 V 300 kHz 4.4 µH 2 24 µs 11.1 9.6

20 V 1.8 V 600 kHz 2.2 µH 2 24 µs 20.2 19.2

20 V 1.8 V 300 kHz 2.2 µH 2 48 µs 20.0 19.2

LC filter transfer function H(s):

T (s) = V_ref V_out

R1 R2

R_{IN T}C_{IN T}

T H(s) (4.10)

where V_ref is bandgap reference voltage 1.2 V. According to Eq. 4.10, Table 4.1 lists sim-ulated DC loop gains under different conditions. Simulation reveals the same relationship as was predicted. DC loop gain is independent of ESR, input voltage, and inductor value.

Therefore, output ripple can be reduced by choosing larger inductor and lower ESR val-ues, which may cause instability in traditional constant on-time control. Figure 4.12 plots simulated loop gain versus the results predicted from Eq. 4.10 with parameters listed in the first row of Table 4.1 and a 940 µF filter capacitor with 15 mΩ ESR.

DC gain of the compensated regulator is about 20 dB. In common voltage-mode PWM converters, DC gains are usually set at 40–60 dB as a rule of thumb. High loop gain reduces load regulation error but decreases phase margin. However, in free-running control, load regulation is not directly related to DC gain. Figure 4.13 illustrates relationship of duty ratio and load current in constant on-time control. Refer to Fig. 3.2 , an increase in load current is effectively a decrease in input voltage, which is described below:

∆VIN = −∆Iload× RON (4.11)

100 1k 2k 3k 4k 5k 7k 10k

Figure 4.12: Loop gain of proposed constant on-time buck regulator.

Because rising slope of output voltage is directly proportional to V_IN − V_out, the rising slope of output voltage with higher load current, V_out⁰ , is smaller. Because T_ON is fixed, V_out⁰ increases less than V_outduring on time. During off time, falling slopes of both V_out⁰ and V_out are the same. As a result, period becomes shorter and duty ratio becomes larger with increasing load current. The increased duty ratio compensates for the increased loading.

Therefore, load regulation is good in proposed control in despite of its low DC gain.